Overview

Description

This compact SMARC 2.1 System on Module (SoM) incorporates a Renesas RZ/A3UL microprocessor for RTOS applications. This system design architecture provides a complete power and timing tree. It is targeted for real-time human machine interface (HMI) applications, such as smart homes/buildings or industrial terminals.

System Benefits​:

  • RTOS operating system
  • Single Arm® Cortex®–A55 configurations for low power consumption
  • Support for multiple memories: Octal Flash and RAM, DDR, QSPI, eMMC
  • Single programmable clock generator
  • Multiple communication interface support: USB, Ethernet, CAN, Wi-Fi/Bluetooth® Low Energy (LE)

Comparison

Applications

Applications

  • Human machine interface (HMI)
  • Embedded vision application
  • Barcode scanners
  • Industrial gateways

Winning Combinations Interactive Diagram

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4:3 ratio Level Shifter Level Shifter Level Shifter Sheet.1 Sheet.2 Sheet.3 Sheet.4 US221 US221 US221 DDR4 DDR4 DDR4 QSP QSP QSP eMMC eMMC eMMC uSD uSD uSD Ethernet PHY Ethernet PHY Ethernet PHY Ethernet PHY Ethernet PHY Ethernet PHY Power/Reset/Boot SW Power/Reset/Boot SW Power/Reset/Boot SW Power/Reset/Boot SW Power/Reset/Boot SW Power/Reset/Boot SW US 222 Carrier Board Carrier Board Carrier Board Sheet.22 Sheet.23 Sheet.24 Sheet.26 Sheet.29 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.50 Sheet.51 Sheet.52 Sheet.53 Sheet.54 Sheet.55 Sheet.56 Sheet.57 Sheet.58 Sheet.59 Sheet.60 Sheet.61 Sheet.62 Sheet.63 Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Sheet.69 Sheet.70 Sheet.72 Sheet.73 Sheet.74 Sheet.75 Sheet.76 Sheet.77 Sheet.78 Sheet.79 Sheet.80 Sheet.81 Sheet.82 Sheet.83 Sheet.84 Sheet.85 VTT VTT VTT VTT (0.5*VDDQ) VTT (0.5*VDDQ) VTT (0.5*VDDQ) DDR VTT Power DDR VTT Power DDR VTT Power PG00D PG00D PG00D Connector 1.119 Sheet.113 Connector 1.140 Connector 1.141 DDR VPP (2.5V) DDR VPP (2.5V) DDR VPP (2.5V) VCore (1.1V) VCore (1.1V) VCore (1.1V) VDDQ (1.2V) VDDQ (1.2V) VDDQ (1.2V) D3.3V (3.3V) D3.3V (3.3V) D3.3V (3.3V) SD Card0 (1.8V/3.3V) SD Card0 (1.8V/3.3V) SD Card0 (1.8V/3.3V) 24MHz 24MHz 24MHz Audio Audio Audio Audio Audio Audio RTC RTC RTC Audio Audio Audio 25MHz, 3.3V 25MHz/3.3V 25MHz/3.3V 25MHz, 3.3V 25MHz/3.3V 25MHz/3.3V Octa Flash Octa Flash Octa Flash Octa RAM Octa RAM Octa RAM LDO LDO LDO Boot Logic/SD Select Boot Logic/SD Select Boot Logic/SD Select Power/RESET Logic Power/ Reset Logic Power/Reset Logic Sheet.169 Sheet.170 USB Logic USB Logic USB Logic Sheet.174 Sheet.175 Sheet.176 Sheet.177 Sheet.178 Sheet.179 Connector 1.180 Connector 1.181 Sheet.186 Sheet.188 Sheet.189 Sheet.190 Sheet.191 Sheet.192 Sheet.194 Sheet.196 Sheet.197 Sheet.198 Connector 1 Connector 1.200 Connector 1.202 Connector 1.203 Connector 1.204 Connector 1.205 Connector 1.206 Connector 1.207 Sheet.208 Sheet.209 Sheet.210 Sheet.211 SD Card1 (1.8V/3.3V) SD Card1 (1.8V/3.3V) SD Card1 (1.8V/3.3V) Ether0 (1.8V/2.5V/3.3V) Ether0 (1.8V/2.5V/3.3V) Ether0 (1.8V/2.5V/3.3V) D1.8V(1.8V) D1.8V(1.8V) D1.8V(1.8V) VIN VIN VIN Connector 1.216 Connector 1.217 Clock Clock Clock PMIC PMIC PMIC PMIC LD01 LD01 LD01 Buck1 Buck1 Buck1 Buck2 Buck2 Buck2 Buck3 Buck3 Buck3 Buck4 Buck4 Buck4 LD02 LD02 LD02 I2C I2C I2C NRSET NRSET NRSET Buckx/VIN Buckx/VIN Buckx/VIN LD03 LD03 LD03 LD04 LD04 LD04 WTD WTD WTD NRSETREQ NRSETREQ NRSETREQ GPIO GPIO GPIO MPU MPU MPU MPU DBSC DBSC DBSC QSPI QSPI QSPI SDHI SDHI SDHI UART UART UART CAN CAN CAN MMC* MMC* MMC* I2C I2C I2C SPI SPI SPI I2C/UART I2C/UART I2C/UART SDHI*/USB UART SDHI*/USB UART SDHI*/USB UART Parallel IF Parallel IF Parallel IF MIPI/CS12 Parallel MIPI/CS12 Parallel MIPI/CS12 Parallel SSI SSI SSI USB 2.0 USB 2.0 USB 2.0 EXTAL EXTAL EXTAL Ether MAC Ether MAC Ether MAC Ether MAC Ether MAC Ether MAC USB 2.0 USB 2.0 USB 2.0
Exiting Interactive Block Diagram