* PSpice Model Editor - Version 16.6.0 *$ .SUBCKT ISL70419SEH 1 2 3 4 5 * | | | | | * | | | | Output * | | | Negative Supply * | | Positive Supply * | Inverting Input * Non-inverting Input * * ************************** LICENSE STATEMENT ************************** * *The information in the SPICE model is protected under United *States copyright laws. Intersil Corporation hereby grants users of *this macro-model, hereto referred to as “Licensee”, a *nonexclusive, nontransferable licence to use this model, as long *as the Licensee abides by the terms of this agreement. Before *using this macro-model, the Licensee should read this license. If *the Licensee does not accept these terms, permission to use the *model is not granted. * *The Licensee may not sell, loan, rent, or license the *macro-model, in whole, in part, or in modified form, to anyone *outside the Licensee’s company. The Licensee may modify the *macro-model to suit his/her specific applications, and the *Licensee may make copies of this macro-model for use within *their company only. * *This macro-model is provided “AS IS, WHERE IS, AND WITH NO *WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, *INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF *MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” *In no event will Intersil be liable for special, collateral, incidental, *or consequential damages in connection with or arising out of *the use of this macro-model. Intersil reserves the right to make *changes to the product and the macro-model without prior *notice. *********************************************************************** * * * The following op-amps are covered by this model: * ISL70419SEH * * Date of model creation: 8/6/2012 * Level of Model Creator: 4.1 * * Revision History: * REV A: 16-JULY-12, Initial Input from Model Creator Rev 4.1 * * * * * Recommendations: * Use PSPICE (or SPICE 2G6; other simulators may require translation) * For a quick, effective design, use a combination of: data sheet * specs, bench testing, and simulations with this macromodel * For high impedance circuits, set GMIN=100F in the .OPTIONS statement * * Supported: * Typical performance for temperature range (-40 to 125) degrees Celsius * DC, AC, Transient, and Noise analyses. * Most specs, including: offsets, DC PSRR, DC CMRR, input impedance, * open loop gain, voltage ranges, supply current, ... , etc. * Temperature effects for Ibias, Iquiescent, Iout short circuit * current, Vsat on both rails, Slew Rate vs. Temp and P.S. * * Not Supported: * Some Variation in specs vs. Power Supply Voltage * bias current cancellation cirui * Vos distribution, Ib distribution for Monte Carlo * Distortion (detailed non-linear behavior) * Some Temperature analysis * Process variation * Behavior outside normal operating region * * Known Discrepancies in Model vs. Datasheet: * Only analog functions modelled. CS ignored. * Saturation recovery model does not accurately predict recovery time. * * * Input Stage V10 3 10 -210M R10 10 11 69.0K R11 10 12 69.0K G10 10 11 10 11 1.44M G11 10 12 10 12 1.44M C11 11 12 115E-15 C12 1 0 6.00P E12 71 14 POLY(6) 20 0 21 0 22 0 23 0 26 0 27 0 0.00 1.23 1.23 1.23 1.23 1 1 G12 1 0 62 0 1m G13 1 2 63 0 1u M12 11 14 15 15 NMI M14 12 2 15 15 NMI G14 2 0 62 0 1m C14 2 0 6.00P I15 15 4 500U V16 16 4 10.0M GD16 16 1 TABLE {V(16,1)} ((-100,-100E-15)(0,0)(1m,1u)(2m,1m)) V13 3 13 -10.0M GD13 2 13 TABLE {V(2,13)} ((-100,-100E-15)(0,0)(1m,1u)(2m,1m)) R71 1 0 10.0E12 R72 2 0 10.0E12 R73 1 2 10.0E12 *C13 1 2 3.00P * * Noise, PSRR, and CMRR I20 21 20 423U D20 20 0 DN1 D21 0 21 DN1 I22 22 23 1N R22 22 0 1k R23 0 23 1k G26 0 26 POLY(2) 3 0 4 0 0.00 -3.16U -3.16U R26 26 0 1 G27 0 27 POLY(2) 1 0 2 0 -1.12U 17.7N 17.7N R27 27 0 1 * * Open Loop Gain, Slew Rate G30 0 30 12 11 1 R30 30 0 1.00K G31 0 31 3 4 0.00 I31 0 31 DC 110 R31 31 0 1 TC=3.77M,-3.17U GD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2)) G32 32 0 3 4 0.00 I32 32 0 DC 107 R32 32 0 1 TC=3.82M,-3.75U GD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n)) G33 0 33 30 0 1m R33 33 0 1K G34 0 34 33 0 17.7 R34 34 0 1K C34 34 0 1.66M G37 0 37 34 0 1m R37 37 0 1K C37 37 0 58.9P G38 0 38 37 0 1m R38 39 0 1K L38 38 39 159N E38 35 0 38 0 1 G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(5.00,1n))(5.5,1)) G36 33 0 TABLE {V(35,4)} ((-5.5,-1)((-5.00,-1n)(0,0)(1,1n)) * * Output Stage R80 50 0 100MEG G50 0 50 57 96 2 R58 57 96 0.50 R57 57 0 100 C58 5 0 2.00P G57 0 57 POLY(3) 3 0 4 0 35 0 0 3.75M 5.00M 10.0M GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) E55 55 0 POLY(2) 3 0 51 0 -1.27 1 -25.8M E56 56 0 POLY(2) 4 0 52 0 1.27 1 -25.8M R51 51 0 1k R52 52 0 1k GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1)) GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) G53 3 0 POLY(1) 51 0 -500U 1M G54 0 4 POLY(1) 52 0 -500U -1M * * Current Limit G99 96 5 99 0 1 R98 0 98 1 TC=-4.72M,10.7U G97 0 98 TABLE { V(96,5) } ((-40.0,-50.0M)(-1.00M,-49.5M)(0,0)(1.00M,49.5M)(40.0,50.0M)) *E97 99 0 VALUE { V(98)* LIMIT(((V(3)-V(4))*0.00 + 1.00),0.05,1E6)} E97 99 0 VALUE { V(98)* LIMIT(((V(3)-V(4))*0.00 + 1.00),0.00,1E6) * + LIMIT(((V(3)-V(4))*800M + -800M),0,1)} D98 4 5 DESD D99 5 3 DESD * * Temperature / Voltage Sensitive IQuiscent R61 0 61 1 TC=3.53M,-2.13U G61 3 4 61 0 1 G60 0 61 TABLE {V(3, 4)} + ((0,0)(500M,4.6U)(2.25,440U)(5.00,445U) + (7.5,450U)(10.0,455U)(15.0,460U)) * * Temperature Sensitive offset voltage I73 0 70 DC 1uA R74 0 70 1 TC=100M E75 1 71 70 0 1 * * Temp Sensistive IBias *I62 0 62 DC 1uA I62 0 62 DC 1000uA R62 0 62 REXP 44.11629U * * Temp Sensistive Offset IBias I63 0 63 DC 1uA R63 0 63 2.5 TC=15.7M,-23.6U * * Models .MODEL NMI NMOS(L=2.00U W=42.0U KP=200U LEVEL=1 ) .MODEL DESD D N=1 IS=1.00E-15 .MODEL DN1 D IS=1P KF=40.0E-18 AF=1 .MODEL REXP RES TCE= 1.81909 .ENDS ISL70419SEH *$