概览

简介

13-bit to 26-bit registered buffer designed for 2.3V-2.7V VDD for PC1600 - PC2700 and 2.5V-2.7V VDD for PC3200, and supports low standby operation. All data inputs and outputs are SSTL_2 level compatible with JEDEC standard for SSTL_2.

特性

  • Differential clock signals
  • Meets SSTL_2 signal data
  • Supports SSTL_2 class I specifications on outputs
  • Low-voltage operation
  • VDD = 2.3V to 2.7V
  • Available in 64 pin TSSOP and 56 pin MLF packages
  • Exceeds ICSSSTVN16859 performance

产品对比

应用

文档

类型 文档标题 日期
数据手册 PDF 422 KB
End Of Life Notice PDF 160 KB
产品变更通告 PDF 611 KB
产品变更通告 PDF 611 KB
产品变更通告 PDF 95 KB
产品变更通告 PDF 50 KB
产品变更通告 PDF 361 KB
7 items

设计和开发

模型