概览

简介

The CD4042BMS radiation hardened Quad D latch contains four latch circuits, each strobed by a common clock. Complementary buffered outputs are available from each circuit. The impedance of the n- and p-channel output devices is balanced and all outputs are electrically identical.

特性

  • High-Voltage Type (20V Rating)
  • Clock Polarity Control
  • Q and Q Outputs
  • Common Clock
  • Low Power TTL Compatible
  • Standardized Symmetrical Output Characteristics
  • 100% Tested for Quiescent Current at 20V
  • Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25 °C
  • 5V, 10V, and 15V Parametric Ratings
  • Noise Margin (Over Full Package Temperature Range):
    • 1V at VDD = 5V
    • 2V at VDD = 10V
    • 2.5V at VDD = 15V
  • Meets All Requirements of JEDEC Tentative Standard No.  13B,  "Standard  Specifications  for  Description  of 'B' Series CMOS Devices"

产品对比

应用

应用

  • Buffer Storage
  • Holding Register
  • General Digital Logic

文档

类型 文档标题 日期
手册 PDF 467 KB
手册 PDF 4.85 MB
Price Increase Notice PDF 360 KB
其他
白皮书 PDF 533 KB
Product Advisory PDF 499 KB
产品变更通告 PDF 230 KB
应用文档 PDF 338 KB
应用文档 PDF 224 KB
9 items

设计和开发

模型