概要

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 400MHz (DDRII 800)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Programmable skew through SMBus
  • Frequency defect control through SMBus
  • Individual output control programmable through SMBus

ドキュメント

設計・開発

ECADモデル

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ECADモデルを調べる
Diagram of ECAD Models

製品選択

    Processing table
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    ご購入 / サンプル
    型名
    9P935AFLF
    circle廃止品
    memory
    view_in_ar
    		SSOP 28 C Yes Tube
    9P935AFLFT
    circle廃止品
    memory
    view_in_ar
    		SSOP 28 C Yes Reel
    9P935AGLF
    circle廃止品
    memory
    view_in_ar
    		TSSOP 28 C Yes Tube
    9P935AGLFT
    circle廃止品
    memory
    view_in_ar
    		TSSOP 28 C Yes Reel
    Parametric Table tips

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