Tsi381 Pinlist -- (Document 80E2000_PN002_03) Copyright © 2009 Integrated Device Technology, Inc.All Rights Reserved. Revision History: 80E2000_PN002_03 - July 2009, This document was updated for IDT formatting. There have been no technical changes. GENERAL DISCLAIMER Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as "reserved" or "undefined" are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk. The IDT logo is registered to Integrated Device Technology, Inc. IDT and CPS are trademarks of Integrated Device Technology, Inc. “Accelerated Thinking” is a service mark of Integrated Device Technology, Inc. Pin Signal -------------------- A1 SR_DOUT A2 SR_DIN A3 TEST_ON A4 PCIE_TXD_n A5 VDD_PCIE A6 PCIE_REFCLK_p A7 VDD_PCIE A8 PCIE_RXD_p A9 N/C A10 GPIO[1] A11 GPIO[3] A12 VSS_IO B1 TEST_BIDR_CTL B2 SR_CLK B3 VDD_PCI B4 VSS B5 PCIE_TXD_p B6 PCIE_REFCLK_n B7 PCIE_RXD_n B8 VSS B9 N/C B10 GPIO[2] B11 VDD_PCI B12 PCIE_PERSTn C1 PCI_AD[1] C2 PCI_CLKO[1] C3 VSS_IO C4 SR_CSn C5 VSS C6 VSS C7 VSSA_PLL C8 TEST_BCE C9 GPIO[0] C10 VDD C11 VSS_IO C12 NC D1 PCI_AD[2] D2 PCI_AD[3] D3 PCI_AD[0] D4 VDD D5 VDD_PCIE D6 VSS D7 VSS D8 TEST_SPARE[1] D9 VSS D10 PCI_M66EN D11 PCI_INTCn D12 PCI_CLK E1 PCI_AD[4] E2 PCI_AD[5] E3 PCI_AD[6] E4 PCI_AD[7] E5 VDDA_PCIE E6 VSS E7 VDDA_PLL E8 N/C E9 PCI_INTBn E10 PCI_INTDn E11 PCI_GNTn[3] E12 PCI_INTAn F1 PCI_CBEn[0] F2 PCI_AD[8] F3 PCI_AD[9] F4 PCI_AD[10] F5 VIO_PCI F6 VDD F7 VSS F8 VDD F9 VDD_PCI F10 PCI_RSTn F11 PCI_GNTn[2] F12 VSS_IO G1 PCI_AD[11] G2 PCI_AD[12] G3 PCI_AD[13] G4 VDD_PCI G5 VSS G6 VDD G7 VDD G8 VIO_PCI G9 PCI_GNTn[1] G10 PCI_GNTn[0] G11 PCI_REQn[0] G12 PCI_REQn[2] H1 PCI_AD[14] H2 PCI_AD[15] H3 PCI_CBEn[1] H4 VSS H5 VDD_PCI H6 VIO_PCI H7 VSS H8 VDD_PCI H9 PCI_REQn[1] H10 PCI_CLKO[0] H11 PCI_REQn[3] H12 PCI_PMEn J1 PCI_PAR J2 PCI_SERRn J3 PCI_PERRn J4 VSS_IO J5 PCI_AD[16] J6 PCI_AD[20] J7 VDD_PCI J8 VSS_IO J9 VDD J10 PCI_AD[31] J11 PCI_AD[29] J12 PCI_AD[30] K1 TEST_SPARE[2] K2 VSS_IO K3 VDD K4 PCI_DEVSELn K5 PCI_CBEn[2] K6 PCI_AD[19] K7 PCI_AD[23] K8 PCI_AD[25] K9 N/C K10 VSS_IO K11 PWRUP_EN_ARB K12 PCI_AD[28] L1 JTAG_TDO L2 VDD_PCI L3 JTAG_TDI L4 PCI_STOPn L5 PCI_IRDYn L6 PCI_AD[17] L7 PCI_AD[22] L8 PCI_AD[24] L9 PCI_AD[27] L10 JTAG_TRSTn L11 NC L12 NC M1 PWRUP_PLL_BYPASS M2 JTAG_TCK M3 PCI_LOCKn M4 PCI_TRDYn M5 PCI_FRAMEn M6 PCI_AD[18] M7 PCI_AD[21] M8 PCI_CBEn[3] M9 PCI_AD[26] M10 VDD_PCI M11 TEST_SPARE[0] M12 JTAG_TMS