Tsi382-66CQY Pinlist (Document 80E2020_PN002_02)
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Copyright © 2009 Integrated Device Technology, Inc.All Rights Reserved.

GENERAL DISCLAIMER
Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT.  IDT products may contain errata which can affect product performance to a minor or immaterial degree.  Current characterized errata will be made available upon request.  Items identified herein as "reserved" or "undefined" are reserved for future definition.  IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items.  IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property.  Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk.

The IDT logo is registered to Integrated Device Technology, Inc. IDT and CPS are trademarks of Integrated Device Technology, Inc.
 
“Accelerated Thinking” is a service mark of Integrated Device Technology, Inc.

Revision History
---------------------

80E2020_PN002_02 - July 2009,  This document was updated for IDT formatting. There have been no technical changes.

80E2020_PN002_01, March 2008 - This is the first version of the document. It supports the LQFP package variant of the Tsi382. 


Pin #	Signal Name
---------------------

1	VSS
2	VSS
3	VSS
4	VSS
5	VSS
6	GPIO[0]
7	VDD
8	VSS
9	GPIO[2]
10	GPIO[3]
11	GPIO[1]
12	TEST_SPARE[1]
13	VSS
14	VDDA_PLL
15	TEST_BCE
16	VSSA_PLL
17	VSS
18	VDD_PCIE
19	VDDA_PCIE
20	VSS
21	PCIE_REFCLK_p
22	PCIE_REFCLK_n
23	VSS
24	PCIE_REXT
25	VSS
26	PCIE_RXD_n
27	PCIE_RXD_p
28	VSS
29	PCIE_TXD_p
30	PCIE_TXD_n
31	VSS
32	VDDA_PCIE
33	VDD_PCIE
34	VSS
35	TEST_ON
36	VDD
37	SR_DIN
38	SR_CSn
39	VSS
40	VSS
41	VSS
42	VSS
43	VSS
44	VSS
45	VSS
46	VSS
47	SR_DOUT
48	SR_CLK
49	TEST_BIDR_CTL
50	VSS
51	PCI_CLKO[1]
52	PCI_AD[7]
53	PCI_AD[1]
54	VDD_PCI
55	VSS
56	PCI_AD[0]
57	PCI_AD[3]
58	VDD
59	VSS
60	PCI_AD[2]
61	PCI_AD[6]
62	PCI_AD[5]
63	VSS
64	PCI_AD[4]
65	PCI_AD[10]
66	PCI_CBEn[0]
67	PCI_AD[8]
68	VDD_PCI
69	VSS
70	PCI_AD[9]
71	VIO_PCI
72	PCI_AD[11]
73	PCI_AD[12]
74	VDD
75	VSS
76	PCI_AD[13]
77	PCI_AD[14]
78	PCI_AD[15]
79	PCI_CBEn[1]
80	VDD_PCI
81	VSS
82	PCI_PAR
83	PCI_SERRn
84	TEST_SPARE[2]
85	PCI_PERRn
86	JTAG_TDO
87	VSS
88	VSS
89	VSS
90	VSS
91	VSS
92	PCI_AD[16]
93	PWRUP_PLL_BYPASS
94	PCI_LOCKn
95	VSS
96	PCI_DEVSELn
97	JTAG_TCK
98	JTAG_TDI
99	VSS
100	VDD_PCI
101	VSS
102	PCI_STOPn
103	PCI_CBEn[2]
104	PCI_TRDYn
105	PCI_IRDYn
106	PCI_FRAMEn
107	VSS
108	VDD
109	PCI_AD[20]
110	VSS
111	VIO_PCI
112	PCI_AD[19]
113	PCI_AD[18]
114	PCI_AD[17]
115	PCI_AD[21]
116	VDD_PCI
117	VSS
118	PCI_AD[22]
119	PCI_AD[23]
120	PCI_CBEn[3]
121	PCI_AD[24]
122	VSS
123	PCI_AD[26]
124	PCI_AD[27]
125	PCI_AD[25]
126	VSS
127	JTAG_TRSTn
128	TEST_SPARE[0]
129	JTAG_TMS
130	VDD
131	VSS
132	VSS
133	VSS
134	PCI_CLKO[2]
135	VSS
136	VDD_PCI
137	PCI_CLKO[3]
138	PCI_REQn[1]
139	VSS
140	PWRUP_EN_ARB
141	PCI_AD[31]
142	PCI_AD[28]
143	PCI_AD[29]
144	VDD
145	VSS
146	PCI_CLKO[0]
147	PCI_AD[30]
148	PCI_REQn[3]
149	PCI_PMEn
150	VDD_PCI
151	VSS
152	PCI_GNTn[0]
153	PCI_REQn[0]
154	PCI_REQn[2]
155	PCI_GNTn[1]
156	VSS
157	PCI_GNTn[2]
158	PCI_RSTn
159	VDD
160	VSS
161	PCI_INTBn
162	PCI_INTAn
163	PCI_GNTn[3]
164	PCI_INTDn
165	VSS
166	VDD_PCI
167	PCI_CLK
168	PCI_INTCn
169	PCI_M66EN
170	PCI_CLKO[4]
171	VSS
172	VDD_PCI
173	VIO_PCI
174	PCIE_PERSTn
175	VSS
176	VSS