Tsi384 Pinlist -- Integrated Device Technology (Document 80E1000_PN002_02) Copyright © August 2009 Integrated Device Technology. All rights reserved. Published in Canada. Disclaimer: IDT assumes no responsibility for the accuracy or completeness of the information presented, which is subject to change without notice. In no event will IDT be liable for any direct, indirect, special, incidental or consequential damages, including lost profits, lost business or lost data, resulting from the use of or reliance upon the information, whether or not IDT has been advised of the possibility of such damages. Mention of non-IDT products or services is for information purposes only and constitutes neither an endorsement nor a recommendation. Revision History --------------------- August 2009, 80E1000_PN002_02 -- This version of the document does not include any technical changes. October 2006, 80E1000_PN002_01 -- This is the first version of the document. Pin Signal --------------------- A1 PCI_AD[21] A2 PCI_AD[19] A3 PCI_CBEn[2] A4 PCI_DEVSELn A5 PCI_PCIXCAP A6 PCI_SERRn A7 PCI_AD[14] A8 PCI_AD[12] A9 PCI_AD[10] A10 PCI_AD[7] A11 PCI_AD[3] A12 PCI_AD[1] A13 PCI_ACK64n A14 PCI_CBEn[6] A15 PCI_AD[63] A16 PCI_AD[61] B1 PCI_AD[23] B2 VDD_PCI B3 PCI_AD[17] B4 PCI_IRDYn B5 VSS B6 PCI_PERRn B7 PCI_CBEn[1] B8 VDD_PCI B9 PCI_M66EN B10 PCI_AD[8] B11 PCI_AD[5] B12 VDD_PCI B13 VSS B14 PCI_CBEn[4] B15 VDD_PCI B16 PCI_AD[59] C1 PCI_CBEn[3] C2 PCI_AD[22] C3 PCI_AD[20] C4 PCI_AD[16] C5 PCI_PCIXCAP_PU C6 PCI_STOPn C7 PCI_AD[15] C8 PCI_AD[11] C9 VSS C10 PCI_AD[6] C11 PCI_AD[2] C12 PCI_AD[0] C13 PCI_CBEn[7] C14 PCI_PAR64 C15 PCI_AD[62] C16 PCI_AD[57] D1 PCI_AD[27] D2 PCI_AD[25] D3 PCI_AD[24] D4 PCI_AD[18] D5 PCI_FRAMEn D6 PCI_TRDYn D7 PCI_PAR D8 PCI_AD[13] D9 PCI_AD[9] D10 PCI_CBEn[0] D11 PCI_AD[4] D12 PCI_REQ64n D13 PCI_CBEn[5] D14 PCI_AD[60] D15 PCI_AD[58] D16 PCI_AD[55] E1 PCI_AD[29] E2 VSS E3 PCI_AD[26] E4 NC E5 VDD_PCI E6 VDD E7 VDD_PCI E8 VDD E9 VDD E10 VDD_PCI E11 VDD E12 VDD_PCI E13 PCI_AD[56] E14 PCI_AD[54] E15 PCI_AD[53] E16 PCI_AD[51] F1 PCI_AD[31] F2 VDD_PCI F3 PCI_AD[30] F4 PCI_AD[28] F5 VDD F6 VSS F7 VSS F8 VSS F9 VSS F10 VSS F11 VSS F12 VDD F13 PCI_AD[52] F14 PCI_AD[50] F15 VSS F16 PCI_AD[49] G1 PCI_REQn[1] G2 PCI_REQn[0] G3 PCI_GNTn[0] G4 PCI_PMEn G5 VDD G6 VSS G7 VSS G8 VSS G9 VSS G10 VSS G11 VSS G12 VDD G13 PCI_AD[48] G14 PCI_AD[46] G15 VDD_PCI G16 PCI_AD[47] H1 PCI_REQn[3] H2 PCI_REQn[2] H3 PCI_GNTn[1] H4 PCI_RSTn H5 VDD_PCI H6 VSS H7 VSS H8 VSS H9 VSS H10 VSS H11 VSS H12 VDD_PCI H13 PCI_AD[44] H14 PCI_AD[42] H15 PCI_AD[45] H16 PCI_AD[43] J1 PCI_CLK J2 VDD_PCI J3 PCI_GNTn[3] J4 PCI_GNTn[2] J5 VDD J6 VSS J7 VSS J8 VSS J9 VSS J10 VSS J11 VSS J12 VDD J13 PCI_AD[40] J14 PCI_AD[38] J15 PCI_AD[41] J16 PCI_AD[39] K1 PCI_CLKO[1] K2 VSS K3 PCI_CLKO[0] K4 PCI_INTCn K5 VDD K6 VSS K7 VSS K8 VSS K9 VSS K10 VSS K11 VSS K12 VDD K13 PCI_AD[36] K14 PCI_AD[34] K15 PCI_AD[37] K16 PCI_AD[35] L1 PCI_CLKO[3] L2 PCI_CLKO[2] L3 PCI_INTAn L4 PWRUP_CLK_MST L5 PWRUP_EN_ARB L6 VSS L7 VSS L8 VSS L9 VSS L10 VSS L11 VSS L12 VDD_PCI L13 NC L14 PCI_AD[32] L15 VSS L16 PCI_AD[33] M1 PCI_INTBn M2 PCI_INTDn M3 VDD_PCI M4 PCI_SEL100 M5 PCIE_RXD_n[0] M6 VDD M7 PCIE_RXD_n[1] M8 VDDA_PLL M9 PCIE_RXD_n[2] M10 VDD M11 PCIE_RXD_n[3] M12 VDD M13 NC M14 SR_CLK M15 VDD_PCI M16 SR_DIN N1 JTAG_TDO N2 JTAG_TDI N3 PCI_CLKO[4] N4 VSSA_PLL N5 PCIE_RXD_p[0] N6 PWRUP_EXT_CLK_SEL N7 PCIE_RXD_p[1] N8 VSS N9 PCIE_RXD_p[2] N10 VSS N11 PCIE_RXD_p[3] N12 VSS N13 NC N14 NC N15 SR_CSn N16 SR_DOUT P1 JTAG_TCK P2 JTAG_TMS P3 PWRUP_PLL_BYPASSn P4 VDDA_PCIE P5 VSS P6 VSS P7 VSS P8 VDD_PCIE P9 VSS P10 VSS P11 VSS P12 VDDA_PCIE P13 NC P14 NC P15 NC P16 TEST_BIDR_CTL R1 JTAG_TRSTn R2 TEST_BCE R3 PCIE_REFCLK_n R4 VDD_PCIE R5 PCIE_TXD_p[0] R6 VDD_PCIE R7 PCIE_TXD_p[1] R8 VDD_PCIE R9 PCIE_TXD_p[2] R10 VDD_PCIE R11 PCIE_TXD_p[3] R12 VDD_PCIE R13 NC R14 NC R15 PCIE_LANE_VALIDn[1] R16 PCIE_LANE_VALIDn[3] T1 PCIE_PERSTn T2 TEST_ON T3 PCIE_REFCLK_p T4 VSS T5 PCIE_TXD_n[0] T6 NC T7 PCIE_TXD_n[1] T8 VSS T9 PCIE_TXD_n[2] T10 NC T11 PCIE_TXD_n[3] T12 VSS T13 NC T14 NC T15 PCIE_LANE_VALIDn[0] T16 PCIE_LANE_VALIDn[2]