W 00 1F 00
W 00 00 44 -- activate spi 4w; 
W 00 01 03 -- ^8 interpolation
W 00 02 80 -- pll_bypass
W 00 14 6E -- adjust dac_cas_bias (H3-improvement)
W 00 1F 04
W 00 07 E3 -- choose ILA initialization at 4th /A/
W 00 1F 02
W 00 03 23 -- define jclk_cntrl (cdi; fclk_sel init)SIM-ONLY
W 00 03 22 -- define jclk_cntrl (cdi; fclk_sel)
W 00 06 07 -- re-adjust dcsmu-timer (tweak startup-time)
W 00 00 30 -- full re-init; sync starts at '1'
