CGC

Driver for the Clock Generation Circuit. More...

Functions
ssp_err_t	R_CGC_Init (void)
	Initialize the CGC API. More...
ssp_err_t	R_CGC_ClocksCfg (cgc_clocks_cfg_t const *const p_clock_cfg)
	Reconfigure all main system clocks. More...
ssp_err_t	R_CGC_ClockStart (cgc_clock_t clock_source, cgc_clock_cfg_t *p_clock_cfg)
	Start the specified clock if it is not currently active. More...
ssp_err_t	R_CGC_ClockStop (cgc_clock_t clock_source)
	Stop the specified clock if it is active and not configured as the system clock. More...
ssp_err_t	R_CGC_SystemClockSet (cgc_clock_t clock_source, cgc_system_clock_cfg_t const *const p_clock_cfg)
	Set the specified clock as the system clock and configure the internal dividers for ICLK, PCLKA, PCLKB, PCLKC, PCLKD and FCLK. More...
ssp_err_t	R_CGC_SystemClockGet (cgc_clock_t *clock_source, cgc_system_clock_cfg_t *p_set_clock_cfg)
	Return the current system clock source and configuration. More...
ssp_err_t	R_CGC_SystemClockFreqGet (cgc_system_clocks_t clock, uint32_t *p_freq_hz)
	Return the requested internal clock frequency in Hz. More...
ssp_err_t	R_CGC_ClockCheck (cgc_clock_t clock_source)
	Check the specified clock for stability. More...
ssp_err_t	R_CGC_OscStopDetect (void(*p_callback)(cgc_callback_args_t *p_args), bool enable)
	Enable or disable the oscillation stop detection for the main clock. The MCU will automatically switch the system clock to MOCO when a stop is detected if Main Clock is the system clock. If the system clock is the PLL, then the clock source will not be changed and the PLL free running frequency will be the system clock frequency. More...
ssp_err_t	R_CGC_OscStopStatusClear (void)
	Clear the Oscillation Stop Detection Status register. More...
ssp_err_t	R_CGC_BusClockOutCfg (cgc_bclockout_dividers_t divider)
	Configure the secondary dividers for BCLKOUT. The primary divider is set using the bsp clock configuration and the R_CGC_SystemClockSet function. More...
ssp_err_t	R_CGC_BusClockOutEnable (void)
	Enable the BCLKOUT output. More...
ssp_err_t	R_CGC_BusClockOutDisable (void)
	Disable the BCLKOUT output. More...
ssp_err_t	R_CGC_ClockOutCfg (cgc_clock_t clock, cgc_clockout_dividers_t divider)
	Configure the dividers for CLKOUT. More...
ssp_err_t	R_CGC_ClockOutEnable (void)
	Enable the CLKOUT output. More...
ssp_err_t	R_CGC_ClockOutDisable (void)
	Disable the CLKOUT output. More...
ssp_err_t	R_CGC_LCDClockCfg (cgc_clock_t clock)
	Configure the source for the segment LCDCLK. More...
ssp_err_t	R_CGC_LCDClockEnable (void)
	Enable the segment LCDCLK output. More...
ssp_err_t	R_CGC_LCDClockDisable (void)
	Disable the segment LCDCLK output. More...
ssp_err_t	R_CGC_SDADCClockCfg (cgc_clock_t clock)
	Configure the source for the SDADCCLK. More...
ssp_err_t	R_CGC_SDADCClockEnable (void)
	Enable the SDADCCLK output. More...
ssp_err_t	R_CGC_SDADCClockDisable (void)
	Disable the SDADCCLK output. More...
ssp_err_t	R_CGC_SDRAMClockOutEnable (void)
	Enable the SDCLK output. More...
ssp_err_t	R_CGC_SDRAMClockOutDisable (void)
	Disable the SDCLK output. More...
ssp_err_t	R_CGC_USBClockCfg (cgc_usb_clock_div_t divider)
	Configure the dividers for UCLK. More...
ssp_err_t	R_CGC_SystickUpdate (uint32_t period_count, cgc_systick_period_units_t units)
	Re-Configure the systick based on the provided period and current system clock frequency. More...
ssp_err_t	R_CGC_VersionGet (ssp_version_t *const p_version)
	Return the driver version. More...
bool	r_cgc_clock_run_state_get (R_SYSTEM_Type *p_system_reg, cgc_clock_t clock)
	This function returns the run state of the selected clock. More...
cgc_operating_modes_t	r_cgc_operating_mode_get (R_SYSTEM_Type *p_system_reg)
	This function checks the MCU for High Speed Mode. More...
void	r_cgc_operating_hw_modeset (R_SYSTEM_Type *p_system_reg, cgc_operating_modes_t operating_mode)
	This function changes the operating power control mode. More...
void	r_cgc_hoco_wait_control_set (R_SYSTEM_Type *p_system_reg, uint8_t hoco_wait)
	This function sets the HOCO wait time register. More...

Detailed Description

Driver for the Clock Generation Circuit.

Clock Generation Circuit Hardware Functions.

This module supports the Clock Generation Circuit. It implements the following interfaces:

• CGC Interface

Function Documentation

R_CGC_BusClockOutCfg()

ssp_err_t R_CGC_BusClockOutCfg

(

cgc_bclockout_dividers_t

divider

)

Configure the secondary dividers for BCLKOUT. The primary divider is set using the bsp clock configuration and the R_CGC_SystemClockSet function.

Return values

SSP_SUCCESS

Operation performed successfully.

R_CGC_BusClockOutDisable()

ssp_err_t R_CGC_BusClockOutDisable

(

void

)

Disable the BCLKOUT output.

Return values

SSP_SUCCESS

Operation performed successfully.

R_CGC_BusClockOutEnable()

ssp_err_t R_CGC_BusClockOutEnable

(

void

)

Enable the BCLKOUT output.

Return values

SSP_SUCCESS

Operation performed successfully.

r_cgc_clock_run_state_get()

bool r_cgc_clock_run_state_get	(	R_SYSTEM_Type *	p_system_reg,
		cgc_clock_t	clock
	)

This function returns the run state of the selected clock.

Parameters

[in]	clock	the clock to check
[in]	p_system_reg	pointer to system register structure
[in]	clock	- the clock to check

Return values

bool	true if clock is running, false if stopped

R_CGC_ClockCheck()

ssp_err_t R_CGC_ClockCheck

(

cgc_clock_t

clock_source

)

Check the specified clock for stability.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_NOT_STABILIZED	Clock not stabilized.
SSP_ERR_CLOCK_ACTIVE	Clock active but not able to check for stability.
SSP_ERR_CLOCK_INACTIVE	Clock not turned on.
SSP_ERR_INVALID_ARGUMENT	Illegal parameter passed.
SSP_ERR_STABILIZED	Clock stabilized.

R_CGC_ClockOutCfg()

ssp_err_t R_CGC_ClockOutCfg	(	cgc_clock_t	clock,
		cgc_clockout_dividers_t	divider
	)

Configure the dividers for CLKOUT.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_INVALID_ARGUMENT	return error if PLL is used as source for clock out
SSP_ERR_CLOCK_INACTIVE	return error if sub clock is not started prior to using it for clock out

R_CGC_ClockOutDisable()

ssp_err_t R_CGC_ClockOutDisable

(

void

)

Disable the CLKOUT output.

Return values

SSP_SUCCESS

Operation performed successfully.

R_CGC_ClockOutEnable()

ssp_err_t R_CGC_ClockOutEnable

(

void

)

Enable the CLKOUT output.

Return values

SSP_SUCCESS

Operation performed successfully.

R_CGC_ClocksCfg()

ssp_err_t R_CGC_ClocksCfg

(

cgc_clocks_cfg_t const *const

p_clock_cfg

)

Reconfigure all main system clocks.

Return values

SSP_SUCCESS	Clock initialized successfully.
SSP_ERR_INVALID_ARGUMENT	Invalid argument used.
SSP_ERR_MAIN_OSC_INACTIVE	PLL Initialization attempted with Main OCO turned off/unstable.
SSP_ERR_CLOCK_ACTIVE	Active clock source specified for modification. This applies specifically to the PLL dividers/multipliers which cannot be modified if the PLL is active. It has to be stopped first before modification.
SSP_ERR_NOT_STABILIZED	The Clock source is not stabilized after being turned off.
SSP_ERR_CLKOUT_EXCEEDED	The main oscillator can be only 8 or 16 MHz.
SSP_ERR_ASSERTION	A NULL is passed for configuration data when PLL is the clock_source.
SSP_ERR_INVALID_MODE	Attempt to start a clock in a restricted operating power control mode.

R_CGC_ClockStart()

ssp_err_t R_CGC_ClockStart	(	cgc_clock_t	clock_source,
		cgc_clock_cfg_t *	p_clock_cfg
	)

Start the specified clock if it is not currently active.

Configures the following when starting the Main Clock Oscillator:

• MainClock drive capacity (Configured based on external clock frequency)
• MainClock stabilization wait time (Compile time configurable: CGC_CFG_MAIN_OSC_WAIT)
• To update the subclock driven capacity, stop the subclock first before calling this function.

Return values

SSP_SUCCESS	Clock initialized successfully.
SSP_ERR_INVALID_ARGUMENT	Invalid argument used.
SSP_ERR_MAIN_OSC_INACTIVE	PLL Initialization attempted with Main OCO turned off/unstable.
SSP_ERR_CLOCK_ACTIVE	Active clock source specified for modification. This applies specifically to the PLL dividers/multipliers which cannot be modified if the PLL is active. It has to be stopped first before modification.
SSP_ERR_NOT_STABILIZED	The Clock source is not stabilized after being turned off.
SSP_ERR_CLKOUT_EXCEEDED	The main oscillator can be only 8 or 16 MHz.
SSP_ERR_ASSERTION	A NULL is passed for configuration data when PLL is the clock_source.
SSP_ERR_INVALID_MODE	Attempt to start a clock in a restricted operating power control mode.
SSP_ERR_HARDWARE_TIMEOUT	Hardware timed out.

R_CGC_ClockStop()

ssp_err_t R_CGC_ClockStop

(

cgc_clock_t

clock_source

)

Stop the specified clock if it is active and not configured as the system clock.

Return values

SSP_SUCCESS	Clock stopped successfully.
SSP_ERR_CLOCK_ACTIVE	Current System clock source specified for stopping. This is not allowed.
SSP_ERR_OSC_STOP_DET_ENABLED	Illegal attempt to stop MOCO when Oscillation stop is enabled.
SSP_ERR_NOT_STABILIZED	Clock not stabilized after starting. A finite stabilization time after starting the clock has to elapse before it can be stopped.
SSP_ERR_INVALID_ARGUMENT	Invalid argument used.
SSP_ERR_HARDWARE_TIMEOUT	Hardware timed out.

r_cgc_hoco_wait_control_set()

void r_cgc_hoco_wait_control_set	(	R_SYSTEM_Type *	p_system_reg,
		uint8_t	hoco_wait
	)

This function sets the HOCO wait time register.

Parameters

[in]	hoco_wait	HOCOWTCR HSTS setting
[in]	p_system_reg	pointer to system register structure

Return values

none

R_CGC_Init()

ssp_err_t R_CGC_Init

(

void

)

Initialize the CGC API.

Configures the following for the clock generator module -If CGC_CFG_SUBCLOCK_AT_RESET_ENABLE is set to true:

• SubClock drive capacity (Compile time configurable: CGC_CFG_SUBCLOCK_DRIVE)
• Initial setting for the SubClock

THIS FUNCTION MUST BE EXECUTED ONCE AT STARTUP BEFORE ANY OF THE OTHER CGC FUNCTIONS CAN BE USED OR THE CLOCK SOURCE IS CHANGED FROM THE MOCO.

Return values

SSP_SUCCESS	Clock initialized successfully.
SSP_ERR_HARDWARE_TIMEOUT	Hardware timed out.

SubClock will stop only if configurable setting is Enabled

R_CGC_LCDClockCfg()

ssp_err_t R_CGC_LCDClockCfg

(

cgc_clock_t

clock

)

Configure the source for the segment LCDCLK.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_TIMEOUT	Timed out.
SSP_ERR_INVALID_ARGUMENT	lcd_clock settings are invalid
SSP_ERR_UNSUPPORTED	lcd_clock configuration is not supported on this device

R_CGC_LCDClockDisable()

ssp_err_t R_CGC_LCDClockDisable

(

void

)

Disable the segment LCDCLK output.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_TIMEOUT	Timed out.
SSP_ERR_UNSUPPORTED	lcd_clock is not supported on this device

R_CGC_LCDClockEnable()

ssp_err_t R_CGC_LCDClockEnable

(

void

)

Enable the segment LCDCLK output.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_TIMEOUT	Timed out.
SSP_ERR_UNSUPPORTED	lcd_clock is not supported on this device

r_cgc_operating_hw_modeset()

void r_cgc_operating_hw_modeset	(	R_SYSTEM_Type *	p_system_reg,
		cgc_operating_modes_t	operating_mode
	)

This function changes the operating power control mode.

Parameters

[in]	p_system_reg	pointer to system register structure
[in]	operating_mode	Operating power control mode

Enable writing to OPCCR and SOPCCR registers.

Wait for transition to complete.

Disable writing to OPCCR and SOPCCR registers.

The Sub-osc bit has to be cleared first.

Wait for transition to complete.

Set OPCCR.

Wait for transition to complete.

Set SOPCCR.

Wait for transition to complete.

Disable writing to OPCCR and SOPCCR registers.

r_cgc_operating_mode_get()

cgc_operating_modes_t r_cgc_operating_mode_get

(

R_SYSTEM_Type *

p_system_reg

)

This function checks the MCU for High Speed Mode.

Parameters

[in]

p_system_reg

pointer to system register structure

Return values

operating_mode

current mode of operation read from OPCCR register

R_CGC_OscStopDetect()

ssp_err_t R_CGC_OscStopDetect	(	void(*)(cgc_callback_args_t *p_args)	p_callback,
		bool	enable
	)

Enable or disable the oscillation stop detection for the main clock. The MCU will automatically switch the system clock to MOCO when a stop is detected if Main Clock is the system clock. If the system clock is the PLL, then the clock source will not be changed and the PLL free running frequency will be the system clock frequency.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_OSC_STOP_DETECTED	The Oscillation stop detect status flag is set. Under this condition it is not possible to disable the Oscillation stop detection function.
SSP_ERR_ASSERTION	Null pointer passed for callback function when the second argument is "true".
SSP_ERR_ASSERTION	Cannot enable oscillator stop detect in sub-osc speed mode
SSP_ERR_ASSERTION	Invalid peripheral clock divisions for oscillator stop detect
SSP_ERR_INVALID_MODE	Invalid peripheral clock divider setting. Frequencies of peripherals should follow certain conditions.

add callback function to BSP

R_CGC_OscStopStatusClear()

ssp_err_t R_CGC_OscStopStatusClear

(

void

)

Clear the Oscillation Stop Detection Status register.

This register is not cleared automatically if the stopped clock is restarted. This function blocks for about 3 ICLK cycles until the status register is cleared.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_OSC_STOP_CLOCK_ACTIVE	The Oscillation Detect Status flag cannot be cleared if the Main Osc or PLL is set as the system clock. Change the system clock before attempting to clear this bit.

R_CGC_SDADCClockCfg()

ssp_err_t R_CGC_SDADCClockCfg

(

cgc_clock_t

clock

)

Configure the source for the SDADCCLK.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_UNSUPPORTED	sdadc_clock configuration is not supported on this device
SSP_ERR_INVALID_ARGUMENT	Invalid clock used

R_CGC_SDADCClockDisable()

ssp_err_t R_CGC_SDADCClockDisable

(

void

)

Disable the SDADCCLK output.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_UNSUPPORTED	sdadc_clock is not supported on this device

R_CGC_SDADCClockEnable()

ssp_err_t R_CGC_SDADCClockEnable

(

void

)

Enable the SDADCCLK output.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_UNSUPPORTED	sdadc_clock is not supported on this device

R_CGC_SDRAMClockOutDisable()

ssp_err_t R_CGC_SDRAMClockOutDisable

(

void

)

Disable the SDCLK output.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_UNSUPPORTED	sdram_clock is not supported on this device

R_CGC_SDRAMClockOutEnable()

ssp_err_t R_CGC_SDRAMClockOutEnable

(

void

)

Enable the SDCLK output.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_UNSUPPORTED	sdram_clock is not supported on this device

R_CGC_SystemClockFreqGet()

ssp_err_t R_CGC_SystemClockFreqGet	(	cgc_system_clocks_t	clock,
		uint32_t *	p_freq_hz
	)

Return the requested internal clock frequency in Hz.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_INVALID_ARGUMENT	Invalid clock specified.
SSP_ERR_ASSERTION	A NULL is passed for frequency data.

R_CGC_SystemClockGet()

ssp_err_t R_CGC_SystemClockGet	(	cgc_clock_t *	clock_source,
		cgc_system_clock_cfg_t *	p_set_clock_cfg
	)

Return the current system clock source and configuration.

Return values

SSP_SUCCESS	Parameters returned successfully.
SSP_ERR_ASSERTION	A NULL is passed for configuration data.
SSP_ERR_ASSERTION	A NULL is passed for clock source.

R_CGC_SystemClockSet()

ssp_err_t R_CGC_SystemClockSet	(	cgc_clock_t	clock_source,
		cgc_system_clock_cfg_t const *const	p_clock_cfg
	)

Set the specified clock as the system clock and configure the internal dividers for ICLK, PCLKA, PCLKB, PCLKC, PCLKD and FCLK.

THIS FUNCTION DOES NOT CHECK TO SEE IF THE OPERATING MODE SUPPORTS THE SPECIFIED CLOCK SOURCE AND DIVIDER VALUES. SETTING A CLOCK SOURCE AND DVIDER OUTSIDE THE RANGE SUPPORTED BY THE CURRENT OPERATING MODE WILL RESULT IN UNDEFINED OPERATION.

IF THE LOCO MOCO OR SUBCLOCK ARE CHOSEN AS THE SYSTEM CLOCK, THIS FUNCTION WILL SET THOSE AS THE SYSTEM CLOCK WITHOUT CHECKING FOR STABILIZATION. IT IS UP TO THE USER TO ENSURE THAT LOCO, MOCO OR SUBCLOCK ARE STABLE BEFORE USING THEM AS THE SYSTEM CLOCK.

Additionally this function sets the RAM and ROM wait states for the MCU. For the S7 MCU the ROMWT register controls ROM wait states. For the S3 MCU the MEMWAIT register controls ROM wait states.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_CLOCK_INACTIVE	The specified clock source is inactive.
SSP_ERR_ASSERTION	The p_clock_cfg parameter is NULL.
SSP_ERR_NOT_STABILIZED	The clock source has not stabilized
SSP_ERR_INVALID_ARGUMENT	Invalid argument used. ICLK is not set as the fastest clock.
SSP_ERR_INVALID_MODE	Peripheral divisions are not valid in sub-osc mode
SSP_ERR_INVALID_MODE	Oscillator stop detect not allowed in sub-osc mode

In order to correctly set the ROM and RAM wait state registers we need to know the current (S3A7 only) and requested iclk frequencies.

R_CGC_SystickUpdate()

ssp_err_t R_CGC_SystickUpdate	(	uint32_t	period_count,
		cgc_systick_period_units_t	units
	)

Re-Configure the systick based on the provided period and current system clock frequency.

Parameters

[in]	period_count	The duration for the systick period.
[in]	units	The units for the provided period.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_INVALID_ARGUMENT	Invalid period specified.
SSP_ERR_ABORTED	Attempt to update systick timer failed.

R_CGC_USBClockCfg()

ssp_err_t R_CGC_USBClockCfg

(

cgc_usb_clock_div_t

divider

)

Configure the dividers for UCLK.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_INVALID_ARGUMENT	Invalid usb_clock divider specified

R_CGC_VersionGet()

ssp_err_t R_CGC_VersionGet

(

ssp_version_t *const

p_version

)

Return the driver version.

Return values

SSP_SUCCESS	Operation performed successfully.
SSP_ERR_ASSERTION	The parameter p_version is NULL..