Interface for clock generation. More...

Data Structures
struct	cgc_callback_args_t

struct	cgc_clock_cfg_t

struct	cgc_system_clock_cfg_t

struct	cgc_clocks_cfg_t

struct	cgc_api_t

struct	cgc_instance_t

Enumerations
enum	cgc_event_t { CGC_EVENT_OSC_STOP_DETECT }

enum	cgc_clock_t { CGC_CLOCK_HOCO = 0x00, CGC_CLOCK_MOCO = 0x01, CGC_CLOCK_LOCO = 0x02, CGC_CLOCK_MAIN_OSC = 0x03, CGC_CLOCK_SUBCLOCK = 0x04, CGC_CLOCK_PLL = 0x05 }

enum	cgc_pll_div_t { CGC_PLL_DIV_1 = 0x00, CGC_PLL_DIV_2 = 0x01, CGC_PLL_DIV_3 = 0x02, CGC_PLL_DIV_4 = 0x03 }

enum	cgc_sys_clock_div_t { CGC_SYS_CLOCK_DIV_1 = 0x00, CGC_SYS_CLOCK_DIV_2 = 0x01, CGC_SYS_CLOCK_DIV_4 = 0x02, CGC_SYS_CLOCK_DIV_8 = 0x03, CGC_SYS_CLOCK_DIV_16 = 0x04, CGC_SYS_CLOCK_DIV_32 = 0x05, CGC_SYS_CLOCK_DIV_64 = 0x06 }

enum	cgc_system_clocks_t { CGC_SYSTEM_CLOCKS_PCLKA, CGC_SYSTEM_CLOCKS_PCLKB, CGC_SYSTEM_CLOCKS_PCLKC, CGC_SYSTEM_CLOCKS_PCLKD, CGC_SYSTEM_CLOCKS_BCLK, CGC_SYSTEM_CLOCKS_FCLK, CGC_SYSTEM_CLOCKS_ICLK }

enum	cgc_clockout_dividers_t { CGC_CLOCKOUT_DIV_1 = 0x00, CGC_CLOCKOUT_DIV_2 = 0x01, CGC_CLOCKOUT_DIV_4 = 0x02, CGC_CLOCKOUT_DIV_8 = 0x03, CGC_CLOCKOUT_DIV_16 = 0x04, CGC_CLOCKOUT_DIV_32 = 0x05, CGC_CLOCKOUT_DIV_64 = 0x06, CGC_CLOCKOUT_DIV_128 = 0x07 }

enum	cgc_bclockout_dividers_t { CGC_BCLOCKOUT_DIV_1 = 0x00, CGC_BCLOCKOUT_DIV_2 = 0x01 }

enum	cgc_usb_clock_div_t { CGC_USB_CLOCK_DIV_3 = 0x02, CGC_USB_CLOCK_DIV_4 = 0x03, CGC_USB_CLOCK_DIV_5 = 0x04 }

enum	cgc_systick_period_units_t { CGC_SYSTICK_PERIOD_UNITS_MILLISECONDS = 1000, CGC_SYSTICK_PERIOD_UNITS_MICROSECONDS = 1000000 }

enum	cgc_clock_change_t { CGC_CLOCK_CHANGE_NONE, CGC_CLOCK_CHANGE_STOP, CGC_CLOCK_CHANGE_START }

Detailed Description

Interface for clock generation.

Summary

The CGC interface provides the ability to configure and use all of the CGC module's capabilities. Among the capabilities is the selection of several clock sources to use as the system clock source. Additionally, the system clocks can be divided down to provide a wide range of frequencies for various system and peripheral needs.

Clock stability can be checked and clocks may also be stopped to save power when not needed. The API has a function to return the frequency of the system and system peripheral clocks at run time. There is also a feature to detect when the main oscillator has stopped, with the option of calling a user provided callback function.

Enumeration Type Documentation

◆ cgc_bclockout_dividers_t

enum cgc_bclockout_dividers_t

Divider values for the external bus clock output.

Enumerator
CGC_BCLOCKOUT_DIV_1	External bus clock source is divided by 1.
CGC_BCLOCKOUT_DIV_2	External bus clock source is divided by 2.

◆ cgc_clock_change_t

enum cgc_clock_change_t

Clock options

Enumerator
CGC_CLOCK_CHANGE_NONE	No change to the clock.
CGC_CLOCK_CHANGE_STOP	Stop the clock.
CGC_CLOCK_CHANGE_START	Start the clock.

◆ cgc_clock_t

enum cgc_clock_t

System clock source identifiers - The source of ICLK, BCLK, FCLK, PCLKS A-D and UCLK prior to the system clock divider

Enumerator
CGC_CLOCK_HOCO	The high speed on chip oscillator.
CGC_CLOCK_MOCO	The middle speed on chip oscillator.
CGC_CLOCK_LOCO	The low speed on chip oscillator.
CGC_CLOCK_MAIN_OSC	The main oscillator.
CGC_CLOCK_SUBCLOCK	The subclock oscillator.
CGC_CLOCK_PLL	The PLL oscillator.

◆ cgc_clockout_dividers_t

enum cgc_clockout_dividers_t

Divider values for the CLKOUT output.

Enumerator
CGC_CLOCKOUT_DIV_1	Clockout source is divided by 1.
CGC_CLOCKOUT_DIV_2	Clockout source is divided by 2.
CGC_CLOCKOUT_DIV_4	Clockout source is divided by 4.
CGC_CLOCKOUT_DIV_8	Clockout source is divided by 8.
CGC_CLOCKOUT_DIV_16	Clockout source is divided by 16.
CGC_CLOCKOUT_DIV_32	Clockout source is divided by 32.
CGC_CLOCKOUT_DIV_64	Clockout source is divided by 64.
CGC_CLOCKOUT_DIV_128	Clockout source is divided by 128.

◆ cgc_event_t

enum cgc_event_t

Events that can trigger a callback function

Enumerator
CGC_EVENT_OSC_STOP_DETECT	Oscillator stop detection has caused the event.

◆ cgc_pll_div_t

enum cgc_pll_div_t

PLL divider values

Enumerator
CGC_PLL_DIV_1	PLL divider of 1.
CGC_PLL_DIV_2	PLL divider of 2.
CGC_PLL_DIV_3	PLL divider of 3 (S7G2 only).
CGC_PLL_DIV_4	PLL divider of 4 (S3A7 only).

◆ cgc_sys_clock_div_t

enum cgc_sys_clock_div_t

System clock divider values - The individually selectable divider of each of the system clocks, ICLK, BCLK, FCLK, PCLKS A-D

Enumerator
CGC_SYS_CLOCK_DIV_1	System clock divided by 1.
CGC_SYS_CLOCK_DIV_2	System clock divided by 2.
CGC_SYS_CLOCK_DIV_4	System clock divided by 4.
CGC_SYS_CLOCK_DIV_8	System clock divided by 8.
CGC_SYS_CLOCK_DIV_16	System clock divided by 16.
CGC_SYS_CLOCK_DIV_32	System clock divided by 32.
CGC_SYS_CLOCK_DIV_64	System clock divided by 64.

◆ cgc_system_clocks_t

enum cgc_system_clocks_t

System clock identifiers - Used as an input parameter to the cgc_api_t::systemClockFreqGet function.

Enumerator
CGC_SYSTEM_CLOCKS_PCLKA	PCLKA - Peripheral module clock A.
CGC_SYSTEM_CLOCKS_PCLKB	PCLKB - Peripheral module clock B.
CGC_SYSTEM_CLOCKS_PCLKC	PCLKC - Peripheral module clock C.
CGC_SYSTEM_CLOCKS_PCLKD	PCLKD - Peripheral module clock D.
CGC_SYSTEM_CLOCKS_BCLK	BCLK - External bus Clock.
CGC_SYSTEM_CLOCKS_FCLK	FCLK - FlashIF clock.
CGC_SYSTEM_CLOCKS_ICLK	ICLK - System clock.

◆ cgc_systick_period_units_t

enum cgc_systick_period_units_t

Available period units for R_CGC_SystickUpdate()

Enumerator
CGC_SYSTICK_PERIOD_UNITS_MILLISECONDS	Requested period in milliseconds.
CGC_SYSTICK_PERIOD_UNITS_MICROSECONDS	Requested period in microseconds.

◆ cgc_usb_clock_div_t

enum cgc_usb_clock_div_t

USB clock divider values

Enumerator
CGC_USB_CLOCK_DIV_3	Divide USB source clock by 3.
CGC_USB_CLOCK_DIV_4	Divide USB source clock by 4.
CGC_USB_CLOCK_DIV_5	Divide USB source clock by 5.

Data Structures

Enumerations