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Synergy Software Package User's Manual
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RTOS-integrated NetX Ethernet driver for the Renesas Synergy software and Synergy Ethernet IP. More...
Modules | |
| Interface file between SF_EL_NX and PHY driver | |
Data Structures | |
| struct | EMAC_BD |
| struct | nx_mac_address_t |
| struct | NX_CALLBACK_REC |
| struct | sf_el_nx_cfg_t |
| struct | NX_REC |
Macros | |
| #define | SF_EL_NX_API_VERSION_MAJOR (2U) |
| #define | SF_EL_NX_CODE_VERSION_MAJOR (2U) |
| #define | MAX_ENET_INSTANCES 2 |
| #define | TX_QUEUE_DEPTH 10 |
| #define | NX_ENET_MAX_MTU 1518U |
| #define | NX_INITIALIZE_DONE 0x0002U |
| #define | NX_LINK_ENABLED 0x0004U |
| #define | DESCRIPTOR_FLAG_ACTIVE 0x80000000U /* TACT/RACT - Tx/Rx descriptor active */ |
Functions | |
| void | edmac_eint_isr (void) |
| edmac_eint_isr More... | |
| UINT | nx_synergy_ethernet_init (NX_REC *nx_rec_ptr, sf_el_nx_cfg_t *sf_el_nx_cfg_ptr, bool hw_padding) |
| nx_synergy_ethernet_init More... | |
| void | nx_driver_event_handler (NX_REC *nx_rec_ptr) |
| nx_driver_event_handler More... | |
| void | enet_hw_enable_interrupt (NX_REC *nx_rec_ptr) |
| enet_hw_enable_interrupt More... | |
| UINT | nx_synergy_ethernet_deinit (NX_REC *nx_rec_ptr, sf_el_nx_cfg_t *sf_el_nx_cfg_ptr) |
| nx_synergy_ethernet_deinit More... | |
| ssp_err_t | nx_ether_custom_packet_send (NX_PACKET_POOL *pool_ptr, NX_REC *nx_record_ptr, UCHAR *data, UINT length, USHORT ether_type, nx_mac_address_t dest_mac_address) |
| nx_ether_custom_packet_send More... | |
| ssp_err_t | nx_ether_driver (NX_IP_DRIVER *driver_req_ptr, NX_REC *nx_rec_ptr, sf_el_nx_cfg_t *sf_el_nx_cfg_ptr) |
| nx_ether_driver More... | |
| void | nx_ether_interrupt (NX_REC *nx_rec_ptr) |
| nx_ether_interrupt More... | |
| ssp_err_t | nx_ethernet_version_get (ssp_version_t *const p_version) |
| Retrieve the API version number. More... | |
RTOS-integrated NetX Ethernet driver for the Renesas Synergy software and Synergy Ethernet IP.
| #define DESCRIPTOR_FLAG_ACTIVE 0x80000000U /* TACT/RACT - Tx/Rx descriptor active */ |
Bits in the status word of the tx / rx descriptors
| #define MAX_ENET_INSTANCES 2 |
Determine if the driver uses IP deferred processing or direct ISR processing.
| #define NX_ENET_MAX_MTU 1518U |
Max Ethernet packet size (14+ 1500 +2)
| #define NX_INITIALIZE_DONE 0x0002U |
Device is Initialized
| #define NX_LINK_ENABLED 0x0004U |
Device is enabled
| #define SF_EL_NX_API_VERSION_MAJOR (2U) |
Version of the API defined in this file
| #define SF_EL_NX_CODE_VERSION_MAJOR (2U) |
Version of code that implements the API defined in this file
| #define TX_QUEUE_DEPTH 10 |
Netx packets queued before dropping
| void edmac_eint_isr | ( | void | ) |
edmac_eint_isr
This is the Ethernet interrupt service routine. It clears the interrupt flag and calls nx_ether_interrupt to process the interrupt.
Save context if RTOS is used
Process the interrupt.
Clear pending interrupt flag to make sure it doesn't fire again after exiting.
Restore context if RTOS is used
| void enet_hw_enable_interrupt | ( | NX_REC * | nx_rec_ptr | ) |
enet_hw_enable_interrupt
This function enables interrupts for the given Ethernet port.
| [in] | nx_rec_ptr | : Pointer to Ethernet record structure. |
Enable interrupts at the NVIC.
Enable interrupts at the Ethernet controller
| void nx_driver_event_handler | ( | NX_REC * | nx_rec_ptr | ) |
nx_driver_event_handler
This function is called from the IP thread deferred event. On every deferred event, this routine checks for Phy link status and handles link up/down and link change. During initialization this routine is responsible for checking for autonegotiation.
| [in] | nx_rec_ptr | : Pointer to Ethernet record structure. |
Determine previous link status.
Save link status and changed polling interval.
Check PHY link status.
Save link status and changed polling interval.
| ssp_err_t nx_ether_custom_packet_send | ( | NX_PACKET_POOL * | pool_ptr, |
| NX_REC * | nx_record_ptr, | ||
| UCHAR * | data, | ||
| UINT | length, | ||
| USHORT | ether_type, | ||
| nx_mac_address_t | dest_mac_address | ||
| ) |
nx_ether_custom_packet_send
Ethernet driver routine to send a user data in raw Ethernet packet frame from a Source HW address to destination HW address with the requested EtherType through a Ethernet channel
| [in] | pool_ptr | : Pointer to packet pool to use |
| [in] | nx_record_ptr | : Pointer to Ethernet record structure |
| [in] | data | : Pointer to data to be send |
| [in] | length | : length of data to send |
| [in] | ether_type | : Type of Ethernet packet |
| [in] | dest_mac_address | : Destination hardware address to send the user data |
| SSP_SUCCESS | : Call successful |
| SSP_ERR_ASSERTION | : - A parameter pointers point to NULL
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| SSP_ERR_OUT_OF_MEMORY | : No memory is free to allocate the packet in the pool buffer |
| SSP_ERR_NOT_OPEN | : Link not enabled |
| SSP_ERR_INTERNAL | : - Maximum transmit queue depth has been reached
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Free the packet that we will not send.
Setup the prepend pointer in order to build the Ethernet frame. Backup another 2 bytes to get 32-bit word alignment.
Build the actual Ethernet frame.
Build the sender's MAC access.
Set the Ethernet frame type.
Endian swapping if necessary.
Put the frame on the wire.
| ssp_err_t nx_ether_driver | ( | NX_IP_DRIVER * | driver_req_ptr, |
| NX_REC * | nx_rec_ptr, | ||
| sf_el_nx_cfg_t * | sf_el_nx_cfg_ptr | ||
| ) |
nx_ether_driver
Ethernet driver function for Renesas Synergy.
| [in] | driver_req_ptr | : Pointer to driver request structure |
| [in] | nx_rec_ptr | : Pointer to Ethernet record structure |
| [in] | sf_el_nx_cfg_ptr | : sf_el_nx configuration structure pointer. This is similar to SSP configuration structure |
| SSP_SUCCESS | : Call successful. |
| SSP_ERR_ASSERTION | : One or more pointers point to NULL. |
Perform parameter checking
Setup the IP pointer from the driver request.
Default to successful return.
Extract driver command.
Process the driver request.
Save the callback record pointer in the record structure.
Record the interface structure in the driver record.
This command is used in multi homed devices - return NX_SUCCESS by default.
Process driver initialization.
Initialize BDs.
Record the interface structure in the driver record.
Update associated channel information in driver record
Configure mac address.
Get MAC address from user.
Detect S5D5 Mask Rev 02 to enable software padding for it
Initialize the ETHERC and E-DMAC hardware.
Setup the link maximum IP layer transfer unit.
See if we can honor the NX_LINK_ENABLE request. NX_ALREADY_ENABLED: Device has already been enabled
Enable the interrupts, at the interrupt controller and Ethernet controller.
Make sure we are in the right state to do the NX_LINK_DISABLE.
Disable receive and transmit.
Clear link enabled flag.
Clear the enabled flag since there is no-one else.
Free the packet that we will not send.
Process driver send packet. Place the Ethernet frame at the front of the packet.
Adjust the prepend pointer to accommodate Ethernet header.
Check if there is enough space in packet to append data.
Packet underflow.
Free the packet as there is not enough space to append data in it.
Adjust packet length.
Setup the prepend pointer in order to build the Ethernet frame. Backup another 2 bytes to get 32-bit word alignment.
Build the actual Ethernet frame.
Use MAC broadcast for this frame.
Build the sender's MAC access.
Set the Ethernet frame type.
Endian swapping if necessary.
Put the frame on the wire.
Enable multicast.
The device automatically receives multicast packets. Nothing needs to be done.
Process driver deferred requests. Process a device driver function on behalf of the IP thread.
Un-Initialize the ETHERC, E-DMAC and EPTPC hardware
Return the unhandled command status.
Return NULL in the supplied return pointer.
| void nx_ether_interrupt | ( | NX_REC * | nx_rec_ptr | ) |
nx_ether_interrupt
This function is the main Renesas Ethernet interrupt handler.
| [in] | nx_rec_ptr | : Pointer to Ethernet record structure |
Read EDMAC and EtherC status register.
Clear all interrupts.
Frame transmit completed interrupt The MAC sets Transmit Complete flag only if all frames are transmitted. This creates a delay in processing transmitted frames. The work around: this driver process transmitted packets when frame receive interrupt occurs. This way the transmitted packets can be released before processing received packets, reducing the delay.
Frame received.
Special case for ECI interrupt + link change.
To report link status changes to the application, add a semaphore put or event flag set to the statement below.
Link present.
| ssp_err_t nx_ethernet_version_get | ( | ssp_version_t *const | p_version | ) |
Retrieve the API version number.
| SSP_SUCCESS | Successful return. |
| SSP_ERR_ASSERTION | The parameter p_version is NULL. |
Return the version number
| UINT nx_synergy_ethernet_deinit | ( | NX_REC * | nx_rec_ptr, |
| sf_el_nx_cfg_t * | sf_el_nx_cfg_ptr | ||
| ) |
nx_synergy_ethernet_deinit
This function performs reset of the ethernet controller and PTP controller.
| [in] | nx_rec_ptr | : Pointer to Ethernet record structure. |
| [in] | sf_el_nx_cfg_ptr | : sf_el_nx configuration structure pointer |
| NX_SUCCESS | : Call successful |
| NX_NOT_SUCCESSFUL | : Call not successful |
Disable transmission and reception at the Ethernet controller
Reset the EPTPC, Resetting after detection of an erroneous flag
Reset the ETHERC and EDMAC
Wait for 64 PCLKA cycles to reset ETHERC and EDMAC
Double check the Interrupts are disabled
Disable interrupts at the NVIC.
Check for the ether channel
Hold PHY in Reset for channel 1
Hold PHY in Reset for channel 0
Disable clock to the module
| UINT nx_synergy_ethernet_init | ( | NX_REC * | nx_rec_ptr, |
| sf_el_nx_cfg_t * | sf_el_nx_cfg_ptr, | ||
| bool | hw_padding | ||
| ) |
nx_synergy_ethernet_init
This function initializes the specified Ethernet port.
| [in] | nx_rec_ptr | Pointer to Ethernet record structure. |
| [in] | hw_padding | Flag to indicate hardware 2 byte padding is used or not. |
| [in] | sf_el_nx_cfg_ptr | Pointer to configuration structure. |
| SSP_SUCCESS | Call successful. |
| NX_NOT_SUCCESSFUL | Call not successful. |
Configure the Ethernet interrupt.
Enable clock
Reset PHY
Initialize & reset EDMAC and ETHERC
Wait at least 64 cycles of PCLKA to reset the EDMAC and ETHERC. PCLKA must be at least 12.5 MHz to use Ethernet, so wait at least 5.12 us.
Set ETHERC default modes 100 Mbps, Full duplex
Set to little Endian.
Initialize controller
Set up descriptor addresses
Configure FIFO
Enable EDMAC receive
Enable receive, transmit, ECI interrupts.
Initialize PHY.
Start PHY auto negotiation
Create a timer to poll for completion of autonegotiation.