PDC Interface

Interface for PDC functions. More...

Data Structures
struct	pdc_state_t
struct	pdc_callback_args_t
struct	pdc_cfg_t
struct	pdc_api_t
struct	pdc_instance_t

Macros
#define	PDC_API_VERSION_MAJOR   (2U)

Typedefs
typedef void	pdc_ctrl_t

Enumerations
enum	pdc_clock_division_t {   PDC_CLOCK_DIVISION_2 = 0u, PDC_CLOCK_DIVISION_4 = 1u, PDC_CLOCK_DIVISION_6 = 2u, PDC_CLOCK_DIVISION_8 = 3u,   PDC_CLOCK_DIVISION_10 = 4u, PDC_CLOCK_DIVISION_12 = 5u, PDC_CLOCK_DIVISION_14 = 6u, PDC_CLOCK_DIVISION_16 = 7u }
enum	pdc_endian_t { PDC_ENDIAN_LITTLE = 0u, PDC_ENDIAN_BIG = 1u }
enum	pdc_hsync_polarity_t { PDC_HSYNC_POLARITY_HIGH = 0u, PDC_HSYNC_POLARITY_LOW = 1u }
enum	pdc_vsync_polarity_t { PDC_VSYNC_POLARITY_HIGH = 0u, PDC_VSYNC_POLARITY_LOW = 1u }
enum	pdc_event_t {   PDC_EVENT_TRANSFER_COMPLETE = 0u, PDC_EVENT_RX_DATA_READY = 0x01u, PDC_EVENT_FRAME_END = 0x02u, PDC_EVENT_ERR_OVERRUN = 0x04u,   PDC_EVENT_ERR_UNDERRUN = 0x08u, PDC_EVENT_ERR_V_SET = 0x10u, PDC_EVENT_ERR_H_SET = 0x20u }
enum	pdc_vsync_state_t { PDC_VSYNC_STATE_LOW = 0u, PDC_VSYNC_STATE_HIGH = 1u }
enum	pdc_hsync_state_t { PDC_HSYNC_STATE_LOW = 0u, PDC_HSYNC_STATE_HIGH = 1u }

Detailed Description

Interface for PDC functions.

Summary

The PDC interface provides the functionality for capturing an image from a camera. When a capture is complete a transfer complete interrupt is triggered.

Known Implementations

See also

PDC

Related SSP architecture topics:

• What is an SSP Interface? SSP Interfaces
• What is a SSP Layer? SSP Predefined Layers
• How to use SSP Interfaces and Modules? Using SSP Modules

Macro Definition Documentation

PDC_API_VERSION_MAJOR

#define PDC_API_VERSION_MAJOR   (2U)

Register definitions, common services and error codes.

Typedef Documentation

pdc_ctrl_t

typedef void pdc_ctrl_t

PDC control block. Allocate an instance specific control block to pass into the PDC API calls.

Implemented as

• pdc_instance_ctrl_t

Enumeration Type Documentation

pdc_clock_division_t

enum pdc_clock_division_t

Clock divider applied to PDC clock to provide PCKO output frequency

Enumerator
PDC_CLOCK_DIVISION_2	CLK / 2.
PDC_CLOCK_DIVISION_4	CLK / 4.
PDC_CLOCK_DIVISION_6	CLK / 6.
PDC_CLOCK_DIVISION_8	CLK / 8.
PDC_CLOCK_DIVISION_10	CLK / 10.
PDC_CLOCK_DIVISION_12	CLK / 12.
PDC_CLOCK_DIVISION_14	CLK / 14.
PDC_CLOCK_DIVISION_16	CLK / 16.

pdc_endian_t

enum pdc_endian_t

Endian of captured data

Enumerator
PDC_ENDIAN_LITTLE	Data is in little endian format.
PDC_ENDIAN_BIG	Data is in big endian format.

pdc_event_t

enum pdc_event_t

PDC events

Enumerator
PDC_EVENT_TRANSFER_COMPLETE	Complete frame transferred by DMAC/DTC.
PDC_EVENT_RX_DATA_READY	Receive data ready interrupt.
PDC_EVENT_FRAME_END	Frame end interrupt.
PDC_EVENT_ERR_OVERRUN	Overrun interrupt.
PDC_EVENT_ERR_UNDERRUN	Underrun interrupt.
PDC_EVENT_ERR_V_SET	Vertical line setting error interrupt.
PDC_EVENT_ERR_H_SET	Horizontal byte number setting error interrupt.

pdc_hsync_polarity_t

enum pdc_hsync_polarity_t

Polarity of input HSYNC signal

Enumerator
PDC_HSYNC_POLARITY_HIGH	HSYNC signal is active high.
PDC_HSYNC_POLARITY_LOW	HSYNC signal is active low.

pdc_hsync_state_t

enum pdc_hsync_state_t

HSYNC signal state

Enumerator
PDC_HSYNC_STATE_LOW	HSYNC signal is low.
PDC_HSYNC_STATE_HIGH	HSYNC signal is high.

pdc_vsync_polarity_t

enum pdc_vsync_polarity_t

Polarity of input VSYNC signal

Enumerator
PDC_VSYNC_POLARITY_HIGH	VSYNC signal is active high.
PDC_VSYNC_POLARITY_LOW	VSYNC signal is active low.

pdc_vsync_state_t

enum pdc_vsync_state_t

VSYNC signal state

Enumerator
PDC_VSYNC_STATE_LOW	VSYNC signal is low.
PDC_VSYNC_STATE_HIGH	VSYNC signal is high.