*ISL28177 Macromodel
**Revision History:
*Revision A, LaFontaine December 14, 2011
*Model for Noise, quiescent supply currents,
*CMRR 145dB, fcm=500kHz, AVOL 140dB 
*f=0.075Hz SR = 0.2V/us, GBWP 600kHz, 
*2nd pole 8Mhz, output voltage clamp 
*and short ckt current limit.
*
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT", Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*	+input
*	|	-input
* 	| 		| 	+Vsupply
* 	| 		| 		|	-Vsupply
* 	| 		| 		| 	|		output
* 	| 		| 		| 	| 			|
.subckt ISL28177 Vin+ Vin- V+ V- VOUT
* source ISL28177_SPICEMODEL
*
*Voltage Noise
E_En         IN+ VIN+ 2 0 1
D_D1         1 2 DN
V_V1         1 0 0.07
R_R19         2 0  5000
*
*Input Stage
I_IOS         IN+ VIN- DC 1e-9  
C_C1         IN+ VIN-  1.2e-12 
C_C2         0 VIN-  2e-12
C_C3         0 IN+ 2e-12
R_R1         VCM VIN-  5e11
R_R2         IN+ VCM  5e11 
R_R3         6 V++  4.45e3
R_R4         7 V++  4.45e3
Q_Q1         4 VIN- 3 SuperB
Q_Q2         5 10 3 SuperB
Q_Q3         V-- 3 9 Mirror
Q_Q4         6 8 4 Cascode
Q_Q5         7 8 5 Cascode
I_IEE         3 V-- DC 200e-6  
I_IEE1         V++ 8 DC 96e-6  
D_D2         8 9 DX    
E_EOS         10 11 VC VMID 1E-9
V_VOS         11 IN+ 30E-6
*
*1st Gain Stage
G_G1         V++ 13 6 7 0.06
G_G2         V-- 13 6 7 0.06
R_R5         13 V++  1
R_R6         V-- 13  1
V_V2         12 13 1.7
V_V3         13 14 1.7
D_D3         12 V++ DX
D_D4         V-- 14 DX
*
*2nd Gain Stage
G_G3         V++ 15 13 VMID 4.712E-3
G_G4         V-- 15 13 VMID 4.712E-3
R_R7         15 V++  2122.196e6 
R_R8         V-- 15  2122.196e6
V_V4         16 15 1.7
V_V5         15 17 1.7
D_D5         16 V++ DX
D_D6         V-- 17 DX
C_C4         15 V++  1e-9
C_C5         V-- 15  1e-9
*
*Mid supply Ref
R_R9         VMID V++  1
R_R10         V-- VMID  1
E_E1         V++ 0 V+ 0 1
E_E2         V-- 0 V- 0 1
I_ISY         V+ V- DC 1.18e-3  
*
*Common Mode Gain Stage with Zero
G_G5         V++ VC VCM VMID 0.1e-6
G_G6         V-- VC VCM VMID 0.1e-6
R_R11         VC 18  1
R_R12         19 VC  1
L_L1         18 V++  318.31927e-6  
L_L2         19 V--  318.31927e-6  
*
*2nd Pole Stage
G_G7         V++ 20 15 VMID 502.64e-6
G_G8         V-- 20 15 VMID 502.64e-6
G_G9         V++ 21 20 VMID 502.64e-6
G_G10         V-- 21 20 VMID 502.64e-6
R_R13         20 V++  1989.49546
R_R14         V-- 20  1989.49546
R_R15         21 V++  1989.49546
R_R16         V-- 21  1989.49546
C_C6         20 V++  10e-12 
C_C7         V-- 20  10e-12
C_C8         21 V++  10e-12
C_C9         V-- 21  10e-12
*
*Output Stage with Correction Current Sources
G_G11         VOUT V++ V++ 21 1.11e-2
G_G12         V-- VOUT 21 V-- 1.11e-2
G_G13         22 V-- VOUT 21 1.11e-2
G_G14         25 V-- 21 VOUT 1.11e-2
D_D7         21 23 DX
D_D8         24 21 DX
D_D9         V++ 22 DX
D_D10         V++ 25 DX
D_D11         V-- 22 DY
D_D12         V-- 25 DY
V_V6         23 VOUT 0.18
V_V7         VOUT 24 0.18
R_R17         VOUT V++  9E1
R_R18         V-- VOUT  9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12  
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 +rb=140 re=0.011 rc=900 cje=0.2E-12 +cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 
+ cjc=0.44E-12 
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28177*ISL28177 Macromodel
**Revision History:
*Revision A, LaFontaine December 14, 2011
*Model for Noise, quiescent supply currents,
*CMRR 145dB, fcm=500kHz, AVOL 140dB 
*f=0.075Hz SR = 0.2V/us, GBWP 600kHz, 
*2nd pole 8Mhz, output voltage clamp 
*and short ckt current limit.
*
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT", Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*	+input
*	|	-input
* 	| 		| 	+Vsupply
* 	| 		| 		|	-Vsupply
* 	| 		| 		| 	|		output
* 	| 		| 		| 	| 			|
.subckt ISL28177 Vin+ Vin- V+ V- VOUT
* source ISL28177_SPICEMODEL
*
*Voltage Noise
E_En         IN+ VIN+ 2 0 1
D_D1         1 2 DN
V_V1         1 0 0.07
R_R19         2 0  5000
*
*Input Stage
I_IOS         IN+ VIN- DC 1e-9  
C_C1         IN+ VIN-  1.2e-12 
C_C2         0 VIN-  2e-12
C_C3         0 IN+ 2e-12
R_R1         VCM VIN-  5e11
R_R2         IN+ VCM  5e11 
R_R3         6 V++  4.45e3
R_R4         7 V++  4.45e3
Q_Q1         4 VIN- 3 SuperB
Q_Q2         5 10 3 SuperB
Q_Q3         V-- 3 9 Mirror
Q_Q4         6 8 4 Cascode
Q_Q5         7 8 5 Cascode
I_IEE         3 V-- DC 200e-6  
I_IEE1         V++ 8 DC 96e-6  
D_D2         8 9 DX    
E_EOS         10 11 VC VMID 1E-9
V_VOS         11 IN+ 150E-6
*
*1st Gain Stage
G_G1         V++ 13 6 7 0.06
G_G2         V-- 13 6 7 0.06
R_R5         13 V++  1
R_R6         V-- 13  1
V_V2         12 13 1.7
V_V3         13 14 1.7
D_D3         12 V++ DX
D_D4         V-- 14 DX
*
*2nd Gain Stage
G_G3         V++ 15 13 VMID 4.712E-3
G_G4         V-- 15 13 VMID 4.712E-3
R_R7         15 V++  2122.196e6 
R_R8         V-- 15  2122.196e6
V_V4         16 15 1.7
V_V5         15 17 1.7
D_D5         16 V++ DX
D_D6         V-- 17 DX
C_C4         15 V++  1e-9
C_C5         V-- 15  1e-9
*
*Mid supply Ref
R_R9         VMID V++  1
R_R10         V-- VMID  1
E_E1         V++ 0 V+ 0 1
E_E2         V-- 0 V- 0 1
I_ISY         V+ V- DC 1.18e-3  
*
*Common Mode Gain Stage with Zero
G_G5         V++ VC VCM VMID 0.1e-6
G_G6         V-- VC VCM VMID 0.1e-6
R_R11         VC 18  1
R_R12         19 VC  1
L_L1         18 V++  318.31927e-6  
L_L2         19 V--  318.31927e-6  
*
*2nd Pole Stage
G_G7         V++ 20 15 VMID 502.64e-6
G_G8         V-- 20 15 VMID 502.64e-6
G_G9         V++ 21 20 VMID 502.64e-6
G_G10         V-- 21 20 VMID 502.64e-6
R_R13         20 V++  1989.49546
R_R14         V-- 20  1989.49546
R_R15         21 V++  1989.49546
R_R16         V-- 21  1989.49546
C_C6         20 V++  10e-12 
C_C7         V-- 20  10e-12
C_C8         21 V++  10e-12
C_C9         V-- 21  10e-12
*
*Output Stage with Correction Current Sources
G_G11         VOUT V++ V++ 21 1.11e-2
G_G12         V-- VOUT 21 V-- 1.11e-2
G_G13         22 V-- VOUT 21 1.11e-2
G_G14         25 V-- 21 VOUT 1.11e-2
D_D7         21 23 DX
D_D8         24 21 DX
D_D9         V++ 22 DX
D_D10         V++ 25 DX
D_D11         V-- 22 DY
D_D12         V-- 25 DY
V_V6         23 VOUT 0.18
V_V7         VOUT 24 0.18
R_R17         VOUT V++  9E1
R_R18         V-- VOUT  9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12  
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 +rb=140 re=0.011 rc=900 cje=0.2E-12 +cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 
+ cjc=0.44E-12 
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends *ISL28177 Macromodel
**Revision History:
*Revision A, LaFontaine December 14, 2011
*Model for Noise, quiescent supply currents,
*CMRR 145dB, fcm=500kHz, AVOL 140dB 
*f=0.075Hz SR = 0.2V/us, GBWP 600kHz, 
*2nd pole 8Mhz, output voltage clamp 
*and short ckt current limit.
*
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT", Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*	+input
*	|	-input
* 	| 		| 	+Vsupply
* 	| 		| 		|	-Vsupply
* 	| 		| 		| 	|		output
* 	| 		| 		| 	| 			|
.subckt ISL28177 Vin+ Vin- V+ V- VOUT
* source ISL28177_SPICEMODEL
*
*Voltage Noise
E_En         IN+ VIN+ 2 0 1
D_D1         1 2 DN
V_V1         1 0 0.07
R_R19         2 0  5000
*
*Input Stage
I_IOS         IN+ VIN- DC 1e-9  
C_C1         IN+ VIN-  1.2e-12 
C_C2         0 VIN-  2e-12
C_C3         0 IN+ 2e-12
R_R1         VCM VIN-  5e11
R_R2         IN+ VCM  5e11 
R_R3         6 V++  4.45e3
R_R4         7 V++  4.45e3
Q_Q1         4 VIN- 3 SuperB
Q_Q2         5 10 3 SuperB
Q_Q3         V-- 3 9 Mirror
Q_Q4         6 8 4 Cascode
Q_Q5         7 8 5 Cascode
I_IEE         3 V-- DC 200e-6  
I_IEE1         V++ 8 DC 96e-6  
D_D2         8 9 DX    
E_EOS         10 11 VC VMID 1E-9
V_VOS         11 IN+ 150E-6
*
*1st Gain Stage
G_G1         V++ 13 6 7 0.06
G_G2         V-- 13 6 7 0.06
R_R5         13 V++  1
R_R6         V-- 13  1
V_V2         12 13 1.7
V_V3         13 14 1.7
D_D3         12 V++ DX
D_D4         V-- 14 DX
*
*2nd Gain Stage
G_G3         V++ 15 13 VMID 4.712E-3
G_G4         V-- 15 13 VMID 4.712E-3
R_R7         15 V++  2122.196e6 
R_R8         V-- 15  2122.196e6
V_V4         16 15 1.7
V_V5         15 17 1.7
D_D5         16 V++ DX
D_D6         V-- 17 DX
C_C4         15 V++  1e-9
C_C5         V-- 15  1e-9
*
*Mid supply Ref
R_R9         VMID V++  1
R_R10         V-- VMID  1
E_E1         V++ 0 V+ 0 1
E_E2         V-- 0 V- 0 1
I_ISY         V+ V- DC 1.18e-3  
*
*Common Mode Gain Stage with Zero
G_G5         V++ VC VCM VMID 0.1e-6
G_G6         V-- VC VCM VMID 0.1e-6
R_R11         VC 18  1
R_R12         19 VC  1
L_L1         18 V++  318.31927e-6  
L_L2         19 V--  318.31927e-6  
*
*2nd Pole Stage
G_G7         V++ 20 15 VMID 502.64e-6
G_G8         V-- 20 15 VMID 502.64e-6
G_G9         V++ 21 20 VMID 502.64e-6
G_G10         V-- 21 20 VMID 502.64e-6
R_R13         20 V++  1989.49546
R_R14         V-- 20  1989.49546
R_R15         21 V++  1989.49546
R_R16         V-- 21  1989.49546
C_C6         20 V++  10e-12 
C_C7         V-- 20  10e-12
C_C8         21 V++  10e-12
C_C9         V-- 21  10e-12
*
*Output Stage with Correction Current Sources
G_G11         VOUT V++ V++ 21 1.11e-2
G_G12         V-- VOUT 21 V-- 1.11e-2
G_G13         22 V-- VOUT 21 1.11e-2
G_G14         25 V-- 21 VOUT 1.11e-2
D_D7         21 23 DX
D_D8         24 21 DX
D_D9         V++ 22 DX
D_D10         V++ 25 DX
D_D11         V-- 22 DY
D_D12         V-- 25 DY
V_V6         23 VOUT 0.18
V_V7         VOUT 24 0.18
R_R17         VOUT V++  9E1
R_R18         V-- VOUT  9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12  
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 +rb=140 re=0.011 rc=900 cje=0.2E-12 +cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 
+ cjc=0.44E-12 
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28177subckt
*ISL28177 Macromodel
**Revision History:
*Revision A, LaFontaine December 14, 2011
*Model for Noise, quiescent supply currents,
*CMRR 145dB, fcm=500kHz, AVOL 140dB 
*f=0.075Hz SR = 0.2V/us, GBWP 600kHz, 
*2nd pole 8Mhz, output voltage clamp 
*and short ckt current limit.
*
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT", Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*	+input
*	|	-input
* 	| 		| 	+Vsupply
* 	| 		| 		|	-Vsupply
* 	| 		| 		| 	|		output
* 	| 		| 		| 	| 			|
.subckt ISL28177 Vin+ Vin- V+ V- VOUT
* source ISL28177_SPICEMODEL
*
*Voltage Noise
E_En         IN+ VIN+ 2 0 1
D_D1         1 2 DN
V_V1         1 0 0.07
R_R19         2 0  5000
*
*Input Stage
I_IOS         IN+ VIN- DC 1e-9  
C_C1         IN+ VIN-  1.2e-12 
C_C2         0 VIN-  2e-12
C_C3         0 IN+ 2e-12
R_R1         VCM VIN-  5e11
R_R2         IN+ VCM  5e11 
R_R3         6 V++  4.45e3
R_R4         7 V++  4.45e3
Q_Q1         4 VIN- 3 SuperB
Q_Q2         5 10 3 SuperB
Q_Q3         V-- 3 9 Mirror
Q_Q4         6 8 4 Cascode
Q_Q5         7 8 5 Cascode
I_IEE         3 V-- DC 200e-6  
I_IEE1         V++ 8 DC 96e-6  
D_D2         8 9 DX    
E_EOS         10 11 VC VMID 1E-9
V_VOS         11 IN+ 150E-6
*
*1st Gain Stage
G_G1         V++ 13 6 7 0.06
G_G2         V-- 13 6 7 0.06
R_R5         13 V++  1
R_R6         V-- 13  1
V_V2         12 13 1.7
V_V3         13 14 1.7
D_D3         12 V++ DX
D_D4         V-- 14 DX
*
*2nd Gain Stage
G_G3         V++ 15 13 VMID 4.712E-3
G_G4         V-- 15 13 VMID 4.712E-3
R_R7         15 V++  2122.196e6 
R_R8         V-- 15  2122.196e6
V_V4         16 15 1.7
V_V5         15 17 1.7
D_D5         16 V++ DX
D_D6         V-- 17 DX
C_C4         15 V++  1e-9
C_C5         V-- 15  1e-9
*
*Mid supply Ref
R_R9         VMID V++  1
R_R10         V-- VMID  1
E_E1         V++ 0 V+ 0 1
E_E2         V-- 0 V- 0 1
I_ISY         V+ V- DC 1.18e-3  
*
*Common Mode Gain Stage with Zero
G_G5         V++ VC VCM VMID 0.1e-6
G_G6         V-- VC VCM VMID 0.1e-6
R_R11         VC 18  1
R_R12         19 VC  1
L_L1         18 V++  318.31927e-6  
L_L2         19 V--  318.31927e-6  
*
*2nd Pole Stage
G_G7         V++ 20 15 VMID 502.64e-6
G_G8         V-- 20 15 VMID 502.64e-6
G_G9         V++ 21 20 VMID 502.64e-6
G_G10         V-- 21 20 VMID 502.64e-6
R_R13         20 V++  1989.49546
R_R14         V-- 20  1989.49546
R_R15         21 V++  1989.49546
R_R16         V-- 21  1989.49546
C_C6         20 V++  10e-12 
C_C7         V-- 20  10e-12
C_C8         21 V++  10e-12
C_C9         V-- 21  10e-12
*
*Output Stage with Correction Current Sources
G_G11         VOUT V++ V++ 21 1.11e-2
G_G12         V-- VOUT 21 V-- 1.11e-2
G_G13         22 V-- VOUT 21 1.11e-2
G_G14         25 V-- 21 VOUT 1.11e-2
D_D7         21 23 DX
D_D8         24 21 DX
D_D9         V++ 22 DX
D_D10         V++ 25 DX
D_D11         V-- 22 DY
D_D12         V-- 25 DY
V_V6         23 VOUT 0.18
V_V7         VOUT 24 0.18
R_R17         VOUT V++  9E1
R_R18         V-- VOUT  9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12  
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 +rb=140 re=0.011 rc=900 cje=0.2E-12 +cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 
+ cjc=0.44E-12 
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28177subckt
*ISL28177 Macromodel
**Revision History:
*Revision A, LaFontaine December 14, 2011
*Model for Noise, quiescent supply currents,
*CMRR 145dB, fcm=500kHz, AVOL 140dB 
*f=0.075Hz SR = 0.2V/us, GBWP 600kHz, 
*2nd pole 8Mhz, output voltage clamp 
*and short ckt current limit.
*
*Copyright 2011 by Intersil Corporation
*Refer to data sheet "LICENSE
*STATEMENT", Use of this model indicates
*your acceptance with the terms and
*provisions in the License Statement.
*
*Intended use:
*This Pspice Macromodel is intended to give
*typical DC and AC performance
*characteristics under a wide range of
*external circuit configurations using
*compatible simulation platforms - such as
*iSim PE.
*
*Device performance features supported by
*this model
*Typical, room temp., nominal power supply
*voltages used to produce the following
*characteristics:
*Open and closed loop I/O impedances
*Open loop gain and phase
*Closed loop bandwidth and frequency
*response
*Loading effects on closed loop frequency
*response
*Input noise terms including 1/f effects
*Slew rate
*Input and Output Headroom limits to I/O
*voltage swing
*Supply current at nominal specified supply
*voltages
**
*Device performance features NOT
*supported by this model:
*Harmonic distortion effects
*Disable operation (if any)
*Thermal effects and/or over temperature
*parameter variation
*Limited performance variation vs. supply
*voltage is modeled
*Part to part performance variation due to
*normal process parameter spread
*Any performance difference arising from
*different packaging
* source
:
*	+input
*	|	-input
* 	| 		| 	+Vsupply
* 	| 		| 		|	-Vsupply
* 	| 		| 		| 	|		output
* 	| 		| 		| 	| 			|
.subckt ISL28177 Vin+ Vin- V+ V- VOUT
* source ISL28177_SPICEMODEL
*
*Voltage Noise
E_En         IN+ VIN+ 2 0 1
D_D1         1 2 DN
V_V1         1 0 0.07
R_R19         2 0  5000
*
*Input Stage
I_IOS         IN+ VIN- DC 1e-9  
C_C1         IN+ VIN-  1.2e-12 
C_C2         0 VIN-  2e-12
C_C3         0 IN+ 2e-12
R_R1         VCM VIN-  5e11
R_R2         IN+ VCM  5e11 
R_R3         6 V++  4.45e3
R_R4         7 V++  4.45e3
Q_Q1         4 VIN- 3 SuperB
Q_Q2         5 10 3 SuperB
Q_Q3         V-- 3 9 Mirror
Q_Q4         6 8 4 Cascode
Q_Q5         7 8 5 Cascode
I_IEE         3 V-- DC 200e-6  
I_IEE1         V++ 8 DC 96e-6  
D_D2         8 9 DX    
E_EOS         10 11 VC VMID 1E-9
V_VOS         11 IN+ 150E-6
*
*1st Gain Stage
G_G1         V++ 13 6 7 0.06
G_G2         V-- 13 6 7 0.06
R_R5         13 V++  1
R_R6         V-- 13  1
V_V2         12 13 1.7
V_V3         13 14 1.7
D_D3         12 V++ DX
D_D4         V-- 14 DX
*
*2nd Gain Stage
G_G3         V++ 15 13 VMID 4.712E-3
G_G4         V-- 15 13 VMID 4.712E-3
R_R7         15 V++  2122.196e6 
R_R8         V-- 15  2122.196e6
V_V4         16 15 1.7
V_V5         15 17 1.7
D_D5         16 V++ DX
D_D6         V-- 17 DX
C_C4         15 V++  1e-9
C_C5         V-- 15  1e-9
*
*Mid supply Ref
R_R9         VMID V++  1
R_R10         V-- VMID  1
E_E1         V++ 0 V+ 0 1
E_E2         V-- 0 V- 0 1
I_ISY         V+ V- DC 1.18e-3  
*
*Common Mode Gain Stage with Zero
G_G5         V++ VC VCM VMID 0.1e-6
G_G6         V-- VC VCM VMID 0.1e-6
R_R11         VC 18  1
R_R12         19 VC  1
L_L1         18 V++  318.31927e-6  
L_L2         19 V--  318.31927e-6  
*
*2nd Pole Stage
G_G7         V++ 20 15 VMID 502.64e-6
G_G8         V-- 20 15 VMID 502.64e-6
G_G9         V++ 21 20 VMID 502.64e-6
G_G10         V-- 21 20 VMID 502.64e-6
R_R13         20 V++  1989.49546
R_R14         V-- 20  1989.49546
R_R15         21 V++  1989.49546
R_R16         V-- 21  1989.49546
C_C6         20 V++  10e-12 
C_C7         V-- 20  10e-12
C_C8         21 V++  10e-12
C_C9         V-- 21  10e-12
*
*Output Stage with Correction Current Sources
G_G11         VOUT V++ V++ 21 1.11e-2
G_G12         V-- VOUT 21 V-- 1.11e-2
G_G13         22 V-- VOUT 21 1.11e-2
G_G14         25 V-- 21 VOUT 1.11e-2
D_D7         21 23 DX
D_D8         24 21 DX
D_D9         V++ 22 DX
D_D10         V++ 25 DX
D_D11         V-- 22 DY
D_D12         V-- 25 DY
V_V6         23 VOUT 0.18
V_V7         VOUT 24 0.18
R_R17         VOUT V++  9E1
R_R18         V-- VOUT  9E1
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12  
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 +rb=140 re=0.011 rc=900 cje=0.2E-12 +cjc=0.16E-12f kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 
+ cjc=0.44E-12 
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends subckt ISL28177