*ISL28190 Macromodel ¨C also used for the following related devices *ISL28290 (dual channel versions) * *Revision History: Rev.4,Nov. 2009 by Jian Wang *Rev.5, March 2010, Added/Correcting Input/Output headroom limits (by Jian Wang) *Rev.6, January 2015, Updated output voltage limit Vih and Vil (by Matt Fortin) *Intended use: This Pspice Macromodel is intended to give typical DC and AC *performance characteristics under a wide range of external circuit configurations *using compatible simulation platforms ¨C such as iSim PE. * *Device performance features supported by this model: *Typical, room temp., nominal power supply voltages used to produce the following characteristics *Open and closed loop I/O impedances *Open loop gain and phase *Closed loop bandwidth and frequency response peaking under different external conditions *Loading effects on closed loop frequency response *Input noise terms including 1/f effects *Slew rate *Input and Output Headroom limits to I/O voltage swing *Supply current at nominal specified supply voltages *Nominal input DC error terms (1/3 of specified data sheet test or specified limits *¨C intended to give 1¦Ò error term on one polarity) *Load current reflected into the power supply current * *Device performance features NOT supported by this model: *Harmonic distortion effects *Composite video differential gain and phase errors *Output current limiting (if any) *Disable operation (if any) *Thermal effects and/or over temperature parameter variation *Limited performance variation vs. supply voltage is modeled *Part to part performance variation due to normal process parameter spread *Any performance difference arising from different packaging * *LICENSE STATEMENT *The information in this SPICE model is protected under *the United States copyright laws. Intersil Corporation hereby *grants users of this macro-model hereto referred to *as "Licensee", a nonexclusive, nontransferable license to use *this model as long as the Licensee abides by the terms of this agreement. *Before using this macro-model, the Licensee should read this license. *If this Licensee does not accept these terms, *permission to use the model is not granted. *The Licensee may not sell, loan, rent, or license the macro-model, *in whole, in part, or in modified form, to anyone *outside the Licensee's company. The Licensee may *modify the macro-model to suit his/her specific applications, *and the Licensee may make copies of this macro-model for use within *their company only. *This macro-model is provided "AS IS, WHERE IS, AND WITH NO *WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT *NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS *FOR A PARTICULAR PURPOSE." *In no event will Intersil be liable for special, collateral, *incidental, or consequential damages in connection with or arising *out of the use of this macro-model. Intersil reserves the right to *make changes to the product and the macro-model without prior notice. * * connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output * | | | | | .subckt ISL28190 Vin+ Vin- V+ V- Vout *Input Stage C_Cin1 Vin+ 0 2.2p C_Cin2 Vin- 0 2.2p C_Cdiff Vin+ Vin- 2p V_Vos 2 Vin- 240uVdc R_R1 4 3 10 R_R2 3 5 10 M_M2 7 2 5 5 pmosisil + L=20u + W=400u M_M3 6 1 4 4 pmosisil + L=20u + W=400u I_I1 V+ V- DC 1mA I_I2 V+ 3 DC 5mA R_R3 V- 6 100 R_R4 V- 7 100 I_Ib1 0 Vin+ DC 9.98uAdc I_Ib2 0 Vin- DC 10.02uAdc *Gain Stage, SR Limiting G_G1 V+ VV1 7 6 0.004 G_G2 V- VV1 7 6 0.004 V_V3 9 VV1 0.8Vdc V_V4 VV1 8 0.8Vdc D_D1 9 V+ DX D_D2 V- 8 DX R_R5 VV1 V+ 1k R_R6 V- VV1 1k *First Pole, SR Limiting G_G3 V+ VV2 VV1 10 0.01 G_G4 V- VV2 VV1 10 0.01 C_C1 VV2 V+ 231p C_C2 V- VV2 231p V_V5 11 VV2 0.7Vdc V_V6 VV2 12 0.7Vdc D_D3 11 V+ DX D_D4 V- 12 DX R_R7 VV2 V+ 4Meg R_R8 V- VV2 4Meg R_R11 11 0 1G R_R12 12 0 1G E_E3 10 V- V+ V- 0.5 *Second Pole Stage G_G5 V+ VV3 VV2 10 0.00001 G_G6 V- VV3 VV2 10 0.00001 R_R9 VV3 V+ 100k R_R10 V- VV3 100k C_C3 VV3 V+ 0.008p C_C4 V- VV3 0.008p *third Pole Stage G_G7 V+ VV4 VV3 10 0.00001 G_G8 V- VV4 VV3 10 0.00001 R_R15 VV4 V+ 100k R_R16 V- VV4 100k C_C5 VV4 V+ 0.004p C_C6 V- VV4 0.004p *Output Stage G_G9 13 V- VOUT VV4 0.0001 G_G10 14 V- VV4 VOUT 0.0001 G_G11 V+ VOUT V+ VV4 -0.02 G_G12 VOUT V- VV4 V- -0.02 D_D5 V+ 13 DX D_D6 V+ 14 DX D_D7 V- 13 DY D_D8 V- 14 DY R_R13 VOUT V+ 50 R_R14 V- VOUT 50 *Voltage Noise D_DN1 102 101 Iden D_DN2 104 103 Iden R_R21 0 101 1 R_R22 0 103 1 E_EN 1 Vin+ 101 103 2 V_V15 102 0 1Vdc V_V16 104 0 1Vdc *Current Noise G_Gn2 VIN+ 0 NI2 0 1 G_Gn1 VIN- 0 NI1 0 1 R_R23 NI2 0 0.00053 R_R24 NI2 0 0.00053 R_R25 NI1 0 0.00053 R_R26 NI1 0 0.00053 .model pmosisil pmos (kp=20e-3 vto=10m) .model Iden d(kf=160e-17 af=1) .MODEL DY D(IS=1E-20 BV=50 Rs=1) .MODEL DX D(IS=1E-15 Rs=1) .ends ISL28190