Tundra Semiconductor Tsi107 Pinout (80C2000_PN001_02)
-------------------------------------------------------

This document lists the pinout for the Tsi107. For more information on the pinout or for signal descriptions, see the Tsi107 Hardware Specification and the Tsi107 User Manual.

Copyright September 2008 Tundra Semiconductor Corporation. All rights reserved. Published in Canada. TUNDRA and Tsi107 are trademarks of Tundra Semiconductor Corporation.

Disclaimer: Tundra assumes no responsibility for the accuracy or completeness of the information presented, which is subject to change without notice. In no event will Tundra be liable for any direct, indirect, special, incidental or consequential damages, including lost profits, lost business or lost data, resulting from the use of or reliance upon the information, whether or not Tundra has been advised of the possibility of such damages. Mention of non-Tundra products or services is for information purposes only and constitutes neither an endorsement nor a recommendation. 

Revision History

September 2008, 80C2000_PN001_02 - This version was updated with various pin name changes. No technical changes were made to the pinlist. 
* D6 changed from RTC to TEST2_. 
* V24 changed from SUSPEND_ to TEST1_. 
* All pins named G were changed to GND. 

November 2003, 80C2000_PN001_01 - This is the first Tundra release of the Tsi107 pinlist. 


Pin	Signal Name
-----------------------
A2	CAS/DQM_(0)
A3	WE_
A4	AS_
A5	SDMA(00)
A6	SDMA(01)
A7	SDMA(03)
A8	SDBA1
A9	SDBA0
A10	CAS/DQM_(3)
A11	CAS/DQM_(2)
A12	CKE
A13	FOE_
A14	PAR/AR(3)
A15	PAR/AR(2)
A16	MDL(18)
A17	MDL(21)
A18	MDL(22)
A19	MDL(23)
A20	MDL(28)
A21	MDL(31)
A22	MDH(31)
A23	AD(06)
A24	C/BE_(0)
A25	AD(08)
AA1	DH(26)
AA2	DH(27)
AA3	bvdd
AA4	DH(28)
AA5	bvdd
AA6	DL(03)
AA7	DL(00)
AA8	A(17)
AA9	bvdd
AA10	TS_
AA11	bvdd
AA12	CPU_CLK(0)
AA13	CPU_CLK(1)
AA14	A(02)
AA15	bvdd
AA16	A(23)
AA17	bvdd
AA18	TT(04)
AA19	TT(03)
AA20	A(10)
AA21	GND
AA22	vdd
AA23	HRESET_
AA24	TRST_
AA25	Test_
AB1	DH(29)
AB2	DL(29)
AB3	DH(30)
AB4	DH(31)
AB5	DL(04)
AB6	DL(02)
AB7	DL(07)
AB8	A(25)
AB9	A(15)
AB10	DBGLB_
AB11	TEA_
AB12	CPU_CLK(2)
AB13	A(28)
AB14	A(16)
AB15	A(09)
AB16	A(07)
AB17	BR0_
AB18	TSIZ(02)
AB19	TT(02)
AB20	A(08)
AB21	HRESET_CPU_
AB22	GND
AB23	vdd
AB24	SDA
AB25	SCL
AC1	DL(31)
AC2	DL(30)
AC3	GND
AC4	DL(05)
AC5	GND
AC6	bvdd
AC7	AACK_
AC8	GND
AC9	bvdd
AC10	DBG0_
AC11	GND
AC12	bvdd
AC13	A(18)
AC14	GND
AC15	bvdd
AC16	WT_
AC17	GND
AC18	bvdd
AC19	TT(01)
AC20	GND
AC21	bvdd
AC22	PLL_CFG(0)
AC23	GND
AC24	vdd
AC25	NMI
AD1	DP(03)
AD2	bvdd
AD3	DL(06)
AD4	DP(06)
AD5	DL(28)
AD6	DP(01)
AD7	DP(05)
AD8	DP(02)
AD9	A(31)
AD10	DBG1_
AD11	BG1_
AD12	A(26)
AD13	A(11)
AD14	A(05)
AD15	A(14)
AD16	CI_
AD17	GBL_
AD18	TSIZ(01)
AD19	TT(00)
AD20	A(06)
AD21	A(04)
AD22	PLL_CFG(2)
AD23	PLL_CFG(1)
AD24	GND
AD25	vdd
AE1	DL(08)
AE2	DL(25)
AE3	DL(26)
AE4	DL(23)
AE5	DP(07)
AE6	DL(24)
AE7	DL(27)
AE8	DP(04)
AE9	DP(00)
AE10	A(27)
AE11	BG0_
AE12	A(13)
AE13	A(22)
AE14	TA_
AE15	A(21)
AE16	A(01)
AE17	A(03)
AE18	QACK_
AE19	TSIZ(00)
AE20	MCP_
AE21	TBST_
AE22	A(00)
AE23	PLL_CFG(3)
AE24	avdd
AE25	GND
B1	CAS/DQM_(1)
B2	gvdd
B3	CAS/DQM_(4)
B4	SDRAS_
B5	RCS2_
B6	SDMA(02)
B7	SDMA(04)
B8	SDMA(07)
B9	RCS1_
B10	RAS/CS_(6)
B11	RAS/CS_(7)
B12	MTP(1)
B13	MTP(2)
B14	MDH(16)
B15	MDH(18)
B16	MDL(20)
B17	MDH(24)
B18	MDL(24)
B19	MDH(28)
B20	MDH(29)
B21	MDH(30)
B22	AD(04)
B23	AD(05)
B24	ovdd
B25	AD(07)
C1	PAR/AR(1)
C2	CAS/DQM_(5)
C3	GND
C4	RAS/CS_(1)
C5	gvdd
C6	GND
C7	SDMA(05)
C8	gvdd
C9	GND
C10	RAS/CS_(4)
C11	gvdd
C12	GND
C13	PAR/AR(7)
C14	gvdd
C15	GND
C16	MDH(21)
C17	gvdd
C18	GND
C19	MDL(29)
C20	gvdd
C21	GND
C22	AD(03)
C23	GND
C24	IRQ_1/S_CLK
C25	AD(02)
D1	PAR/AR(4)
D2	PAR/AR(0)
D3	PAR/AR(5)
D4	SDCAS_
D5	RAS/CS_(2)
D6	TEST2_
D7	RCS3_
D8	SDMA(08)
D9	SDMA(11)
D10	RCS0_
D11	CAS/DQM_(7)
D12	SDRAM_SYNC_OUT
D13	SDRAM_CLK(1)
D14	SDRAM_CLK(0)
D15	MDH(17)
D16	MDH(20)
D17	MDH(23)
D18	MDH(22)
D19	MDL(26)
D20	MDL(30)
D21	AD(00)
D22	lvdd(1)
D23	AD(01)
D24	FTP(3)
D25	AD(09)
E1	MDH(15)
E2	MDL(15)
E3	GND
E4	RAS/CS_(3)
E5	gvdd
E6	RAS/CS_(0)
E7	SDMA(06)
E8	SDMA(09)
E9	gvdd
E10	SDMA(13)
E11	gvdd
E12	SDRAM_CLK(2)
E13	SDRAM_SYNC_IN
E14	SDRAM_CLK(3)
E15	gvdd
E16	MDH(19)
E17	gvdd
E18	MDL(25)
E19	MDH(26)
E20	MDH(27)
E21	ovdd
E22	AD(10)
E23	ovdd
E24	AD(11)
E25	AD(13)
F1	MDH(14)
F2	MDL(14)
F3	gvdd
F4	MDL(12)
F5	MDH(13)
F6	GND
F7	lavdd
F8	SDMA(10)
F9	SDMA(12)
F10	GND
F11	RAS/CS_(5)
F12	CAS/DQM_(6)
F13	PAR/AR(6)
F14	MDL(16)
F15	MDL(17)
F16	GND
F17	MDL(19)
F18	MDH(25)
F19	MDL(27)
F20	GND
F21	AD(12)
F22	lvdd(2)
F23	GND
F24	AD(14)
F25	SERR_
G1	MDL(13)
G2	MDL(10)
G3	MDH(10)
G4	MDL(11)
G5	MDH(11)
G6	MDH(12)
G7	gvdd
G8	GND
G9	gvdd
G10	vdd
G11	GND
G12	gvdd
G13	GND
G14	gvdd
G15	GND
G16	vdd
G17	gvdd
G18	GND
G19	gvdd
G20	FRAME_
G21	LOCK_
G22	C/BE_(1)
G23	DEVSEL_
G24	PAR
G25	PERR_
H1	MDL(07)
H2	MDL(08)
H3	GND
H4	MDH(08)
H5	MDH(09)
H6	MDL(09)
H7	GND
H19	GND
H20	AD(15)
H21	STOP_
H22	lvdd(3)
H23	ovdd
H24	IRDY_
H25	TRDY_
J1	MDL(05)
J2	MDL(06)
J3	gvdd
J4	MDH(06)
J5	gvdd
J6	MDH(07)
J7	gvdd
J19	ovdd
J20	AD(18)
J21	ovdd
J22	C/BE_(2)
J23	GND
J24	AD(17)
J25	AD(16)
K1	MDL(03)
K2	MDH(03)
K3	MDL(04)
K4	MDH(04)
K5	MDH(05)
K6	GND
K7	vdd
K19	vdd
K20	GND
K21	AD(19)
K22	lvdd(4)
K23	AD(20)
K24	AD(21)
K25	AD(22)
L1	MDL(01)
L2	MDL(02)
L3	GND
L4	MDH(01)
L5	gvdd
L6	MDH(02)
L7	GND
L19	GND
L20	AD(24)
L21	ovdd
L22	AD(23)
L23	ovdd
L24	C/BE_(3)
L25	IDSEL
M1	DL(11)
M2	DL(16)
M3	gvdd
M4	QREQ_
M5	MDL(00)
M6	MDH(00)
M7	gvdd
M19	ovdd
M20	AD(29)
M21	AD(28)
M22	AD(27)
M23	GND
M24	AD(26)
M25	AD(25)
N1	DL(15)
N2	DL(21)
N3	DL(12)
N4	DL(13)
N5	DL(14)
N6	DL(10)
N7	GND
N19	GND
N20	GNT_(0)
N21	AD(30)
N22	lvdd(5)
N23	AD(31)
N24	PCI_CLK(3)
N25	PCI_CLK(4)
P1	DH(00)
P2	DH(02)
P3	GND
P4	DL(20)
P5	DL(19)
P6	DH(07)
P7	bvdd
P19	ovdd
P20	PCI_SYNC_IN
P21	GNT_(2)
P22	GNT_(3)
P23	ovdd
P24	PCI_CLK(1)
P25	PCI_SYNC_OUT
R1	DH(01)
R2	DL(17)
R3	bvdd
R4	DH(06)
R5	bvdd
R6	DH(13)
R7	GND
R19	GND
R20	FTP(2)
R21	ovdd
R22	GNT_(1)
R23	GND
R24	PCI_CLK(2)
R25	PCI_CLK(0)
T1	DH(04)
T2	DH(18)
T3	DH(05)
T4	DH(03)
T5	DH(11)
T6	GND
T7	vdd
T19	vdd
T20	GND
T21	IRQ_2/S_RST
T22	lvdd(6)
T23	REQ_(0)
T24	GNT_(4)
T25	REQ_(1)
U1	DH(12)
U2	DL(22)
U3	GND
U4	DH(17)
U5	bvdd
U6	DH(08)
U7	bvdd
U19	ovdd
U20	IRQ_3/S_FRAME
U21	ovdd
U22	OSC_IN
U23	ovdd
U24	IRQ_0/S_INT
U25	REQ_(2)
V1	DL(18)
V2	DH(10)
V3	bvdd
V4	DH(15)
V5	DH(09)
V6	DH(19)
V7	GND
V19	GND
V20	CKO
V21	INTA_
V22	IRQ_4
V23	GND
V24	TEST1_
V25	REQ_(3)
W1	DH(14)
W2	DH(16)
W3	DH(20)
W4	DL(09)
W5	DH(21)
W6	DL(01)
W7	bvdd
W8	GND
W9	bvdd
W10	vdd
W11	GND
W12	bvdd
W13	GND
W14	bvdd
W15	GND
W16	vdd
W17	bvdd
W18	GND
W19	vdd
W20	vdd
W21	Trig_Out
W22	Trig_In
W23	TDO
W24	TCK
W25	REQ_(4)
Y1	DH(22)
Y2	DH(23)
Y3	GND
Y4	DH(24)
Y5	DH(25)
Y6	GND
Y7	ARTRY_
Y8	A(30)
Y9	A(29)
Y10	GND
Y11	A(20)
Y12	A(19)
Y13	A(24)
Y14	BR1_
Y15	A(12)
Y16	GND
Y17	LBCLAIM_
Y18	SRESET_
Y19	GND
Y20	GND
Y21	vdd
Y22	INT_
Y23	ovdd
Y24	TMS
Y25	TDI