Tsi110 Pinlist (80E5000_PN001_04) -- Integrated Device Technology, Inc. ------------------------------------------------------------------------------------------------------------- This document contains the Tsi110 pinlist. For information signal descriptions, see the Tsi110 User Manual (80E5000_MA001). Note, 80E5000_PN001_04 release was updated for IDT formatting. There have been no technical changes. Copyright © September 2009 Integrated Device Technology, Inc.. All rights reserved. GENERAL DISCLAIMER Integrated Device Technology, Inc. ("IDT") reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance. IDT does not assume responsibility for use of any circuitry described herein other than the circuitry embodied in an IDT product. Disclosure of the information herein does not convey a license or any other right, by implication or otherwise, in any patent, trademark, or other intellectual property right of IDT. IDT products may contain errata which can affect product performance to a minor or immaterial degree. Current characterized errata will be made available upon request. Items identified herein as "reserved" or "undefined" are reserved for future definition. IDT does not assume responsibility for conflicts or incompatibilities arising from the future definition of such items. IDT products have not been designed, tested, or manufactured for use in, and thus are not warranted for, applications where the failure, malfunction, or any inaccuracy in the application carries a risk of death, serious bodily injury, or damage to tangible property. Code examples provided herein by IDT are for illustrative purposes only and should not be relied upon for developing applications. Any use of such code examples shall be at the user's sole risk. A1 NO BALL A2 SD_DQ[56] A3 SD_DQ[60] A4 SD_CLK_N[5] A5 SD_CLK_N[2] A6 SD_CLK_P[2] A7 SD_DQ[34] A8 SD_DQ[38] A9 SD_DQS_P[4] A10 SD_DQS_N[13] A11 SD_DQ[33] A12 SD_DQ[32] A13 SD_DQ[36] A14 SD_CLK_N[3] A15 SD_CLKFBO_N A16 SD_CLKFBI_P A17 SD_CLK_P[0] A18 SD_DQ[19] A19 SD_DQ[18] A20 SD_DQ[23] A21 SD_DQS_P[2] A22 SD_DQS_N[11] A23 SD_DQS_P[11] A24 SD_DQ[16] A25 SD_DQ[20] A26 SD_CLK_N[4] A27 SD_CLK_N[1] A28 SD_DQ[3] A29 SD_DQ[2] A30 SD_DQ[6] A31 SD_DQS_N[0] A32 VSS_IO B1 SD_DQS_P[16] B2 SD_DQ[57] B3 VSS_IO B4 NC B5 SD_CLK_P[5] B6 VSS_IO B7 SD_DQ[35] B8 SD_DQ[39] B9 VSS_IO B10 SD_DQS_N[4] B11 SD_DQS_P[13] B12 VSS_IO B13 SD_DQ[37] B14 SD_CLK_P[3] B15 VSS_IO B16 SD_CLKFBO_P B17 SD_CLKFBI_N B18 SD_CLK_N[0] B19 VSS_IO B20 SD_DQ[22] B21 SD_DQS_N[2] B22 VSS_IO B23 SD_DQ[17] B24 SD_DQ[21] B25 VSS_IO B26 SD_CLK_P[4] B27 SD_CLK_P[1] B28 VSS_IO B29 SD_DQ[7] B30 SD_DQS_P[0] B31 VSS_IO B32 SD_DQS_N[9] C1 VSS_IO C2 SD_DQS_N[16] C3 SD_DQ[61] C4 VDD_SD C5 SD_DQ[54] C6 SD_DQS_N[6] C7 VDD_SD C8 SD_DQ[53] C9 SD_DQ[43] C10 VDD_SD C11 SD_DQS_N[5] C12 SD_DQS_P[14] C13 VDD_SD C14 NC C15 NC C16 VDD_SD C17 NC C18 VDD_SD C19 NC C20 SD_DQ[26] C21 VDD_SD C22 SD_DQS_N[12] C23 NC C24 VDD_SD C25 SD_DQ[11] C26 SD_DQ[15] C27 VDD_SD C28 NC C29 VDD_SD C30 NC C31 SD_DQS_P[9] C32 SD_DQ[1] D1 SD_DQS_P[7] D2 SD_DQS_N[7] D3 SD_DQ[62] D4 SD_DQ[51] D5 SD_DQ[55] D6 SD_DQS_P[6] D7 SD_DQS_P[15] D8 SD_DQ[48] D9 SD_DQ[52] D10 SD_DQ[47] D11 SD_DQS_P[5] D12 SD_DQS_N[14] D13 SD_DQ[40] D14 SD_DQ[44] D15 NC D16 NC D17 NC D18 NC D19 NC D20 SD_DQ[31] D21 SD_DQS_P[3] D22 SD_DQS_P[12] D23 SD_DQ[25] D24 SD_DQ[29] D25 SD_DQ[10] D26 SD_DQ[14] D27 SD_DQS_N[1] D28 SD_DQS_P[10] D29 SD_DQ[8] D30 NC D31 SD_DQ[0] D32 SD_DQ[5] E1 SD_DQ[63] E2 SD_DQ[58] E3 VSS_IO E4 NC E5 SD_DQ[50] E6 VSS_IO E7 SD_DQS_N[15] E8 SD_DQ[49] E9 VSS_IO E10 SD_DQ[42] E11 SD_DQ[46] E12 VSS_IO E13 SD_DQ[41] E14 SD_DQ[45] E15 VSS_IO E16 NC E17 NC E18 NC E19 VSS_IO E20 SD_DQ[30] E21 SD_DQS_N[3] E22 VSS_IO E23 SD_DQ[24] E24 SD_DQ[28] E25 VSS_IO E26 SD_DQS_P[1] E27 SD_DQS_N[10] E28 VDD_SD E29 SD_DQ[13] E30 VSS_IO E31 SD_DQ[4] E32 CG_PB_SELECT[1] F1 SD_DQ[59] F2 VSS_IO F3 NC F4 NC F5 NC F6 NC F7 SD_ODT[3] F8 NC F9 SD_CSn[1] F10 VDD_SD F11 SD_ODT[0] F12 NC F13 VDD_SD F14 SD_RASn F15 NC F16 SD_DLL_TEST[0] F17 VDD_SD F18 SD_DLL_TEST[1] F19 SD_DQ[27] F20 SD_A[6] F21 VDD_SD F22 SD_VREF[1] F23 SD_BA[2] F24 VDD_SD F25 NC F26 SD_CLKEN[1] F27 VSS_IO F28 SD_DQ[9] F29 SD_DQ[12] F30 PB_A[33] F31 PB_RSTn F32 CG_REF G1 HLP_AD[0] G2 HLP_AD[1] G3 SD_I2C_CLK G4 SD_I2C_SD G5 HLP_AD[8] G6 HLP_AD[9] G7 VSS_IO G8 SD_ODT[1] G9 SD_CSn[3] G10 SD_A[13] G11 SD_ODT[2] G12 SD_CASn G13 SD_WEn G14 SD_CSn[0] G15 SD_A[10] G16 SD_A[0] G17 SD_A[2] G18 SD_A[1] G19 SD_A[4] G20 SD_A[9] G21 SD_A[8] G22 SD_A[11] G23 SD_A[14] G24 SD_A[15] G25 SD_CLKEN[0] G26 VDD_SD G27 NC G28 VSS_IO G29 CG_SD_SELECT[0] G30 NC G31 VSS_IO G32 CG_SD_SELECT[1] H1 HLP_AD[2] H2 HLP_AD[3] H3 HLP_AD[4] H4 VSS_IO H5 HLP_AD[5] H6 HLP_AD[6] H7 HLP_AD[7] H8 NC H9 VSS_IO H10 VDD_SD H11 VDD_SD H12 SD_VREF[0] H13 VSS_IO H14 SD_CSn[2] H15 SD_BA[0] H16 SD_BA[1] H17 VSS_IO H18 SD_A[3] H19 SD_A[5] H20 VSS_IO H21 SD_A[7] H22 SD_A[12] H23 VDD_SD H24 VDD_SD H25 VSS_IO H26 PB_A[34] H27 VDD_PB H28 CG_SD_SELECT[2] H29 CG_PB_SELECT[2] H30 VDD_PB H31 CG_PB_CLKO[1] H32 CG_PB_CLKO[0] J1 CLKGEN_PLL_AVDD[1] J2 CLKGEN_PLL_AVSS[1] J3 HLP_AD[10] J4 HLP_AD[11] J5 HLP_AD[12] J6 HLP_AD[13] J7 HLP_AD[14] J8 HLP_AD[15] J9 VDD_PC J10 VSS_IO J11 VDD_SD J12 VSS_IO J13 VDD_SD J14 VSS_IO J15 VDD_SD J16 VSS_IO J17 VDD_SD J18 VSS_IO J19 VDD_SD J20 VSS_IO J21 VDD_SD J22 VSS_IO J23 VDD_SD J24 VSS_IO J25 PB_A[35] J26 PB_A[10] J27 PB_A[32] J28 PB_A[0] J29 PB_TSIZ[2] J30 NC J31 CG_PB_SELECT[0] J32 NC K1 HLP_AD[16] K2 VSS_IO K3 HLP_AD[17] K4 HLP_AD[18] K5 HLP_AD[19] K6 HLP_AD[20] K7 VSS_IO K8 HLP_AD[21] K9 VDD_PC K10 VDD_PC K11 VSS_IO K12 VDD_SD K13 VDD_SD K14 VDD_SD K15 VDD_SD K16 VDD_SD K17 VDD_SD K18 VDD_SD K19 VDD_SD K20 VDD_SD K21 VDD_SD K22 VDD_SD K23 VSS_IO K24 VDD_PB K25 PB_TT[3] K26 PB_A[8] K27 PB_A[6] K28 VSS_IO K29 CLKGEN_PLL_AVDD[0] K30 CLKGEN_PLL_AVSS[0] K31 VSS_IO K32 PB_A[4] L1 HLP_AD[22] L2 HLP_AD[23] L3 HLP_AD[24] L4 HLP_AD[25] L5 VSS_IO L6 HLP_AD[26] L7 HLP_AD[27] L8 HLP_AD[28] L9 VDD_PC L10 VDD_PC L11 VSS_IO L12 VSS_IO L13 VSS_IO L14 VSS_IO L15 VSS_IO L16 VSS_IO L17 VSS_IO L18 VSS_IO L19 VSS_IO L20 VSS_IO L21 VSS_IO L22 VSS_IO L23 VDD_PB L24 VDD_PB L25 RESERVED[21] L26 PB_TT[1] L27 VDD_PB L28 PB_TT[0] L29 PB_TT[4] L30 VDD_PB L31 SD_PLL_AVDD L32 SD_PLL_AVSS M1 HLP_WEn M2 HLP_CSn[0] M3 HLP_CSn[2] M4 HLP_CSn[3] M5 HLP_LE M6 HLP_AD[29] M7 HLP_AD[30] M8 HLP_AD[31] M9 VDD_PC M10 VDD_PC M11 VSS_IO M12 VSS M13 VDD M14 VSS M15 VDD M16 VSS M17 VDD M18 VSS M19 VDD M20 VSS M21 VDD M22 VSS_IO M23 VDD_PB M24 VSS_IO M25 PB_INTn[1] M26 PB_INTn[2] M27 PB_INTn[3] M28 PB_A[2] M29 PB_PLL_AVSS M30 PB_PLL_AVDD M31 PB_TSIZ[1] M32 SD_SYSCLK N1 HLP_CSn[1] N2 VSS_IO N3 HLP_RDYn N4 HLP_OEn N5 GPIO[0] N6 GPIO[1] N7 VSS_IO N8 U_1_RX N9 VDD_PC N10 VDD_PC N11 VSS_IO N12 VDD N13 VSS N14 VDD N15 VSS N16 VDD N17 VSS N18 VDD N19 VSS N20 VDD N21 VSS N22 VSS_IO N23 VDD_PB N24 VDD_PB N25 VSS_IO N26 RESERVED[0] N27 NC N28 VSS_IO N29 PB_BRn[0] N30 RESERVED[19] N31 VSS_IO N32 RESERVED[20] P1 JTAG_TDO P2 JTAG_TDI P3 GPIO[2] P4 VSS_IO P5 GPIO[3] P6 GPIO[4] P7 GPIO[5] P8 U_0_RX P9 VDD_PC P10 VDD_PC P11 VSS_IO P12 VSS P13 VDD P14 VSS P15 VDD P16 VSS P17 VDD P18 VSS P19 VDD P20 VSS P21 VDD P22 VSS_IO P23 VDD_PB P24 VSS_IO P25 RESERVED[17] P26 PB_TSIZ[0] P27 VDD_PB P28 PB_TT[2] P29 NC P30 VDD_PB P31 PB_TBSTn P32 PB_SYSCLK R1 TEST_TM[1] R2 JTAG_TCK R3 GPIO[6] R4 INT[0] R5 GPIO[7] R6 GPIO[8] R7 GPIO[9] R8 U_1_TX R9 VDD_PC R10 VDD_PC R11 VSS_IO R12 VDD R13 VSS R14 VDD R15 VSS R16 VDD R17 VSS R18 VDD R19 VSS R20 VDD R21 VSS R22 VSS_IO R23 VDD_PB R24 VDD_PB R25 PB_QACKn[0] R26 PB_A[14] R27 PB_A[23] R28 PB_GBLn R29 PB_A[7] R30 PB_A[9] R31 RESERVED[18] R32 RESERVED[1] T1 TEST_TM[3] T2 VSS_IO T3 JTAG_TRSTn T4 GPIO[10] T5 GPIO[11] T6 INT[2] T7 VSS_IO T8 U_0_TX T9 VDD_PC T10 VDD_PC T11 VSS_IO T12 VSS T13 VDD T14 VSS T15 VDD T16 VSS T17 VDD T18 VSS T19 VDD T20 VSS T21 VDD T22 VSS_IO T23 VDD_PB T24 VSS_IO T25 PB_A[24] T26 PB_A[16] T27 PB_A[3] T28 VSS_IO T29 PB_A[1] T30 PB_A[12] T31 VSS_IO T32 PB_INTn[0] U1 TEST_TM[2] U2 JTAG_TMS U3 TEST_ON U4 INT[1] U5 VSS_IO U6 GPIO[12] U7 GPIO[13] U8 I2C_SCLK U9 VDD_PC U10 VDD_PC U11 VSS_IO U12 VDD U13 VSS U14 VDD U15 VSS U16 VDD U17 VSS U18 VDD U19 VSS U20 VDD U21 VSS U22 VSS_IO U23 VDD_PB U24 VDD_PB U25 VSS_IO U26 PB_TSn U27 VDD_PB U28 PB_A[21] U29 PB_DBWOn U30 VDD_PB U31 PB_A[20] U32 PB_TAn V1 TEST_TM[0] V2 TEST_BIDR_CTL V3 OCN_RSTn V4 GPIO[14] V5 GPIO[15] V6 INT[3] V7 NC V8 I2C_SD V9 VDD_PC V10 VDD_PC V11 VSS_IO V12 VSS V13 VDD V14 VSS V15 VDD V16 VSS V17 VDD V18 VSS V19 VDD V20 VSS V21 VDD V22 VSS_IO V23 VDD_PB V24 VSS_IO V25 PB_TEAn V26 PB_A[22] V27 PB_A[18] V28 NC V29 PB_BGn[0] V30 PB_A[5] V31 PB_A[13] V32 PB_RSTOD W1 E_MDIO W2 VSS_IO W3 E_MDC W4 E_1_TCG[9] W5 E_0_TCG[9] W6 E_0_TCG[8] W7 VSS_IO W8 E_0_TCG[7] W9 VDD_PC W10 VDD_PC W11 VSS_IO W12 VDD W13 VSS W14 VDD W15 VSS W16 VDD W17 VSS W18 VDD W19 VSS W20 VDD W21 VSS W22 VSS_IO W23 VDD_PB W24 VDD_PB W25 PB_A[11] W26 PB_AACKn W27 RESERVED[2] W28 VSS_IO W29 RESERVED[3] W30 NC W31 VSS_IO W32 PB_ARTRYn Y1 E_REF125 Y2 E_1_TCG[7] Y3 E_1_TCG[6] Y4 VSS_IO Y5 E_0_TCG[6] Y6 E_0_TCG[5] Y7 E_0_TCG[4] Y8 E_0_TCG[3] Y9 VDD_PC Y10 VDD_PC Y11 VSS_IO Y12 VSS Y13 VDD Y14 VSS Y15 VDD Y16 VSS Y17 VDD Y18 VSS Y19 VDD Y20 VSS Y21 VDD Y22 VSS_IO Y23 VDD_PB Y24 VSS_IO Y25 PB_A[27] Y26 PB_A[28] Y27 PB_A[30] Y28 PB_DBGn[0] Y29 NC Y30 PB_A[17] Y31 PB_A[26] Y32 NC AA1 E_1_TCG[8] AA2 E_1_TCG[5] AA3 E_1_TCG[4] AA4 E_1_TCG[3] AA5 E_0_TCG[2] AA6 E_0_TCG[1] AA7 E_0_TCG[0] AA8 E_0_TXCLK AA9 VDD_PC AA10 VDD_PC AA11 VSS_IO AA12 VDD AA13 VSS AA14 VDD AA15 VSS AA16 VDD AA17 VSS AA18 VDD AA19 VSS AA20 VDD AA21 VSS AA22 VSS_IO AA23 VDD_PB AA24 VDD_PB AA25 VSS_IO AA26 PB_A[19] AA27 VDD_PB AA28 NC AA29 PB_QREQn[0] AA30 VDD_PB AA31 PB_A[15] AA32 PB_A[29] AB1 E_1_TXCLK AB2 VSS_IO AB3 E_1_TCG[1] AB4 E_1_TCG[0] AB5 E_0_PCOL_RBCM AB6 E_0_PRBS_PASS AB7 VSS_IO AB8 E_0_ECMDT AB9 VDD_PC AB10 VDD_PC AB11 VSS_IO AB12 VSS_IO AB13 VSS_IO AB14 VSS_IO AB15 VSS_IO AB16 VSS_IO AB17 VSS_IO AB18 VSS_IO AB19 VSS_IO AB20 VSS_IO AB21 VSS_IO AB22 VSS_IO AB23 VDD_PB AB24 VSS_IO AB25 PB_D[39] AB26 RESERVED[23] AB27 RESERVED[22] AB28 VSS_IO AB29 RESERVED[24] AB30 PB_A[25] AB31 VSS_IO AB32 PB_A[31] AC1 E_1_TCG[2] AC2 E_1_PCRS_SDET AC3 E_1_PCOL_RBCM AC4 E_1_PRBS_PASS AC5 VSS_IO AC6 E_0_PRBSEN AC7 E_0_RXCLK AC8 E_0_RCG[0] AC9 VDD_PC AC10 VDD_PC AC11 VDD_PC AC12 VDD_PC AC13 VDD_PC AC14 VDD_PC AC15 VDD_PC AC16 VDD_PC AC17 VDD_PC AC18 VDD_PC AC19 VDD_PC AC20 VSS_IO AC21 VDD_PB AC22 VSS_IO AC23 VDD_PB AC24 VDD_PB AC25 PB_D[33] AC26 PB_D[37] AC27 PB_D[19] AC28 PB_D[34] AC29 PB_D[35] AC30 PB_D[56] AC31 RESERVED[27] AC32 RESERVED[29] AD1 E_GTXCLK[0] AD2 E_1_EWRAP AD3 VSS_IO AD4 E_0_PCRS_SDET AD5 E_0_RCG[1] AD6 E_0_RCG[2] AD7 E_0_RCG[3] AD8 VSS_IO AD9 VDD_PC AD10 VDD_PC AD11 VDD_PC AD12 VDD_PC AD13 VDD_PC AD14 VDD_PC AD15 VDD_PC AD16 VDD_PC AD17 VDD_PC AD18 VDD_PC AD19 VDD_PC AD20 VSS_IO AD21 VDD_PB AD22 VDD_PB AD23 VDD_PB AD24 VSS_IO AD25 PB_D[58] AD26 RESERVED[25] AD27 VDD_PB AD28 PB_D[23] AD29 PB_D[26] AD30 VDD_PB AD31 PB_D[32] AD32 PB_D[54] AE1 E_1_ECMDT AE2 E_1_RCG[0] AE3 E_1_PRBSEN AE4 E_0_EWRAP AE5 E_0_RCG[4] AE6 E_0_RCG[5] AE7 E_0_RCG[6] AE8 PCI_AD[26] AE9 PCI_AD[20] AE10 PCI_AD[16] AE11 PCI_DEVSELn AE12 PCI_M66EN AE13 PCI_AD[5] AE14 PCI_CBEn[6] AE15 PCI_AD[60] AE16 PCI_AD[57] AE17 PCI_AD[50] AE18 PCI_AD[44] AE19 PCI_AD[38] AE20 PWRUP_PCI_HOST AE21 NC AE22 RESERVED[4] AE23 RESERVED[5] AE24 VDD_PB AE25 PB_D[60] AE26 PB_D[57] AE27 RESERVED[26] AE28 VSS_IO AE29 PB_D[18] AE30 RESERVED[28] AE31 VSS_IO AE32 PB_D[36] AF1 E_1_RXCLK AF2 VSS_IO AF3 E_1_RCG[1] AF4 VSS_IO AF5 E_0_RCG[7] AF6 E_0_RCG[8] AF7 VSS_IO AF8 PCI_AD[27] AF9 PCI_AD[21] AF10 VSS_IO AF11 PCI_STOPn AF12 PCI_AD[11] AF13 VSS_IO AF14 PCI_CBEn[5] AF15 PCI_AD[61] AF16 VSS_IO AF17 PCI_AD[51] AF18 PCI_AD[45] AF19 VSS_IO AF20 PCI_AD[34] AF21 NC AF22 VSS_IO AF23 RIU AF24 PB_D[31] AF25 VSS_IO AF26 PB_D[30] AF27 PB_D[7] AF28 PB_D[15] AF29 PB_D[14] AF30 PB_D[20] AF31 PB_D[29] AF32 PB_D[62] AG1 E_1_RCG[2] AG2 E_1_RCG[3] AG3 E_1_RCG[4] AG4 E_1_RCG[5] AG5 E_0_RCG[9] AG6 PCI_REQn[3] AG7 PCI_AD[31] AG8 PCI_AD[28] AG9 PCI_AD[22] AG10 PCI_CBEn[2] AG11 PCI_PERRn AG12 PCI_AD[12] AG13 PCI_AD[6] AG14 PCI_CBEn[0] AG15 PCI_AD[62] AG16 PCI_AD[58] AG17 PCI_AD[52] AG18 PCI_AD[46] AG19 PCI_AD[39] AG20 PCI_AD[35] AG21 PB_SENSE AG22 RESERVED[6] AG23 VDD_PB AG24 PB_D[59] AG25 PB_D[27] AG26 PB_D[38] AG27 VDD_PB AG28 PB_D[6] AG29 PB_D[11] AG30 VDD_PB AG31 PB_D[17] AG32 PB_D[22] AH1 E_GTXCLK[1] AH2 E_1_RCG[6] AH3 E_1_RCG[7] AH4 PCI_SENSE AH5 PCI_GNTn[3] AH6 PCI_REQn[2] AH7 PCI_ES AH8 VSS_IO AH9 PCI_AD[23] AH10 PCI_FRAMEn AH11 PCI_SERRn AH12 PCI_PAR AH13 PCI_AD[7] AH14 VSS_IO AH15 PCI_AD[63] AH16 PCI_CBEn[4] AH17 PCI_AD[53] AH18 PCI_AD[47] AH19 PCI_AD[40] AH20 VSS_IO AH21 RESERVED[7] AH22 RESERVED[8] AH23 RESERVED[9] AH24 PB_D[63] AH25 PB_D[61] AH26 PB_D[52] AH27 PB_D[53] AH28 VSS_IO AH29 PB_D[12] AH30 PB_D[10] AH31 VSS_IO AH32 PB_D[16] AJ1 E_1_RCG[8] AJ2 VSS_IO AJ3 PCI_INTCn AJ4 PCI_PCIXCAP[1] AJ5 VSS_IO AJ6 PCI_GNTn[7] AJ7 PCI_REQn[6] AJ8 PCI_AD[29] AJ9 PCI_AD[24] AJ10 PCI_AD[17] AJ11 VSS_IO AJ12 PCI_CBEn[1] AJ13 PCI_AD[8] AJ14 PCI_AD[1] AJ15 PCI_AD[0] AJ16 PCI_PAR64 AJ17 VSS_IO AJ18 PCI_AD[48] AJ19 PCI_AD[41] AJ20 PCI_AD[36] AJ21 PCI_CLK AJ22 RESERVED[10] AJ23 RESERVED[11] AJ24 VSS_IO AJ25 PB_D[25] AJ26 VSS_IO AJ27 PB_D[43] AJ28 PB_D[51] AJ29 PB_D[0] AJ30 PB_D[2] AJ31 PB_D[9] AJ32 PB_D[8] AK1 E_1_RCG[9] AK2 PCI_RSTDIR AK3 PCI_PCIXCAP[0] AK4 PCI_INTAn AK5 PCI_GNTn[2] AK6 PCI_GNTn[6] AK7 PCI_REQn[5] AK8 PCI_REQn[1] AK9 PCI_CBEn[3] AK10 PCI_AD[18] AK11 PCI_ENUMn AK12 PCI_AD[13] AK13 PCI_AD[9] AK14 PCI_AD[2] AK15 PCI_ACK64n AK16 PCI_AD[59] AK17 PCI_AD[54] AK18 PCI_AD[49] AK19 PCI_AD[42] AK20 PCI_AD[37] AK21 PCI_AD[32] AK22 RESERVED[12] AK23 VDD_PB AK24 PB_D[24] AK25 PB_D[28] AK26 PB_D[48] AK27 VDD_PB AK28 PB_D[40] AK29 PB_D[5] AK30 VDD_PB AK31 PB_D[1] AK32 PB_D[13] AL1 PCI_RSTn AL2 PCI_INTDn AL3 PCI_LEDn AL4 VSS_IO AL5 PCI_GNTn[1] AL6 PCI_GNTn[5] AL7 VSS_IO AL8 PCI_PMEn AL9 PCI_IDSEL AL10 VSS_IO AL11 PCI_IRDYn AL12 PCI_AD[14] AL13 VSS_IO AL14 PCI_AD[3] AL15 PCI_REQ64n AL16 VSS_IO AL17 PCI_AD[55] AL18 CG_PCI_CLKO[3] AL19 VSS_IO AL20 PCI_AD[43] AL21 PCI_PLL_AVSS AL22 VSS_IO AL23 RESERVED[13] AL24 RESERVED[14] AL25 VSS_IO AL26 PB_D[21] AL27 PB_D[47] AL28 VSS_IO AL29 PB_D[42] AL30 PB_D[55] AL31 VSS_IO AL32 PB_D[3] AM1 VSS_IO AM2 PCI_HEALTHYn AM3 PCI_HS64ENn AM4 PCI_INTBn AM5 PCI_REQn[7] AM6 PCI_GNTn[4] AM7 PCI_REQn[4] AM8 PCI_AD[30] AM9 PCI_AD[25] AM10 PCI_AD[19] AM11 PCI_TRDYn AM12 PCI_AD[15] AM13 PCI_AD[10] AM14 PCI_AD[4] AM15 PCI_AD[33] AM16 PCI_CBEn[7] AM17 CG_PCI_CLKO[1] AM18 CG_PCI_CLKO[0] AM19 CG_PCI_CLKO[2] AM20 PCI_AD[56] AM21 PCI_PLL_AVDD AM22 RESERVED[15] AM23 RESERVED[16] AM24 PB_D[45] AM25 PB_D[41] AM26 VDD_PB AM27 PB_D[46] AM28 PB_D[44] AM29 PB_D[50] AM30 PB_D[49] AM31 PB_D[4] AM32 VSS_IO