Circuit Diagram and Timing Diagram

This design works by charging and discharging C2 in Figure 1 above. The length of time it takes for C2 (the switching capacitor) to discharge is proportional to the load current. C1 is a decoupling capacitor for the GreenPAK’s power supply, and C3 is a decoupling capacitor for the output rail. This design is essentially a modified Buck design that regulates its output rail to between 1.9v and 2.0v.

The left half of Figure 1 shows the pinout of the circuit with the Power Switch inputs and outputs labeled. The right half shows how the power switches are connected inside the GreenPAK.

Figure 1. Circuit Diagram

In Figure 2 you can see the timing signals in this design. Unlike some of Silego’s GreenFET Power Switches, the SLG46517V’s two internal 45mΩ P-FETs are asserted active LOW, meaning that the P-FET will conduct when its gate is driven low. Likewise, when the gate is driven HIGH, the P-FET will not conduct.

Figure 2. Timing Diagram

In order to prevent shoot-through, we inserted some timing protections in the GreenPAK design to ensure that both FETs will never be on at the same time . The technique used to prevent shoot-through is discussed further in the GreenPAK Design section below.

GreenPAK Design

Figure 3. GreenPAK Design

As you can see in Figure 3, Pin17 (VCAP) of the GreenPAK is used to monitor the voltage at the top of C2. ACMP0 is used with the settings shown in Figure 4. The ACMP’s threshold is set to 1v and its gain to x0.5, resulting in a real VIH threshold of 2.0v. A hysteresis of 50mV (along with the x0.5 gain) gives us a VIL threshold of 1.9v. So the ACMP will output HIGH when the voltage at Pin17 raises above 2.0v, and will stay HIGH until the voltage drops below 1.9v. 3-bit LUT4 is used as a short buffer to give ACMP0 a little time to settle before affecting either of the switches.

The two Edge Detectors and the two delay blocks are used to create the timing protections that prevent shoot-through. If the ACMP goes LOW, falling edge detector EDGE DET0 will output a short active HIGH pulse, which will be inverted by 2-bit LUT0, whose output is connected to the nRESET of DFF4. Since DFF4’s output polarity is inverted, it will output HIGH, which will turn off FET1. 120µs later, DLY6 will clock DFF3, thus turning on FET0.

At this point FET0 is ON and FET1 is OFF, so C2 is connected to VDD through FET0. It will charge up until ACMP0 registers that the voltage at the top of C2 has reached 2.0v. At this point, the rising edge detector EDGE DET1 and inverter 2-bit LUT1 are used to reset DFF3, and 120µs later DLY5 is used to clock DFF4. At this point FET0 is OFF and FET1 is ON, so C2 is connected to the LOAD through FET1 and will begin to discharge.

A user can retrieve the Coulomb Counter information in a few different ways:

• Look at the raw output, aka the frequency of the FET switching by watching Pin24 and Pin25.
• Receive a notification on Pin4 when CNT0 goes HIGH after a certain amount of switching has occurred.
• Use an I2C read command to retrieve the count in CNT0 dynamically, then reset the counter with a pair of I2C write commands. In the commands below, ‘[‘ indicates a START bit, and ‘]’ indicates a STOP bit.
• Read CNT0 MSBs: [0x00 0xEC [0x01 r
• Read CNT0 LSBs: [0x00 0xEB [0x01 r
• Reset CNT0: [0x00 0xF4 0x01] [0x00 0xF4 0x00]

Results

Figure 6 shows operation when the Load Current is 50µA. The oscilloscope channels are probing:

• Channel 1 (Yellow) – Gate of FET0
• Channel 2 (Blue) – Gate of FET1
• Channel 3 (Pink) – Voltage at the top of C2

Figure 7 shows the Gate signals from a zoomed in perspective – you can see that both FETs will not be enabled at the same time due to the non-overlapping circuitry we built into the GreenPAK design.

We measured the raw output switching frequency with various load currents, from 1µA to 50mA. As you can see from Figure 8, the relationship between the Load Current and the Switching Frequency is reasonably linear from 1µA to 20mA. In Figure 9, however, the relationship becomes less linear around 30-40mA. This is because the switching capacitor (C2) is being discharged so quickly that the power switches are no longer able to switch fast enough to keep up with demand.

Depending on the application, you may need to change the size of the capacitors used in the coulomb counter. If you need to track load currents of >20mA for instance, you would need larger capacitors for C2 and C3.

Table 1. I_LOAD vs Switching Frequency

Conclusion

In this app note we created a coulomb counter using a Silego GreenPAK SLG46517V that allows a user to monitor how much current their load circuitry draws. This coulomb counter behaves like a buck converter and regulates its output rail to 1.9-2.0v. With a 1µF switching capacitor (C2) and a 10µF decoupling capacitor (C3) on the load, this design’s output frequency has a fairly linear relationship with the load current, from 1µA to 20mA. If the user needs to monitor a load current higher than 20mA, they can increase the size of both the switching capacitor and the decoupling capacitor.

About the Author

Name: David Riedell

Background: David attained a BS in Computer Engineering from North Carolina State University. He is currently working with CMICs as an applications engineer at Silego Technology.

Contact: appnotes@silego.com