Existing Technology

This duty cycle configuration is currently achieved by using multiple connected devices, such as TI’s TPS61291, TPL5111, or CD4541, as well as associated passive components.

Figure 1. Example of a setup using purpose-made discrete devices to achieve power duty cycling

Silego Technology

The ability to modify the delay period between each cycle is advantageous, as it allows the application to modify the duty cycle for the best battery life by taking into account external factors (e.g. time of day, season, temperature, traffic volumes, etc.).

Figure 2. Example of Silego SLG46116V/SLG46117V based replacement, with a smaller footprint, fewer supporting passive components, and optionally enhanced duty cycle control with MCU modifiable interval

Figure 3. Block diagram of SLG internals (inside dotted line)

Implementation

The circuit is implemented using a SPI interface to set and change the time interval. When the external circuit is not powered, it is expected that the input pins would have high impedance or be held at logic LOW.

It is left to the user to implement a hardwired version if the time interval is constant or a parallel interface version if preferred.

Figure 4. Power duty cycle controller GreenPAK™ schematic

Counter blocks CNT0-CNT3 are configured as rising edge delays with various delay times. When the DLY_IN signal to each of the blocks goes HIGH for 100ms, 500ms, 1s, and 5s respectively, the blocks will output HIGH. The select pins of each of the 3 muxes are connected to DFF0 and DFF1, whose operation is described below. The selected MUX output will go HIGH at the end of the delay period and will drive the P-FET Power Switch on, connecting Power in to Power out. Once the MCU or other external hardware has determined that the required operations have been completed, the Sleep pin is driven HIGH, and after inversion through 2-L3, this signal resets DFF2 and the CNT/DLYs, resulting in DFF 2's output going LOW. This turns off the P-FET switch. At this time, the Sleep input should return to LOW or voltage free (the pin is internally pulled down) as the external circuit loses power.

To program the selection of the time period, with SPIEN driven HIGH, the logic level at pin D is clocked into DFF0 on the rising edge of CLK. Data already in DFF0 is clocked into DFF1. This sets up SEL0 and SEL1. As most MCUs have a minimum SPI data frame size larger than two bits, it should be noted that only the last two clocked bits are retained (so you should only set up the last two bits transmitted when implementing the SPI interface on the MCU). SPIEN should remain LOW or at high impedance (it is internally pulled LOW) when the SPI interface is not in use.

At first power up, DFF0 and DFF1 have default values of 0, which results in the shortest delay. Additionally, DFF2 has an initial polarity of HIGH, turning on the P-FET switch. At this time, the desired delay should be programmed. Afterwards, the programmed delay interval will be retained until a power loss to the Silego chip, or until the delay is reprogrammed.

The shown delay times can be modified to any allowable delay period by reconfiguring the Counter data (and/or Clock) for each CNT/DLY module and/or the OSC module.

Figure 5. Predefined delays can be changed by modifying the configuration

If the SPIEN function is not required, the 2-L2 gate can be removed, and the CLK can drive DFF0 and DFF1 directly. In this case, CLK should be held LOW or be at high impedance when not clocking data.

Table 1. Programmed bits, intermediate selections, and results

The SPI input has been tested at a clock speed of 8MHz, and works in SPI mode 0, 1, and 3.

Waveforms

Figure 6. Demonstration of changing delay from 100 ms to 1 s

Figure 7. Showing the sleep pulse (yellow) to end the cycle

Arduino Code

These tests and demonstrations were completed using the following Arduino test code:

Table 2. SLG46117V Arduino interconnections used in demonstration

Conclusion

In this app note we created a variable-length power duty cycle controller to help prolong the battery life of a system. It allows a microcontroller to decide how long to power down and when to wake back up. Since GreenPAK’s quiescent current is less than a typical microcontroller’s quiescent current, using the GreenPAK as a dedicated wake/sleep device will help the system operate for a longer period of time before the battery runs out.

About the Author

Name: Craig Wilkins

Background: Craig has been developing electronic based industrial products since 1980 and started programming in 1985. He has worked on products across many industries and categories, including AC motor control, marine, automotive test equipment, agricultural processing, electrostatic powder coating, footwear manufacturing machinery, general machinery, and various hydraulic and pneumatic systems. His programming exploits range from embedded assembly, C/C++ firmware, accounting and inventory control software, computer vision, CAD based programs, and others. He has designed plastic injection moulds and other products on CNC maching centers using CAD/CAM/CAE.

Contact: appnotes@silego.com