
Min-placement step: Set up placement.
There are 14 instances. After combining instances in chains, there are 12 instances to place.
There are 6 nets in the design, 0 of which have fanout larger than 49. Average fanout is 1.50.
There is 1 clock in the design.
Resource usages:
 Type=L: Capacity=280 Utilized=1 NumInst=1. [ChainLen=1]=1
 Type=M: Capacity=80 Utilized=0 NumInst=0.
 Type=IOB: Capacity=308 Utilized=11 NumInst=11.
 Type=ZIOB: Capacity=56 Utilized=0 NumInst=0.
Min-placement step: Global placement and legalization.
Adjusting placement to reduce overflow for RBB-L and M: (iter=0)
Adjusting placement to reduce overflow for RBB-L and M: (iter=0)
Legalizing non-chains of RBB-L: .(1,0|0,0)
Improving the placement of 1 instances for resource type(s) of RBB-L RBB-M: ...........................................................................................................
pClockAap: #TIlE=[1,2]
#Parts=1
	Part[0]: [0,0] W1 W0 E1 E0 S1 S0 [0,1] W1 W0 E1 E0 N1 N0
BuildRelationalGroups: PrProperty=<none>
#Group=1
	Group: #Clocks=1 DIRBM=NONE
		Clock ID=0 #LoadParts=1 DIRBM=NONE
			LoadPart[0]: DIRBM=NONE [0,1] [0,0] COL=0 ROW=0 1 
#Unassigned(align)=1. Initial filtering of signle-choices.
#Unassigned(align)=1. Start working on aligned-choices.
	GROUP(CLK=0):
		PER_TILE_PORT: {EW}=P ASSIGN([0,1]E1=0) ASSIGN([0,0]E1=0) OK
#Unassigned(noalign)=0. Work on the remainder with any-choices.
#AssignedSingle=0 #AssignedAligned=1 #AssignedAny=0 #Unassigned=0
=================================================================================================================
#Parts=1
	Part[0]: [0,0] W1 W0 E1=0 E0 S1 S0 [0,1] W1 W0 E1=0 E0 N1 N0
#Group=1
	Group: #Clocks=1 DIRBM=EW
		Clock ID=0 #LoadParts=1 DIRBM=EW
			LoadPart[0]: DIRBM=EW [0,1] [0,0] COL=0 ROW=0 1  ASSIGNED_PORT= [0,1]E1=0 [0,0]E1=0
pClockAap: SUCCESSFUL.
Min-placement step ends: Global placement and legalization. Runtime: 0:0:45 (CPU time), 0:0:45 (real time); peak memory: 1304MB.


There are 14 instances. After combining instances in chains, there are 12 instances to place.
There are 6 nets in the design. Average fanout is 1.50.
There is 1 clock in the design.
Resource usages:
 Type=L: Capacity=280 Utilized=1 NumInst=1. [ChainLen=1]=1
 Type=M: Capacity=80 Utilized=0 NumInst=0.
 Type=IOB: Capacity=308 Utilized=11 NumInst=11.
 Type=ZIOB: Capacity=56 Utilized=0 NumInst=0.
Min-placement step: Replication (mode=1).
pClockAap: #TIlE=[1,2]
#Parts=1
	Part[0]: [0,0] W1 W0 E1 E0 S1 S0 [0,1] W1 W0 E1 E0 N1 N0
BuildRelationalGroups: PrProperty=<none>
#Group=1
	Group: #Clocks=1 DIRBM=NONE
		Clock ID=0 #LoadParts=1 DIRBM=NONE
			LoadPart[0]: DIRBM=NONE [0,1] [0,0] COL=0 ROW=0 1 
#Unassigned(align)=1. Initial filtering of signle-choices.
#Unassigned(align)=1. Start working on aligned-choices.
	GROUP(CLK=0):
		PER_TILE_PORT: {EW}=P ASSIGN([0,1]E1=0) ASSIGN([0,0]E1=0) OK
#Unassigned(noalign)=0. Work on the remainder with any-choices.
#AssignedSingle=0 #AssignedAligned=1 #AssignedAny=0 #Unassigned=0
=================================================================================================================
#Parts=1
	Part[0]: [0,0] W1 W0 E1=0 E0 S1 S0 [0,1] W1 W0 E1=0 E0 N1 N0
#Group=1
	Group: #Clocks=1 DIRBM=EW
		Clock ID=0 #LoadParts=1 DIRBM=EW
			LoadPart[0]: DIRBM=EW [0,1] [0,0] COL=0 ROW=0 1  ASSIGNED_PORT= [0,1]E1=0 [0,0]E1=0
pClockAap: SUCCESSFUL.
Min-placement step ends: Replication (mode=1). Runtime: 0:0:25 (CPU time), 0:0:25 (real time); peak memory: 1337MB.


There are 14 instances. After combining instances in chains, there are 12 instances to place.
There are 6 nets in the design. Average fanout is 1.50.
There is 1 clock in the design.
Resource usages:
 Type=L: Capacity=280 Utilized=1 NumInst=1. [ChainLen=1]=1
 Type=M: Capacity=80 Utilized=0 NumInst=0.
 Type=IOB: Capacity=308 Utilized=11 NumInst=11.
 Type=ZIOB: Capacity=56 Utilized=0 NumInst=0.
Min-placement step: Detaild placement (mode=2).
Long connection estimation: .....
Short connection estimation: ......
pClockAap: #TIlE=[1,2]
#Parts=1
	Part[0]: [0,0] W1 W0 E1 E0 S1 S0 [0,1] W1 W0 E1 E0 N1 N0
BuildRelationalGroups: PrProperty=<none>
#Group=1
	Group: #Clocks=1 DIRBM=NONE
		Clock ID=0 #LoadParts=1 DIRBM=NONE
			LoadPart[0]: DIRBM=NONE [0,1] [0,0] COL=0 ROW=0 1 
#Unassigned(align)=1. Initial filtering of signle-choices.
#Unassigned(align)=1. Start working on aligned-choices.
	GROUP(CLK=0):
		PER_TILE_PORT: {EW}=P ASSIGN([0,1]E1=0) ASSIGN([0,0]E1=0) OK
#Unassigned(noalign)=0. Work on the remainder with any-choices.
#AssignedSingle=0 #AssignedAligned=1 #AssignedAny=0 #Unassigned=0
=================================================================================================================
#Parts=1
	Part[0]: [0,0] W1 W0 E1=0 E0 S1 S0 [0,1] W1 W0 E1=0 E0 N1 N0
#Group=1
	Group: #Clocks=1 DIRBM=EW
		Clock ID=0 #LoadParts=1 DIRBM=EW
			LoadPart[0]: DIRBM=EW [0,1] [0,0] COL=0 ROW=0 1  ASSIGNED_PORT= [0,1]E1=0 [0,0]E1=0
pClockAap: SUCCESSFUL.

Placement timing:
         Clock        Group  Achievable Frequency(MHz)
--------------  -----------  -------------------------


Min-placement step ends: Detaild placement (mode=2). Runtime: 0:1:5 (CPU time), 0:1:5 (real time); peak memory: 1420MB.


There are 14 instances. After combining instances in chains, there are 12 instances to place.
There are 6 nets in the design. Average fanout is 1.50.
There is 1 clock in the design.
Resource usages:
 Type=L: Capacity=280 Utilized=1 NumInst=1. [ChainLen=1]=1
 Type=M: Capacity=80 Utilized=0 NumInst=0.
 Type=IOB: Capacity=308 Utilized=11 NumInst=11.
 Type=ZIOB: Capacity=56 Utilized=0 NumInst=0.
Min-placement step: Delay and congestion estimation (fastest_delay=0 gentable=0 mode=1).
Long connection estimation: .....
Short connection estimation: ......
Long connection estimation: (50)w---------(60)----------(70)----------(80)----------(90)----------(100)-
Long connection estimation: (50)pxxxxxxxxx(60)xxxxxxxxxx(70)xxxxxxxxxx(80)xxxxxxxxxx(90)xxxxxxxxxx(100)x
pClockAap: #TIlE=[1,2]
#Parts=1
	Part[0]: [0,0] W1 W0 E1 E0 S1 S0 [0,1] W1 W0 E1 E0 N1 N0
BuildRelationalGroups: PrProperty=<none>
#Group=1
	Group: #Clocks=1 DIRBM=NONE
		Clock ID=0 #LoadParts=1 DIRBM=NONE
			LoadPart[0]: DIRBM=NONE [0,1] [0,0] COL=0 ROW=0 1 
#Unassigned(align)=1. Initial filtering of signle-choices.
#Unassigned(align)=1. Start working on aligned-choices.
	GROUP(CLK=0):
		PER_TILE_PORT: {EW}=P ASSIGN([0,1]E1=0) ASSIGN([0,0]E1=0) OK
#Unassigned(noalign)=0. Work on the remainder with any-choices.
#AssignedSingle=0 #AssignedAligned=1 #AssignedAny=0 #Unassigned=0
=================================================================================================================
#Parts=1
	Part[0]: [0,0] W1 W0 E1=0 E0 S1 S0 [0,1] W1 W0 E1=0 E0 N1 N0
#Group=1
	Group: #Clocks=1 DIRBM=EW
		Clock ID=0 #LoadParts=1 DIRBM=EW
			LoadPart[0]: DIRBM=EW [0,1] [0,0] COL=0 ROW=0 1  ASSIGNED_PORT= [0,1]E1=0 [0,0]E1=0
pClockAap: SUCCESSFUL.

Placement timing:
         Clock        Group  Achievable Frequency(MHz)
--------------  -----------  -------------------------


Min-placement step ends: Delay and congestion estimation (fastest_delay=0 gentable=0 mode=1). Runtime: 0:1:10 (CPU time), 0:1:10 (real time); peak memory: 1379MB.


