<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<azone>
    <rzone name="R7KA8D2KFLCAC.rzone"/>
    <partition>
        <memory parent="RAM_NS" name="RAM_NS_CPU0_N" size="0x0" offset="0x1D4000" security="n" Pname="CPU0"/>
        <memory parent="RAM_NS" name="RAM_NS_CPU1_N" size="0x0" offset="0x1D4000" security="n" Pname="CPU1"/>
        <memory parent="RAM" name="RAM_CPU0_S" size="0x145000" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="RAM" name="RAM_CPU0_C" size="0x0" offset="0x145000" security="c" Pname="CPU0"/>
        <memory parent="RAM" name="SHARED_MEM" size="0x8000" offset="0x145000" security="s" Pname="CPU0" info="@user"/>
        <memory parent="RAM" name="RAM_CPU1_S" size="0x87000" offset="0x14D000" security="s" Pname="CPU1"/>
        <memory parent="RAM" name="RAM_CPU1_C" size="0x0" offset="0x1D4000" security="c" Pname="CPU1"/>
        <memory parent="FLASH_NS" name="FLASH_NS_CPU0_N" size="0x0" offset="0x100000" security="n" Pname="CPU0"/>
        <memory parent="FLASH_NS" name="FLASH_NS_CPU1_N" size="0x0" offset="0x100000" security="n" Pname="CPU1"/>
        <memory parent="FLASH" name="FLASH_CPU0_S" size="0xF0000" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="FLASH" name="FLASH_CPU0_C" size="0x0" offset="0xF0000" security="c" Pname="CPU0"/>
        <memory parent="FLASH" name="FLASH_CPU1_S" size="0x10000" offset="0xF0000" security="s" Pname="CPU1"/>
        <memory parent="FLASH" name="FLASH_CPU1_C" size="0x0" offset="0x100000" security="c" Pname="CPU1"/>
        <memory parent="DATA_FLASH_NS" name="DATA_FLASH_NS_CPU0_N" size="0x0" offset="0x0" security="n" Pname="CPU0"/>
        <memory parent="DATA_FLASH_NS" name="DATA_FLASH_NS_CPU1_N" size="0x0" offset="0x0" security="n" Pname="CPU1"/>
        <memory parent="DATA_FLASH" name="DATA_FLASH_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="DATA_FLASH" name="DATA_FLASH_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="SDRAM" name="SDRAM_CPU0_S" size="0x2000000" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="SDRAM" name="SDRAM_CPU1_S" size="0x0" offset="0x2000000" security="s" Pname="CPU1"/>
        <memory parent="SDRAM" name="SDRAM_CPU0_N" size="0x0" offset="0x8000000" security="n" Pname="CPU0"/>
        <memory parent="SDRAM" name="SDRAM_CPU1_N" size="0x0" offset="0x8000000" security="n" Pname="CPU1"/>
        <memory parent="OSPI0_CS0" name="OSPI0_CS0_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OSPI0_CS0" name="OSPI0_CS0_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OSPI0_CS0" name="OSPI0_CS0_CPU0_N" size="0x0" offset="0x10000000" security="n" Pname="CPU0"/>
        <memory parent="OSPI0_CS0" name="OSPI0_CS0_CPU1_N" size="0x0" offset="0x10000000" security="n" Pname="CPU1"/>
        <memory parent="OSPI0_CS1" name="OSPI0_CS1_CPU0_S" size="0x4000000" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OSPI0_CS1" name="OSPI0_CS1_CPU1_S" size="0x0" offset="0x4000000" security="s" Pname="CPU1"/>
        <memory parent="OSPI0_CS1" name="OSPI0_CS1_CPU0_N" size="0x0" offset="0x10000000" security="n" Pname="CPU0"/>
        <memory parent="OSPI0_CS1" name="OSPI0_CS1_CPU1_N" size="0x0" offset="0x10000000" security="n" Pname="CPU1"/>
        <memory parent="OSPI1_CS0" name="OSPI1_CS0_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OSPI1_CS0" name="OSPI1_CS0_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OSPI1_CS0" name="OSPI1_CS0_CPU0_N" size="0x0" offset="0x8000000" security="n" Pname="CPU0"/>
        <memory parent="OSPI1_CS0" name="OSPI1_CS0_CPU1_N" size="0x0" offset="0x8000000" security="n" Pname="CPU1"/>
        <memory parent="OSPI1_CS1" name="OSPI1_CS1_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OSPI1_CS1" name="OSPI1_CS1_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OSPI1_CS1" name="OSPI1_CS1_CPU0_N" size="0x0" offset="0x8000000" security="n" Pname="CPU0"/>
        <memory parent="OSPI1_CS1" name="OSPI1_CS1_CPU1_N" size="0x0" offset="0x8000000" security="n" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS0" name="OPTION_SETTING_OFS0_CPU0_S" size="0x4" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS0" name="OPTION_SETTING_OFS0_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS2" name="OPTION_SETTING_OFS2_CPU0_S" size="0x4" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS2" name="OPTION_SETTING_OFS2_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_SAS" name="OPTION_SETTING_SAS_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_SAS" name="OPTION_SETTING_SAS_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS1" name="OPTION_SETTING_OFS1_CPU0_N" size="0x0" offset="0x0" security="n" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS1" name="OPTION_SETTING_OFS1_CPU1_N" size="0x0" offset="0x0" security="n" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS1_SEC" name="OPTION_SETTING_OFS1_SEC_CPU0_S" size="0x4" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS1_SEC" name="OPTION_SETTING_OFS1_SEC_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS1_SEL" name="OPTION_SETTING_OFS1_SEL_CPU0_S" size="0x4" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS1_SEL" name="OPTION_SETTING_OFS1_SEL_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS3" name="OPTION_SETTING_OFS3_CPU0_N" size="0x0" offset="0x0" security="n" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS3" name="OPTION_SETTING_OFS3_CPU1_N" size="0x0" offset="0x0" security="n" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS3_SEC" name="OPTION_SETTING_OFS3_SEC_CPU0_S" size="0x4" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS3_SEC" name="OPTION_SETTING_OFS3_SEC_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OFS3_SEL" name="OPTION_SETTING_OFS3_SEL_CPU0_S" size="0x4" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS3_SEL" name="OPTION_SETTING_OFS3_SEL_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_BPS" name="OPTION_SETTING_BPS_CPU0_N" size="0x0" offset="0x0" security="n" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_BPS" name="OPTION_SETTING_BPS_CPU1_N" size="0x0" offset="0x0" security="n" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_BPS_SEC" name="OPTION_SETTING_BPS_SEC_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_BPS_SEC" name="OPTION_SETTING_BPS_SEC_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_FSBLCTRL0" name="OPTION_SETTING_OTP_FSBLCTRL0_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_FSBLCTRL0" name="OPTION_SETTING_OTP_FSBLCTRL0_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_FSBLCTRL1" name="OPTION_SETTING_OTP_FSBLCTRL1_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_FSBLCTRL1" name="OPTION_SETTING_OTP_FSBLCTRL1_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_FSBLCTRL2" name="OPTION_SETTING_OTP_FSBLCTRL2_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_FSBLCTRL2" name="OPTION_SETTING_OTP_FSBLCTRL2_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SAMR" name="OPTION_SETTING_OTP_SAMR_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SAMR" name="OPTION_SETTING_OTP_SAMR_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC00" name="OPTION_SETTING_OTP_SACC00_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC00" name="OPTION_SETTING_OTP_SACC00_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC10" name="OPTION_SETTING_OTP_SACC10_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC10" name="OPTION_SETTING_OTP_SACC10_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC01" name="OPTION_SETTING_OTP_SACC01_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC01" name="OPTION_SETTING_OTP_SACC01_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC11" name="OPTION_SETTING_OTP_SACC11_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC11" name="OPTION_SETTING_OTP_SACC11_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC02" name="OPTION_SETTING_OTP_SACC02_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC02" name="OPTION_SETTING_OTP_SACC02_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC12" name="OPTION_SETTING_OTP_SACC12_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC12" name="OPTION_SETTING_OTP_SACC12_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC03" name="OPTION_SETTING_OTP_SACC03_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC03" name="OPTION_SETTING_OTP_SACC03_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_SACC13" name="OPTION_SETTING_OTP_SACC13_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_SACC13" name="OPTION_SETTING_OTP_SACC13_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_PBPS_SEC" name="OPTION_SETTING_OTP_PBPS_SEC_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_PBPS_SEC" name="OPTION_SETTING_OTP_PBPS_SEC_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_PBPS" name="OPTION_SETTING_OTP_PBPS_CPU0_N" size="0x0" offset="0x0" security="n" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_PBPS" name="OPTION_SETTING_OTP_PBPS_CPU1_N" size="0x0" offset="0x0" security="n" Pname="CPU1"/>
        <memory parent="OPTION_SETTING_OTP_ZHUK" name="OPTION_SETTING_OTP_ZHUK_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_ZHUK" name="OPTION_SETTING_OTP_ZHUK_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="ITCM_NS" name="ITCM_NS_CPU0_N" size="0x0" offset="0x20000" security="n" Pname="CPU0"/>
        <memory parent="ITCM" name="ITCM_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="DTCM_NS" name="DTCM_NS_CPU0_N" size="0x0" offset="0x20000" security="n" Pname="CPU0"/>
        <memory parent="DTCM" name="DTCM_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="CTCM_NS" name="CTCM_NS_CPU1_N" size="0x0" offset="0x10000" security="n" Pname="CPU1"/>
        <memory parent="CTCM" name="CTCM_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <memory parent="STCM_NS" name="STCM_NS_CPU1_N" size="0x0" offset="0x10000" security="n" Pname="CPU1"/>
        <memory parent="STCM" name="STCM_CPU1_S" size="0x0" offset="0x0" security="s" Pname="CPU1"/>
        <peripheral name="PORT1.CPU0" group="PORT">
            <slot name="P100.CPU0" secure="true"/>
            <slot name="P101.CPU0" secure="true"/>
            <slot name="P102.CPU0" secure="true"/>
            <slot name="P103.CPU0" secure="true"/>
            <slot name="P104.CPU0" secure="true"/>
            <slot name="P105.CPU0" secure="true"/>
            <slot name="P106.CPU0" secure="true"/>
            <slot name="P108.CPU0" secure="true"/>
            <slot name="P112.CPU0" secure="true"/>
            <slot name="P113.CPU0" secure="true"/>
            <slot name="P114.CPU0" secure="true"/>
            <slot name="P115.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORT2.CPU0" group="PORT">
            <slot name="P208.CPU0" secure="true"/>
            <slot name="P209.CPU0" secure="true"/>
            <slot name="P210.CPU0" secure="true"/>
            <slot name="P211.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORT3.CPU0" group="PORT">
            <slot name="P300.CPU0" secure="true"/>
            <slot name="P301.CPU0" secure="true"/>
            <slot name="P302.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORT4.CPU0" group="PORT">
            <slot name="P411.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORT5.CPU0" group="PORT">
            <slot name="P503.CPU0" secure="true"/>
            <slot name="P504.CPU0" secure="true"/>
            <slot name="P505.CPU0" secure="true"/>
            <slot name="P506.CPU0" secure="true"/>
            <slot name="P507.CPU0" secure="true"/>
            <slot name="P508.CPU0" secure="true"/>
            <slot name="P509.CPU0" secure="true"/>
            <slot name="P510.CPU0" secure="true"/>
            <slot name="P514.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORT6.CPU0" group="PORT">
            <slot name="P600.CPU0" secure="true"/>
            <slot name="P601.CPU0" secure="true"/>
            <slot name="P607.CPU0" secure="true"/>
            <slot name="P608.CPU0" secure="true"/>
            <slot name="P609.CPU0" secure="true"/>
            <slot name="P610.CPU0" secure="true"/>
            <slot name="P611.CPU0" secure="true"/>
            <slot name="P612.CPU0" secure="true"/>
            <slot name="P613.CPU0" secure="true"/>
            <slot name="P614.CPU0" secure="true"/>
            <slot name="P615.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORT8.CPU0" group="PORT">
            <slot name="P800.CPU0" secure="true"/>
            <slot name="P801.CPU0" secure="true"/>
            <slot name="P802.CPU0" secure="true"/>
            <slot name="P803.CPU0" secure="true"/>
            <slot name="P804.CPU0" secure="true"/>
            <slot name="P808.CPU0" secure="true"/>
            <slot name="P813.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORTA.CPU0" group="PORT">
            <slot name="PA00.CPU0" secure="true"/>
            <slot name="PA01.CPU0" secure="true"/>
            <slot name="PA02.CPU0" secure="true"/>
            <slot name="PA03.CPU0" secure="true"/>
            <slot name="PA04.CPU0" secure="true"/>
            <slot name="PA05.CPU0" secure="true"/>
            <slot name="PA06.CPU0" secure="true"/>
            <slot name="PA08.CPU0" secure="true"/>
            <slot name="PA09.CPU0" secure="true"/>
            <slot name="PA10.CPU0" secure="true"/>
            <slot name="PA11.CPU0" secure="true"/>
            <slot name="PA12.CPU0" secure="true"/>
            <slot name="PA13.CPU0" secure="true"/>
            <slot name="PA14.CPU0" secure="true"/>
            <slot name="PA15.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORTC.CPU0" group="PORT">
            <slot name="PC00.CPU0" secure="true"/>
            <slot name="PC01.CPU0" secure="true"/>
            <slot name="PC02.CPU0" secure="true"/>
            <slot name="PC03.CPU0" secure="true"/>
            <slot name="PC04.CPU0" secure="true"/>
            <slot name="PC05.CPU0" secure="true"/>
            <slot name="PC06.CPU0" secure="true"/>
            <slot name="PC07.CPU0" secure="true"/>
            <slot name="PC08.CPU0" secure="true"/>
            <slot name="PC09.CPU0" secure="true"/>
            <slot name="PC10.CPU0" secure="true"/>
            <slot name="PC11.CPU0" secure="true"/>
            <slot name="PC12.CPU0" secure="true"/>
            <slot name="PC13.CPU0" secure="true"/>
            <slot name="PC14.CPU0" secure="true"/>
            <slot name="PC15.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="PORTD.CPU0" group="PORT">
            <slot name="PD00.CPU0" secure="true"/>
        </peripheral>
        <peripheral name="DMA_DMAC0.CPU0" group="DMA_DMAC" security="s"/>
        <peripheral name="GLCDC.CPU0" security="s"/>
        <peripheral name="GPT13.CPU0" group="GPT" security="s"/>
        <peripheral name="ICU.CPU0">
            <slot name="IRQ0.CPU0" secure="true"/>
            <slot name="IRQ1.CPU0" secure="true"/>
            <slot name="IRQ2.CPU0" secure="true"/>
            <slot name="IRQ3.CPU0" secure="true"/>
            <slot name="IRQ4.CPU0" secure="true"/>
            <slot name="IRQ5.CPU0" secure="true"/>
            <slot name="IRQ6.CPU0" secure="true"/>
            <slot name="IRQ7.CPU0" secure="true"/>
            <slot name="IRQ8.CPU0" secure="true"/>
        </peripheral>
        <memory parent="OPTION_SETTING_OFS1" name="OPTION_SETTING_OFS1_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OFS3" name="OPTION_SETTING_OFS3_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_BPS" name="OPTION_SETTING_BPS_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <memory parent="OPTION_SETTING_OTP_PBPS" name="OPTION_SETTING_OTP_PBPS_CPU0_S" size="0x0" offset="0x0" security="s" Pname="CPU0"/>
        <peripheral name="PORT0.CPU1" group="PORT">
            <slot name="P000.CPU1" secure="true"/>
            <slot name="P001.CPU1" secure="true"/>
            <slot name="P002.CPU1" secure="true"/>
            <slot name="P003.CPU1" secure="true"/>
            <slot name="P004.CPU1" secure="true"/>
            <slot name="P005.CPU1" secure="true"/>
            <slot name="P006.CPU1" secure="true"/>
            <slot name="P007.CPU1" secure="true"/>
            <slot name="P008.CPU1" secure="true"/>
            <slot name="P009.CPU1" secure="true"/>
            <slot name="P010.CPU1" secure="true"/>
            <slot name="P011.CPU1" secure="true"/>
            <slot name="P012.CPU1" secure="true"/>
            <slot name="P013.CPU1" secure="true"/>
            <slot name="P014.CPU1" secure="true"/>
            <slot name="P015.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT1.CPU1" group="PORT">
            <slot name="P107.CPU1" secure="true"/>
            <slot name="P109.CPU1" secure="true"/>
            <slot name="P110.CPU1" secure="true"/>
            <slot name="P111.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT2.CPU1" group="PORT">
            <slot name="P200.CPU1" secure="true"/>
            <slot name="P201.CPU1" secure="true"/>
            <slot name="P206.CPU1" secure="true"/>
            <slot name="P207.CPU1" secure="true"/>
            <slot name="P212.CPU1" secure="true"/>
            <slot name="P213.CPU1" secure="true"/>
            <slot name="P214.CPU1" secure="true"/>
            <slot name="P215.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT3.CPU1" group="PORT">
            <slot name="P303.CPU1" secure="true"/>
            <slot name="P304.CPU1" secure="true"/>
            <slot name="P305.CPU1" secure="true"/>
            <slot name="P306.CPU1" secure="true"/>
            <slot name="P307.CPU1" secure="true"/>
            <slot name="P309.CPU1" secure="true"/>
            <slot name="P310.CPU1" secure="true"/>
            <slot name="P311.CPU1" secure="true"/>
            <slot name="P312.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT4.CPU1" group="PORT">
            <slot name="P400.CPU1" secure="true"/>
            <slot name="P401.CPU1" secure="true"/>
            <slot name="P402.CPU1" secure="true"/>
            <slot name="P405.CPU1" secure="true"/>
            <slot name="P406.CPU1" secure="true"/>
            <slot name="P407.CPU1" secure="true"/>
            <slot name="P408.CPU1" secure="true"/>
            <slot name="P409.CPU1" secure="true"/>
            <slot name="P410.CPU1" secure="true"/>
            <slot name="P412.CPU1" secure="true"/>
            <slot name="P413.CPU1" secure="true"/>
            <slot name="P414.CPU1" secure="true"/>
            <slot name="P415.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT5.CPU1" group="PORT">
            <slot name="P500.CPU1" secure="true"/>
            <slot name="P501.CPU1" secure="true"/>
            <slot name="P511.CPU1" secure="true"/>
            <slot name="P512.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT6.CPU1" group="PORT">
            <slot name="P606.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT7.CPU1" group="PORT">
            <slot name="P700.CPU1" secure="true"/>
            <slot name="P701.CPU1" secure="true"/>
            <slot name="P702.CPU1" secure="true"/>
            <slot name="P703.CPU1" secure="true"/>
            <slot name="P704.CPU1" secure="true"/>
            <slot name="P705.CPU1" secure="true"/>
            <slot name="P706.CPU1" secure="true"/>
            <slot name="P707.CPU1" secure="true"/>
            <slot name="P708.CPU1" secure="true"/>
            <slot name="P709.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT8.CPU1" group="PORT">
            <slot name="P810.CPU1" secure="true"/>
            <slot name="P811.CPU1" secure="true"/>
            <slot name="P814.CPU1" secure="true"/>
            <slot name="P815.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORT9.CPU1" group="PORT">
            <slot name="P902.CPU1" secure="true"/>
            <slot name="P905.CPU1" secure="true"/>
            <slot name="P906.CPU1" secure="true"/>
            <slot name="P907.CPU1" secure="true"/>
            <slot name="P908.CPU1" secure="true"/>
            <slot name="P909.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORTA.CPU1" group="PORT">
            <slot name="PA07.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORTB.CPU1" group="PORT">
            <slot name="PB02.CPU1" secure="true"/>
            <slot name="PB03.CPU1" secure="true"/>
            <slot name="PB04.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="PORTD.CPU1" group="PORT">
            <slot name="PD01.CPU1" secure="true"/>
            <slot name="PD02.CPU1" secure="true"/>
            <slot name="PD03.CPU1" secure="true"/>
            <slot name="PD04.CPU1" secure="true"/>
            <slot name="PD05.CPU1" secure="true"/>
            <slot name="PD07.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="ICU_EXT_IRQ.CPU1">
            <slot name="ICU_EXT_IRQ19.CPU1" secure="true"/>
        </peripheral>
        <peripheral name="IIC1.CPU1" group="IIC" security="s"/>
        <peripheral name="RTC.CPU1" security="s"/>
        <peripheral name="ICU.CPU1">
            <slot name="IRQ0.CPU1" secure="true"/>
            <slot name="IRQ1.CPU1" secure="true"/>
            <slot name="IRQ2.CPU1" secure="true"/>
            <slot name="IRQ3.CPU1" secure="true"/>
            <slot name="IRQ4.CPU1" secure="true"/>
            <slot name="IRQ5.CPU1" secure="true"/>
            <slot name="IRQ6.CPU1" secure="true"/>
            <slot name="IRQ7.CPU1" secure="true"/>
        </peripheral>
    </partition>
    <zones>
        <zone name="CPU0_S" Pname="CPU0" security="s">
            <assign memory="RAM_CPU0_S"/>
            <assign memory="RAM_CPU0_C"/>
            <assign memory="SHARED_MEM"/>
            <assign memory="FLASH_CPU0_S"/>
            <assign memory="FLASH_CPU0_C"/>
            <assign memory="DATA_FLASH_CPU0_S"/>
            <assign memory="SDRAM_CPU0_S"/>
            <assign memory="OSPI0_CS0_CPU0_S"/>
            <assign memory="OSPI0_CS1_CPU0_S"/>
            <assign memory="OSPI1_CS0_CPU0_S"/>
            <assign memory="OSPI1_CS1_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS0_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS2_CPU0_S"/>
            <assign memory="OPTION_SETTING_SAS_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS1_SEC_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS1_SEL_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS3_SEC_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS3_SEL_CPU0_S"/>
            <assign memory="OPTION_SETTING_BPS_SEC_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_FSBLCTRL0_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_FSBLCTRL1_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_FSBLCTRL2_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SAMR_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC00_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC10_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC01_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC11_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC02_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC12_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC03_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_SACC13_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_PBPS_SEC_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_ZHUK_CPU0_S"/>
            <assign memory="ITCM_CPU0_S"/>
            <assign memory="DTCM_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS1_CPU0_S"/>
            <assign memory="OPTION_SETTING_OFS3_CPU0_S"/>
            <assign memory="OPTION_SETTING_BPS_CPU0_S"/>
            <assign memory="OPTION_SETTING_OTP_PBPS_CPU0_S"/>
            <assign group="PORT" peripheral="PORT1.P100"/>
            <assign group="PORT" peripheral="PORT1.P101"/>
            <assign group="PORT" peripheral="PORT1.P102"/>
            <assign group="PORT" peripheral="PORT1.P103"/>
            <assign group="PORT" peripheral="PORT1.P104"/>
            <assign group="PORT" peripheral="PORT1.P105"/>
            <assign group="PORT" peripheral="PORT1.P106"/>
            <assign group="PORT" peripheral="PORT1.P108"/>
            <assign group="PORT" peripheral="PORT1.P112"/>
            <assign group="PORT" peripheral="PORT1.P113"/>
            <assign group="PORT" peripheral="PORT1.P114"/>
            <assign group="PORT" peripheral="PORT1.P115"/>
            <assign group="PORT" peripheral="PORT2.P208"/>
            <assign group="PORT" peripheral="PORT2.P209"/>
            <assign group="PORT" peripheral="PORT2.P210"/>
            <assign group="PORT" peripheral="PORT2.P211"/>
            <assign group="PORT" peripheral="PORT3.P300"/>
            <assign group="PORT" peripheral="PORT3.P301"/>
            <assign group="PORT" peripheral="PORT3.P302"/>
            <assign group="PORT" peripheral="PORT4.P411"/>
            <assign group="PORT" peripheral="PORT5.P503"/>
            <assign group="PORT" peripheral="PORT5.P504"/>
            <assign group="PORT" peripheral="PORT5.P505"/>
            <assign group="PORT" peripheral="PORT5.P506"/>
            <assign group="PORT" peripheral="PORT5.P507"/>
            <assign group="PORT" peripheral="PORT5.P508"/>
            <assign group="PORT" peripheral="PORT5.P509"/>
            <assign group="PORT" peripheral="PORT5.P510"/>
            <assign group="PORT" peripheral="PORT5.P514"/>
            <assign group="PORT" peripheral="PORT6.P600"/>
            <assign group="PORT" peripheral="PORT6.P601"/>
            <assign group="PORT" peripheral="PORT6.P607"/>
            <assign group="PORT" peripheral="PORT6.P608"/>
            <assign group="PORT" peripheral="PORT6.P609"/>
            <assign group="PORT" peripheral="PORT6.P610"/>
            <assign group="PORT" peripheral="PORT6.P611"/>
            <assign group="PORT" peripheral="PORT6.P612"/>
            <assign group="PORT" peripheral="PORT6.P613"/>
            <assign group="PORT" peripheral="PORT6.P614"/>
            <assign group="PORT" peripheral="PORT6.P615"/>
            <assign group="PORT" peripheral="PORT8.P800"/>
            <assign group="PORT" peripheral="PORT8.P801"/>
            <assign group="PORT" peripheral="PORT8.P802"/>
            <assign group="PORT" peripheral="PORT8.P803"/>
            <assign group="PORT" peripheral="PORT8.P804"/>
            <assign group="PORT" peripheral="PORT8.P808"/>
            <assign group="PORT" peripheral="PORT8.P813"/>
            <assign group="PORT" peripheral="PORTA.PA00"/>
            <assign group="PORT" peripheral="PORTA.PA01"/>
            <assign group="PORT" peripheral="PORTA.PA02"/>
            <assign group="PORT" peripheral="PORTA.PA03"/>
            <assign group="PORT" peripheral="PORTA.PA04"/>
            <assign group="PORT" peripheral="PORTA.PA05"/>
            <assign group="PORT" peripheral="PORTA.PA06"/>
            <assign group="PORT" peripheral="PORTA.PA08"/>
            <assign group="PORT" peripheral="PORTA.PA09"/>
            <assign group="PORT" peripheral="PORTA.PA10"/>
            <assign group="PORT" peripheral="PORTA.PA11"/>
            <assign group="PORT" peripheral="PORTA.PA12"/>
            <assign group="PORT" peripheral="PORTA.PA13"/>
            <assign group="PORT" peripheral="PORTA.PA14"/>
            <assign group="PORT" peripheral="PORTA.PA15"/>
            <assign group="PORT" peripheral="PORTC.PC00"/>
            <assign group="PORT" peripheral="PORTC.PC01"/>
            <assign group="PORT" peripheral="PORTC.PC02"/>
            <assign group="PORT" peripheral="PORTC.PC03"/>
            <assign group="PORT" peripheral="PORTC.PC04"/>
            <assign group="PORT" peripheral="PORTC.PC05"/>
            <assign group="PORT" peripheral="PORTC.PC06"/>
            <assign group="PORT" peripheral="PORTC.PC07"/>
            <assign group="PORT" peripheral="PORTC.PC08"/>
            <assign group="PORT" peripheral="PORTC.PC09"/>
            <assign group="PORT" peripheral="PORTC.PC10"/>
            <assign group="PORT" peripheral="PORTC.PC11"/>
            <assign group="PORT" peripheral="PORTC.PC12"/>
            <assign group="PORT" peripheral="PORTC.PC13"/>
            <assign group="PORT" peripheral="PORTC.PC14"/>
            <assign group="PORT" peripheral="PORTC.PC15"/>
            <assign group="PORT" peripheral="PORTD.PD00"/>
            <assign group="DMA_DMAC" peripheral="DMA_DMAC0"/>
            <assign peripheral="GLCDC"/>
            <assign group="GPT" peripheral="GPT13"/>
            <assign peripheral="ICU.IRQ0"/>
            <assign peripheral="ICU.IRQ1"/>
            <assign peripheral="ICU.IRQ2"/>
            <assign peripheral="ICU.IRQ3"/>
            <assign peripheral="ICU.IRQ4"/>
            <assign peripheral="ICU.IRQ5"/>
            <assign peripheral="ICU.IRQ6"/>
            <assign peripheral="ICU.IRQ7"/>
            <assign peripheral="ICU.IRQ8"/>
        </zone>
    </zones>
</azone>
