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*******************************************************************************/
/******************************************************************************
* System Name : RZ/A1H R7S72100 Example Program for GENMAI - JCU, PFV
* $FileName: readme_e.txt $
******************************************************************************/
/**********************************************************************************
*
* History     : Mar.20, 2014 : 0.90 : Supported OSPL's Async
*               Jun.24, 2014 : 1.00 : Supported multi compiler
*               Jul.24, 2014 : 1.01 : Explanation of sample in this file was adjusted
*               Sep. 3, 2014 : 1.01 : Examples were adjusted to be able to run the 
*                                     JCU recorder example after running PFV examples
*               Sep. 5, 2014 : 1.01 : Adjust the byte order in JCU recorder example
*               Feb.29, 2016 : 1.02 : Updated to JCU 1.03, PFV 1.01
*               Feb. 2, 2018 : 2.01 : Updated to JCU 2.01, PFV 1.03
***********************************************************************************/

1. Before Use

  This example program has been run and confirmed by the CPU board RTK772100BC00000BR
  with the RZ/A1H group R7S72100. Use this Application note and the example program 
  as a reference for you software development.
 

  ****************************** CAUTION ******************************
   This example programs are all reference, and no one to guarantee the 
   operation. Please use this example program for the technical 
   reference when customers develop software.
  ****************************** CAUTION ******************************


2. Directory Configuration
  The files used in this example program are listed in the description file 
  (filecomposition.txt) of the RZ/A1H directory and file composition.

  Main directories:

  OS less environment:
    workspace\RZ_A1H_JCU_PFV_Example    : Project Directory (Arm DS-5, IAR EWARM)
    workspace\RZ_A1H_JCU_PFV_Example_e2 : Project Directory (GNU e2studio)

  RTX-BSP environment (with RTOS):
    workspace\RZ_A1H_BSP_JCU_PFV_Arm_patch : Patch of BSP (Arm DS-5)


3. System Requirements
  The system requirements for this example program are listed below.

    CPU                     : RZ/A1H
    Evaluation board        : RTK772100BC00000BR (CPU board)
                            : RTK7721000B00000BR(OPT board)
    Arm     : IDE           : ARM Integrated development environment
                              ARM Development Studio 5 (DS-5(TM)) Ver.5.15
    Arm     : Compiler      : ARM(R) Compiler
                              ARM C/C++ Compiler/Linker/Assembler Ver.5.03 [Build 102]
    IAR     : IDE, Compiler : IAR Embedded Workbench for ARM 7.80.4.12495
    Renesas : IDE           : e2 studio (Version: 5.3.0.023)
    Renesas : Compiler      : GNUARM-NONE-EABI v16.01

    (IDE = Integrated development environment)

    Customers need to prepare the emulator which corresponds to the RZ/A1H. 
    The method for writing a program to the NOR flash memory depends on the emulator. 
    Customers are also required to prepare the environment which 
    corresponds to the emulator in use for the program writing environment.


4. About Example Program

  This example program operates the following processing.

  (1) R_JCU_SampleDecode function - Decodes JPEG data via JCU unit
      decode_sample.c

      [ On-Chip RAM >> JCU decompression >> On-Chip RAM ]

      Source image is the global variable corresponding to the file
        workspace\RZ_A1H_JCU_PFV_Example\armcc\common\src\samples\jcu\Image\image01.jpg
      Size of image is 800x480.
      This function decodes to ARGB8888 format frame buffer in Large-Capacity On-Chip RAM.
      The address of data before decompression is set to "buffer.source.address" variable.
      The address of data after decompression is set to "buffer.destination.address" variable.

  (2) R_JCU_SampleDecodeEncode function - Encodes and decodes JPEG data
      decode_encode_sample.c

      [ On-Chip RAM >> JCU decompression >> On-Chip RAM >> JCU compression >> On-Chip RAM ]

      This is added JPEG decoding based on R_JCU_SampleDecode function.
      Compressed data is output to Large-Capacity On-Chip RAM.
      The address of data before decompression is set to "buffer.source.address" variable.
      The address of data after decompression is set to "buffer.destination.address" variable.
      If compressed data was saved as binary, it is the JPEG file.
      You can set calculated quantization table (example) by input quality in
      "QuantizationTable_Generator.html" file.

  (3) R_JCU_SampleDecodeAndShow function - Decodes and play Motion JPEG data and show on the display
      decode_show_sample.c

      [ On-Chip RAM >> JCU decompression >> On-Chip RAM >> VDC5(OUT) >> Display ]

      The movie data is "g_MotionJPEG_Sample" variable which has data copied from
      attached "MotionJPEG.avi" file. The sample program picks up JPEG data as each
      frame from AVI format container.
      Frames are decoded to YcbCr422 format and other format frame memory in On-Chip RAM
      and output to D-sub (Opposite RCA connector).
      Size of screen is 800x600. Size of frame is 800x480.
      Video output of VDC is used. Video signal input is not used.

  (4) R_JCU_SampleVideoEncodeAndShowI function - Encodes and decodes video signal input
      video_encode_decode_i_sample.c

      [ Camera >> VDC5(IN) >> On-Chip RAM >> JCU compression >> On-Chip RAM
        >> JCU decompression >> On-Chip RAM >> VDC5(OUT) >> Display ]

      This function continues to encode and decode each top and bottom field of video
      signal input connected with RCA connector (at left up) by interlace at the same
      time (60fps). Decoded image is shown
      through D-sub (opposite to RCA connector).
      This program receives events signaled from interrupt handlers at
      "R_OSPL_EVENT_Wait" function and responds as followings.
        1. After external video image was put in the video buffer,
           JPEG compression is started.
        2. After the compression was finished, the JPEG data is started to
           decompress to the back buffer.
        3. After the decompression was finished, this program shows by swapping
           the back buffer for the front buffer.
      The buffer put JPEG data has 1 frame only.
      There is 1 frame delay because operations of compression, decompression
      and showing.
      If compressed data was saved as binary, it is the JPEG file.

  (5) R_JCU_SampleVideoEncodeAndShowP function - Encodes and decodes video signal input
      video_encode_decode_p_sample.c

      [ Camera >> VDC5(IN) >> On-Chip RAM >> JCU compression >> On-Chip RAM
        >> JCU decompression >> On-Chip RAM >> VDC5(OUT) >> Display ]

      This function continues to encode and decode video signal input connected with
      RCA connector (at left up) by progressive at the same time (60fps). The other
      specifications are same as R_JCU_SampleVideoEncodeAndShowI function.

  (6) Sample_PFV_PIO function - Converts pixel format via PFV unit
      pfv_sample.c

      [ On-Chip RAM >> PFV Conversion >> On-Chip RAM ]

      CPU transfers pixel data from the memory to PFV and
      transfers converted pixel data from PFV to the memory.
      This function returns immediately and go to next example program.

  (7) Sample_PFV_DMAC function - Converts pixel format via PFV unit with DMAC unit
      pfv_sample.c

      [ On-Chip RAM >> DMAC >> PFV Conversion >> DMAC >> On-Chip RAM ]

      DMAC transfers pixel data from the memory to PFV and
      transfers converted pixel data from PFV to the memory.
      This function returns immediately and go to next example program.

  (8) Sample_PFV_DMAC_Image function - Shows and blinks a image on the display
      pfv_sample.c

      [ On-Chip RAM >> DMAC >> PFV Conversion >> DMAC >> On-Chip RAM >> VDC5(OUT) >> Display ]

      This program changes gain parameter in PFV and change pixel format
      from ARGB8888 to YCbCr422.
      Source image is the global variable corresponding to the file
        workspace\RZ_A1H_JCU_PFV_Example\armcc\common\src\samples\pfv\Image\PFV_Sample.bmp
      This program outputs to D-sub (Opposite to RCA connector).
      This function returns after several seconds and go to next example program.

   JCU and PFV are available without any display.
   For example, Sample_PFV_DMAC function and R_JCU_SampleDecode function do not use VDC5.
   Refer to application notes for the details about the example program. 


5. Operation Confirmation Conditions
  
  (1) Boot mode
      - Boot mode 0 - For OnChip-RAM or NOR flash
        (Boot from the memory (16-bit bus width) connected to the CSO space.)
      - Boot mode 3 - For serial flash boot
        (Boot from the flash memory 1 connected with SPI multi I/O bus space 1)
        * The program cannot be activated when other boot mode is set.

  (2) Operating frequency
      The RZ/A1H clock pulse oscillator is set to see that the RZ/A1H clocks on the CPU
      board RTK772100BC00000BR have the following frequencies. 
      (The frequencies indicate the values in the state that the clock with 13.33MHz
      is input to the EXTAL pin in RZ/A1H clock mode 0.)
      - CPU clock (I clock)                 : 400MHz
      - Image processing clock (G clock)    : 266.67MHz
      - Internal bus clock (B clock)        : 133.33MHz
      - Peripheral clock1 (P1 clock)        : 66.67MHz
      - Peripheral clock0 (P0 clock)        : 33.33MHz

  (3) Setting for asynchronous communication
      - Bit rate        : 115200 bps
      - Data bit        : 8 bit
      - Parity bit      : none
      - Stop bit        : 1 bit

  (4) Setting for cache

    (4-a) The project for OS less
      Initial setting for the L1 cache is executed by the MMU. Refer to the application
      note "Setting for MMU" for the valid/invalid area of L1 cache.
      This example program does not provide the L2 cache setting.
      The virtual address as On-chip RAM not mirror area is expected to
      map MMU to physical address.
      Modify in "r_ospl_memory.c", if your board was other than confirmation conditions.
      This example does not use L2 cache.

    (4-b) The project for RTX-RTOS
      The project expects MMU setting that a part of On-Chip RAM has uncached area like
      the setting written in "scatter.sct" file.
      Physical address is same as virtual address at all of memory area.
      Modify in "r_ospl_memory.c", if your board was other than confirmation conditions.


6. Operational Procedure

  Use the following procedure to execute this example program.
  OPT board is not necessary without any display (VDC5).
  This file describes the following cases.
    - IDE : { Arm DS-5,  Renesas e2 studio,  IAR Embedded Workbench }
    - boot : { On-Chip RAM,  NOR flash,  Serial flash }
    - OS : { OS less,  RTX-BSP }
  About the current setting of boot, see "7. How to change the download target".

  (1) Setting for DIP switches and jumpers  
    (1-1) CPU board - For On-Chip RAM or NOR flash
      Set the DIP switches and jumpers of the RTK772100BC00000BR as follows.

      - SW1-1: ON, SW1-2: ON, SW1-3: ON, SW1-4: ON, SW1-5: ON, SW1-6: ON
             (Fix MD_BOOT0, MD_BOOT1, MD_BOOT2, MD_CLK, and MD_CLKS on "L" level)
             (Boots from NOR flash memory or On-Chip RAM)
      - SW2-1: OFF, SW2-2: ON, SW2-3: ON, SW2-4: ON
             (SW2-1:Used on option board LCD1_DATA10)
             (SW2-3:Fix BSCANP on "L" level)
      - SW3-1:OFF, SW3-2:OFF, SW3-3:OFF, SW3-4:OFF,
        SW3-5:OFF, SW3-6:OFF, SW3-7:OFF, SW3-8:OFF
      - JP1 : Open (Setting to use device U4 (SDRAM1) and U5 (SDRAM2))
      - JP2 : 1-2 (Connect A16 to device U2 (NOR-flash1) and U3 (NOR-flash2))
      - JP3 : 1-2 (Connect IRQ6 to device SW6(IRQ6 switch))
      - JP4 : 2-3 (Connect ET_MDC to device U20(Ethernet PHY))
      - JP5 : 2-3 (Connect CS0 to device U2 (NOR-flash1))
      - JP6 : 2-3 (Connect CS1 to device U3 (NOR-flash2))
      - JP7 : 1-2 (Connect SPBSSL_0 to device U6(Serial-flash1) and U7(Serial-flash2))
      - JP8 : Open (Setting to use device U2 (NOR-flash1) and U3 (NOR-flash2))
      - JP9 : 1-2 (Setting to use USB ch0 as host mode(Supply VBUS0))
      - JP10: 1-2 (Connect SSL40 to device U19(Audio CODEC))
      - JP11: 1-2 (Setting to use USB ch1 as host mode(Supply VBUS1))
      - JP12: 1-2 (Connect RxD2 to device U27)
      - JP13: 1-2 (Connect TxD2 to device U27)
      - JP14: 2-3 (Setting to supply system power from J25(used AC adapter))
      - JP15: 1-2 (Setting to supply 5V power from U30)
      - JP16: 1-2
      - JP17: 1-2
      - JP18: 1-2 (Setting to supply 3.3V digital power from U32 for R7S72100)
      - JP19: 1-2 (Setting to supply 3.3V analog power from U32 for R7S72100)
      - JP20: 1-2
      - JP21: 1-2 (Setting to supply 1.18V power from U34 for R7S72100)
      - JP22: 1-2

      Refer to the CPU board RTK772100BC00000BR user's manual for more details about
      setting for the DIP switches and jumpers.

    (1-2) CPU board - For serial flash boot
      Serial flash setting (the difference with On-Chip RAM and NOR flash) is the following
      DIP switches and jumpers.

      - SW1-1: OFF, SW1-2: ON, SW1-3: OFF, SW1-4: ON, SW1-5: ON, SW1-6: ON
        (Fix MD_BOOT1, MD_CLK and MD_CLKS on "L" level. Fix MD_BOOT0 and MD_BOOT2 on "H" level.)
      - JP5 : 1-2 (Connected to DIP switch for system setting (SW-3) as MD_BOOT2 input pin)
      - JP8 : 1-2 (Connected to serial flash memory (U8) as SPBSSL_1 output pin)

    (1-3) OPT board
      Set the DIP switches and jumpers of the RTK7721000B00000BR as follows.

      - SW14-1: OFF, SW14-2: ON,  SW14-3: OFF, SW14-4: OFF,
        SW14-5: ON,  SW14-6: OFF, SW14-7: OFF, SW14-8: OFF
      - J1  : Open
      - JP1 : Open (Setting to use SCI mode)
      - JP2 : Open (Connect LCD1_DATA16 to J12-J14 and U10)
      - JP3 : Open (Connect LCD1_DATA9 to J12-J14 and U10)
      - JP4 : 2-3 (Connect P10_3 to J17(CMOS camera))
      - JP5 : Open (Connect SCI_RXD0 to J2(SIM card slot) /
                    Connect RxD3 to J3(UART connector))
      - JP6(*): Open (Use P3_7 as CS1 output pin)
      - JP7(*): 1-2 (Use P5_9 as LCD1_DATA16 output pin)

      Refer to the OPT board RTK7721000B00000BR user's manual for more details about 
      setting for the DIP switches and jumpers.
      (*) The OPT board of undescribed revision is equivalent to 1-2 shorted
          because the jumpers don't be implement.

  (2) Connecting with emulator
      Connect the emulator and the CPU board RTK772100BC00000BR. 
      With regard to connecting the emulator and the debugger, set the configuration
      corresponding to the debugging system in use when it is required. 

      (2-a) Case of Renesas e2 studio
          Connected to J-Link LITE.

      (2-b)Case of IAR Embedded Workbench
          Connected to I-jet.

  (3) Connecting with display
      Connect the D-sub display cable and J15 D-sub connector (VDC5 ch0) in option board.

  (4) Building example code

      (4-a) Case of OS less, Arm DS-5
          Copy the "workspace\RZ_A1H_JCU_PFV_Example" directory into the workspace
          directory of the host PC
              (e.g. "C:\Workspace").
          Activate the integrated development environment DS-5.
          Open
              "C:\Workspace\RZ_A1H_JCU_PFV_Example\JCU_PFV_Example\armcc_Workspace".
          DS-5 [ File >> Import >> General >> Existing Projects into Workspace ].
          Import all projects in
              "C:\Workspace\RZ_A1H_JCU_PFV_Example".
          Click right button on "RZ_A1H_JCU_PFV_Sample_armcc" and [ Build Project ]
          to generate the executable file "RZ_A1H_JCU_PFV_Sample_armcc.axf".

      (4-b) Case of OS less, IAR EWARM
          Copy the "workspace\RZ_A1H_JCU_PFV_Example" directory into the workspace
          directory of the host PC
              (e.g. "C:\Workspace").
          Move "common" directory.

          source:
              JCU_PFV_Example\armcc\common
          destination:
              JCU_PFV_Example\iccarm\common

          To start EWARM, double click "RZ_A1H_JCU_PFV_Sample.eww".
          Click right button on "RZ_A1H_JCU_PFV_Sample" and [ Make ]
          to generate the executable file "RZ_A1H_JCU_PFV_Sample.out".

      (4-c) Case of OS less, Renesas e2 studio
          Copy the "workspace\RZ_A1H_JCU_PFV_Example_e2" directory into the workspace
          directory of the host PC
              (e.g. "C:\Workspace").
          Activate the integrated development environment e2 studio.
          Open
              "C:\Workspace\RZ_A1H_JCU_PFV_Example_e2\Workspace".
          e2studio [ File >> Import >> General >> Existing Projects into Workspace ].
          Import all projects in
              "C:\Workspace\RZ_A1H_JCU_PFV_Example_e2".
          Also import after checking "Search for nested projects".
          Click right button on "RZA1_JCU_PFV_gcc" and [ Build Project ]
          to generate the executable file "RZA1_JCU_PFV_gcc.x".

      (4-d) Case of RTX-BSP, Arm DS-5
          Copy the "CMSIS_RTOS_RTX" directory from RZ/A1H RTX BSP V2.03
          (an_r01an2200jj0203_rza1h_other.zip) into the workspace
          directory of the host PC
              (e.g. C:\Workspace\RZ_A1H_RTX_JCU_PFV_Arm).
          Double click "workspace\RZ_A1H_RTX_JCU_PFV_Arm_patch\AttachPatch.vbs" and
          attach the patch to
              "C:\Workspace\RZ_A1H_RTX_JCU_PFV_Arm".
          Activate the integrated development environment DS-5.
          Open
              "C:\Workspace\RZ_A1H_RTX_JCU_PFV_Arm\Workspace".
          DS-5 [ File >> Import >> General >> Existing Projects into Workspace ].
          Import all projects in
              "C:\Workspace\RZ_A1H_RTX_JCU_PFV_Arm" and
          all projects in
              "C:\Workspace\RZ_A1H_RTX_JCU_PFV_Arm\CMSIS_RTOS_RTX\RTOS".
          Click right button on "Display_smp1" and [ Build Project ]
          to generate the executable file "Display_smp1.axf".
          Notice: "SVC_Stack_Size" in "Display\sample1\ARM\setup_Renesas_RZ_A1.s"
            is changed to the value of "GS_INTERRUPT_STACK_SIZE" in "r_ospl.c".

  (5) Downloading boot program - For only serial flash boot
      Write the boot program "RZ_A1H_sflash_boot_init_armcc.axf" into serial flash
      memory by using download function of emulator.
      To get the boot program's source, search R01AN1960JJ0101 in Renesas Japan
      home page and download it.

  (6) Downloading example program
      Write the load module (*.axf, *.x, *.out) of the example program
      using download function of the emulator.

      (6-a) Case of Renesas e2 studio
          [ Run >> Debug Configurations >> (Child node of Renesas GDB Hardware Debugging ) ]
          [ Debug ]B
          (When the program was downloaded into flash memory, CPU is reset after downloading.)
          If "Confirm Perspective Switch" was shown, click "Yes".

      (6-a) Case of IAR Embedded Workbench
          [ Project >> Download and Debug ]
          (When the program was downloaded into flash memory, CPU is reset after downloading.)

  (7) Executing example program

      (7-a) Case of Renesas e2 studio
          Click [Resume] button (green right arrow).
          To exit the debugger, click [Terminate] button (red square).

      (7-b) Case of IAR Embedded Workbench
          Click [Go] button.
          To exit the debugger, click [Stop Debugging] button (red X).

      (7-c) Case of another emulator
          Use run function of your emulator.


7. How to change the download target

  a. Case of OS less, Arm DS-5

    Boot from            LOAD_START(*1)
    --------------------------------------------------------------------
    On-Chip RAM          (UNCACHED_LRAM_END - RAM_DOWNLOAD_MAX_SIZE)
    NOR flash            (NOR_START)
    Serial flash         (SERIAL_FLASH_START)

    (*1) The define of "LOAD_START" macro in "scatter_file\scatter.scat" file


  b. Case of OS less, Renesas e2 studio

    Boot from            Comment out for RAM_only(*1)  For RAM_only(*2)
    --------------------------------------------------------------------
    On-Chip RAM          Comment out                   Enabled
    NOR flash            Enabled                       Comment out
    Serial flash         Not supported

    (*1) The line of /* Comment out for RAM_only */
         written in "linker_script_file\NOR_or_RAM.ld" file
    (*2) The line of /* For RAM_only */
         written in "linker_script_file\NOR_or_RAM.ld" file


  c. Case of OS less, IAR Embedded Workbench

    Boot from            Support or not support
    --------------------------------------------------------------------
    On-Chip RAM          not support
    NOR flash            support
    Serial flash         not support


  d. Case of RTX-BSP, Arm DS-5

    Boot from            Scatter file (*1)
    --------------------------------------------------------------------
    On-Chip RAM          scatter.scat
    NOR flash            scatter_nflashboot.scat
    Serial flash         scatter_sflashboot.scat

    (*1) Scatter file that is set in linker option.
        Set .scat file by clicking right button on the project in DS-5
        [ Properties >> C/C++ Build >> Settings >> ARM Linker 5 >> Image Layout
        >> Scatter file ].
        Relink the project, if the setting was changed.

/* End of File */
