/***********************************************************************************************************************
* File Name    : readme.txt
* Description  : Contains general information about Example Project and detailed instructions.
***********************************************************************************************************************/

1. Project Overview:
    The example project demonstrates the typical use of the IIC master HAL module APIs.
    The project initializes IIC master module with fast mode and interfaces with PmodACL™ Board for ADXL345.

    On power up after establishing the connection of sensor with the board, it displays accelerometer axis data on 
    RTTviewer. Any API/event failure will be displayed on RTTviewer.

2. Software Requirements:
    Renesas Flexible Software Package (FSP): Version 4.1.0
    e2 studio: Version 2026-04.1
    GCC ARM Embedded Toolchain: Version 13.3.1.arm-13-24
    SEGGER J-Link RTT Viewer: Version 8.60

3. Hardware Requirements:
    RZ supported boards: RZ/N2L-RSK.
    1 x RZ board.
    1 x USB Type-C cable.
    1 x USB Type-A to micro USB cable.
    1 x Pmod ACL.

4. Hardware Configurations:
    (1) Boot Mode:
        Boot mode 3 (SCIF Downloading) with CA55 cold boot.
    (2) Set for DIP switches and jumpers as follow:

        1. *External flash memory must be blank to start this sample program (RAM execution).
        NOR flash memory on this board is blank, so set the operating mode switch for 16-bit bus boot mode (NOR flash).
        SW4.1 : ON
        SW4.2 : OFF
        SW4.3 : ON

        2. *Enables signals other than the external bus. (CAN, Emulator, I2C, etc.).
        SW4.7  : ON

        3. *Set SW8 following.
        SW8.2  : ON
        SW8.4  : ON
        SW8.7  : ON
        SW8.10 : ON

        4. *Set SW11 following.
        SW11.1  : ON
        SW11.5  : ON
        SW11.7  : ON
        SW11.10 : ON

        5. Connect Pmod ACL and RSK + RZN2L Board as follows.
        Pmod ACL has two on board connectors, J2 is used for I2C communication.
        ------------------------------------
        J2 (Pmod ACL)       J27 Grove (I2C)
        |1  5|---SCL  --->  J27.1
        |2  6|---SDA  --->  J27.2
        |3  7|---GND  --->  J27.4
        |4  8|---VCC  --->  J27.3
        ------                       -------
        ( RZ/N2L RSK uses IIC1)

Note:
1. Segger RTT block address may be needed to download and observe EP operation using a hex file with RTT-Viewer.
   RTT Block address for hex file committed in repository are as follows:
   a. e2studio: 0x30100000

2. If an EP is modified, compiled, and downloaded please find the block address (for the variable in RAM called _SEGGER_RTT) 
   in .map file generated in the build configuration folder (Debug/Release).