RAFW Flexible Software Package Documentation  Release v2.0.1

 
Clock Settings (Low Power, XTAL etc.)

Detailed Description

Settings for the different clock-types of the chip.

Macros

#define dg_configLP_CLK_SOURCE
 Source of Low Power clock used (LP_CLK_IS_ANALOG, LP_CLK_IS_DIGITAL)
 
#define dg_configEXT_LP_IS_DIGITAL
 External LP type. More...
 
#define MIN_SCALE_MS
 Minimum sleep time. More...
 
#define dg_configRC32K_FREQ
 Vaule of the RC32K oscilator frequency in Hz.
 
#define dg_configLP_CLK_DRIFT
 Acceptable clock tick drift (in parts per million) for the Low-power clock.
 
#define dg_configXTAL32K_SETTLE_TIME
 Time needed for the settling of the LP clock, in msec.
 
#define dg_configXTAL40M_SETTLE_TIME_IN_USEC
 XTAL40M settle time. More...
 
#define dg_configENABLE_XTAL40M_ON_WAKEUP
 Enable XTAL40M upon system wake-up. More...
 
#define dg_configVOLTAGE_CHECK_LP_CYCLES
 The number of LP clock cycles required to check the voltage of an LDO during startup.
 
#define dg_configHW_FSM_WAKEUP_CYCLES
 The number of LP clock cycles required for the HW FSM to detect the wake-up signal.
 
#define dg_configSYSTEM_STARTUP_CYCLES
 The number of LP clock cycles required for the system to start-up.
 
#define dg_configWAKEUP_RC32_TIME_SLOW
 RC32 wake-up time in slow wake-up mode. More...
 
#define dg_configWAKEUP_RC32_TIME_FAST
 RC32 wake-up time in fast wake-up mode. More...
 
#define dg_configWAKEUP_RC32_TIME_ULTRA_FAST
 RC32 wake-up time. More...
 
#define dg_configDEFAULT_CLK_FREQ_TRIM_REG__XTAL32M_TRIM__VALUE
 XTAL32M trimming default settings.
 

Macro Definition Documentation

◆ dg_configEXT_LP_IS_DIGITAL

#define dg_configEXT_LP_IS_DIGITAL

External LP type.

  • 0: a crystal is connected to XTAL32Kp and XTALK32Km
  • 1: a digital clock is provided.
Note
the frequency of the digital clock must be 32KHz or 32.768KHz and be always running.

◆ MIN_SCALE_MS

#define MIN_SCALE_MS

Minimum sleep time.

No power savings if we enter sleep when the sleep time is less than N LP cycles.

Note
It should be ~3msec but this may vary.

◆ dg_configXTAL40M_SETTLE_TIME_IN_USEC

#define dg_configXTAL40M_SETTLE_TIME_IN_USEC

XTAL40M settle time.

Time needed for the settling of the XTAL40M, in usec.

Note
If set to zero, the settling time will be automatically adjusted.

◆ dg_configENABLE_XTAL40M_ON_WAKEUP

#define dg_configENABLE_XTAL40M_ON_WAKEUP

Enable XTAL40M upon system wake-up.

If set to 1 the PDC will enable XTAL40M when it wakes-up M33

◆ dg_configWAKEUP_RC32_TIME_SLOW

#define dg_configWAKEUP_RC32_TIME_SLOW

RC32 wake-up time in slow wake-up mode.

This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code using RC32 in slow wake-up mode.

Note
Wake-up time calculation: dg_configHW_FSM_WAKEUP_CYCLES cycles for wake-up 1 additional cycle for slow wake-up 2 cycles for V30 (worst case Vclamp -> 3V) 1 cycle for BG dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V12 and V14 dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V18P dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V18 dg_configSYSTEM_STARTUP_CYCLES cycles for system start-up

◆ dg_configWAKEUP_RC32_TIME_FAST

#define dg_configWAKEUP_RC32_TIME_FAST

RC32 wake-up time in fast wake-up mode.

This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code using RC32 in fast wake-up mode.

Note
Wake-up time calculation: dg_configHW_FSM_WAKEUP_CYCLES cycles for wake-up dg_configVOLTAGE_CHECK_LP_CYCLES cycles for V12 (worst case 0.75V -> 0.9V) dg_configSYSTEM_STARTUP_CYCLES cycles for system start-up

◆ dg_configWAKEUP_RC32_TIME_ULTRA_FAST

#define dg_configWAKEUP_RC32_TIME_ULTRA_FAST

RC32 wake-up time.

This is the maximum time, in LP cycles, needed to wake-up the chip and start executing code using RC32 in ultra-fast wake-up mode.

Note
Wake-up time calculation: dg_configHW_FSM_WAKEUP_CYCLES cycles for wake-up dg_configSYSTEM_STARTUP_CYCLES cycles for system start-up