OSPI Flash (r_ospi_w)

Functions
fsp_err_t	R_OSPI_W_Open (spi_flash_ctrl_t *const p_ctrl, spi_flash_cfg_t const *const p_cfg)
fsp_err_t	R_OSPI_W_Close (spi_flash_ctrl_t *const p_ctrl)
fsp_err_t	R_OSPI_W_DirectWrite (spi_flash_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
fsp_err_t	R_OSPI_W_DirectRead (spi_flash_ctrl_t *const p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
fsp_err_t	R_OSPI_W_DirectTransfer (spi_flash_ctrl_t *const p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
fsp_err_t	R_OSPI_W_SpiProtocolSet (spi_flash_ctrl_t *const p_ctrl, spi_flash_protocol_t spi_protocol)
fsp_err_t	R_OSPI_W_XipEnter (spi_flash_ctrl_t *const p_ctrl)
fsp_err_t	R_OSPI_W_XipExit (spi_flash_ctrl_t *const p_ctrl)
fsp_err_t	R_OSPI_W_Write (spi_flash_ctrl_t *const p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
fsp_err_t	R_OSPI_W_Erase (spi_flash_ctrl_t *const p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
fsp_err_t	R_OSPI_W_StatusGet (spi_flash_ctrl_t *const p_ctrl, spi_flash_status_t *const p_status)
fsp_err_t	R_OSPI_W_BankSet (spi_flash_ctrl_t *const _ctrl, uint32_t bank)
fsp_err_t	R_OSPI_W_AutoCalibrate (spi_flash_ctrl_t *const p_ctrl)

Detailed Description

Driver for the OSPI_W peripheral on RA6W1/RA6W2 MCUs. This module implements the SPI Flash Interface.

Overview

The OSPI_W peripheral supports xSPI (or OSPI) compatible external memory devices, and it interfaces with these devices to perform data I/O Operations. Please note that this document will reference the xSPI protocol to which OSPI is a subset. The OSPI_W peripheral is compatible with a variety of xSPI protocol operating modes.

Features

The OSPI_W driver has the following key features to support the xSPI device:

• Perform data I/O Operation in both SPI and DOPI modes
• Direct memory-mapped access to the xSPI device memory up to 64 MB.
• Erasing the xSPI device
• Sending device specific commands and reading back responses of up to 8 bytes
• 3 byte addressing for SPI
• 4 byte addressing for SPI and DOPI
• Decryption-on-the-fly

Note

The RA6W1/RA6W2 uses this ospi for default code memory. that means when RTOS call ospi_w APIs, it already be activated and in automode.

Configuration

OSPI_W Flash:

Build Time Configurations for r_ospi_w

The following build time configurations are defined in fsp_cfg/r_ospi_w_cfg.h:

Configuration	Options	Default	Description
Memory-mapping Support
Prefetch Function	Enable Disable	Enable	Enable prefetch function on memory-mapped reads.
XiP Support	Enable	Enable	Enable the use of XiP enter and exit codes.
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
DMAC Support	Disable	Disable	RRQ61X dose not support DMAC.
Autocalibration Support	Disable	Disable	RRQ61x does not support autocalibration.
DOTF Support	Disable	Disable	DOTF will activate in secure mode.

Configurations for Storage > OSPI Flash (r_ospi_w)

This module can be added to the Stacks tab via New Stack > Storage > OSPI Flash (r_ospi_w).

Configuration	Options	Default	Description
General
Name	Name must be a valid C symbol	g_ospi	Module name.
Channel	Only one channel available	0	Specify the OSPI chip select line to use.
Initial Protocol Mode	SPI (1S-1S-1S) DSPI (1S-2S-2S) DSPI (2S-2S-2S) QSPI (1S-4S-4S) QSPI (4S-4S-4S) QSPI (4S-4D-4D) Dual data rate OSPI (8D-8D-8D)	SPI (1S-1S-1S)	Select the initial protocol mode of the xSPI target device. Please see the documentation for examples of changing the protocol mode.
Initial Address Bytes	3 4	3	Select the number of address bytes.
Address line for page program	SPI_FLASH_DATA_LINES_1 SPI_FLASH_DATA_LINES_4 SPI_FLASH_DATA_LINES_8	SPI_FLASH_DATA_LINES_4	Select the number of data line for program address.
Write Status Bit	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Write Status Command.
Write Enable Bit	Must be an integer between 0 and 7	1	Which bit contains the write enable status returned from the Write Enable Command.
Sector Erase Size	Must be an integer greater than or equal to 0	4096	The sector erase size. Set Sector Erase Size to 0 if Sector Erase is not supported.
Block Erase Size	Must be an integer greater than or equal to 0	32768	The block(32k) erase size. Set Block Erase Size to 0 if Block Erase is not supported.
General > Block[64k] Erase Size	Must be an integer greater than or equal to 0	65536	The block(64k) erase size. Set Block Erase Size to 0 if Block Erase is not supported.
Defaults
Defaults > Command Definitions
Page Program Command	Page Program Command under OPI|QPI Mode|Command Definitions	0x32	Default command to program a page.
Read Command	Read Command under OPQ|QPI Mode|Command Definitions	0xEB	Default command to read.
Write Enable Command	Write Enable Command under SPI Mode|Command Definitions	0x06	Default command to enable write.
Status Command	Status Command under SPI Mode|Command Definitions	0x05	Default command to query the status of a write or erase command.
Defaults > Erase Command Definitions
Sector Erase Command	Must be an integer between 0x01 and 0xFFFF, inclusive.	0x20	Default command to erase a sector. The lower byte will be used for 1-byte commands. Set to 0 if unused.
Block Erase Command	Must be an integer between 0x01 and 0xFFFF, inclusive.	0x52	Default command to erase a block(32k). The lower byte will be used for 1-byte commands. Set to 0 if unused.
Block(64k) Erase Command	Must be an integer between 0x01 and 0xFFFF, inclusive.	0xD8	Default command to erase a block(64k). The lower byte will be used for 1-byte commands. Set to 0 if unused.
High-speed Mode
High-speed Mode > Command Definitions
Page Program Command	OSPI|QPI Page Program Command under High-speed Mode|Command Definitions	0x32	The command to program a page in OPI|QPI mode.
Dual Read Command	OSPI|QSPI Read Command under High-speed Mode|Command Definitions	0xEB	The command to read in High-speed mode (8DTRD).
Write Enable Command	OSPI|QPI Write Enable Command under High-speed Mode|Command Definitions	0x06	The command to enable write in OPI mode. Set to 0 to ignore.
Status Command	OSPI|QPI Status Command under High-speed Mode|Command Definitions	0x05	The command to query the status of a write or erase command in OPI mode. Set to 0 to ignore.
Sector Erase Command	Must be an integer between 0x01 and 0xFFFF, inclusive.	0	The command to erase a sector for high-speed mode. Set to 0 if unused.
Block Erase Command	Must be an integer between 0x01 and 0xFFFF, inclusive.	0	The command to erase a block for high-speed mode. Set to 0 if unused.
Chip Erase Command	Must be an integer between 0x01 and 0xFFFF, inclusive.	0	The command to erase the entire chip for high-speed mode. Set to 0 if unused.
Protocol	SPI (1S-1S-1S) DSPI (1S-2S-2S) DSPI (2S-2S-2S) QSPI (1S-4S-4S) QSPI (4S-4S-4S) QSPI (4S-4D-4D) Dual data rate OSPI (8D-8D-8D)	QSPI (1S-4S-4S)	Select the High-Speed xSPI protocol.
Command Length Bytes	1 2	1	Command length in bytes
Memory Read Dummy Cycles	Must be an integer between 0 and 31	0x02	Memory read dummy cycles
Status Read Dummy Cycles	Must be an integer between 0 and 31	0	Status read dummy cycles
HW config
Clk_div	Divide by 1 Divide by 2 Divide by 4 Divide by 8	Divide by 2	Clock divide value
Clock mode	Mode 0 Mode 1	Mode 1	Clock mode Mode 0: OSPI_W clock is low when CS is high Mode 1: OSPI_W clock is high when CS is high
IO2 pad direction	Auto Sel Output	Auto Sel	IO2 pad direction Auto sel : Pad is determined by the controller Output : Pad is output
IO2 pad value	Low High	Low	IO2 pad value
IO3 pad direction	Auto Sel Output	Auto Sel	IO3 pad direction Auto Sel : Pad is determined by HW Output : Pad is output
IO3 pad value	Low High	Low	IO3 pad value
IO4_7 pad direction	Auto Sel Output	Auto Sel	IO4_7 pad direction Auto Sel : Pad is determined by HW Output : Pad is output
IO4_7 pad value	0000 1111	0000	IO4_7 pad value
HREADY mode	Wait No wait	Wait	HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers. This configuration is useful when the frequency of the OSPI clock is much lower than the clock of the AMBA bus, in order to avoid locking the AMBA bus for a long time. When set to OSPI_W_DEVICE_HREADY_MODE_WAIT, there is no need to check the OSPIC_BUSY for detecting completion of the requested access.
Sampling edge	Edge pos Edge neg	Edge neg	Clock edge setting for the sampling of the incoming data when the read pipe is disabled
Read pipe setting	Enable Disable	Enable	Read pipe setting. When read pipe is disabled, the sampling clock is determined by sampling_edge. but when it is enabled, it is determined by pipe_delay. It is always recommended to enable read pipe and set the pipe_delay to the optimal value.
Pipe delay	Pipe delay 0 Pipe delay 1 Pipe delay 2 Pipe delay 3 Pipe delay 4 Pipe delay 5 Pipe delay 6 Pipe delay 7	Pipe delay 7	Read pipe clock delay in relation to the falling edge of ospi_w_clock. Always sets this value to PIPE_DELAY_7 for power supply voltage 1.2V and PIPE_DELAY_2 for power supply voltage 0.9V
Slew rate control	Slew rate 0 Slew rate 1 Slew rate 2 Slew rate 3	Slew rate 0	Pads slew rate control Slew rate 0 Rise = 1.7 V/ns, Fall = 1.9 V/ns (weak) Slew rate 1 Rise = 2.0 V/ns, Fall = 2.3 V/ns Slew rate 2 Rise = 2.3 V/ns, Fall = 2.6 V/ns Slew rate 3 Rise = 2.4 V/ns, Fall = 2.7 V/ns (strong)
Drive current	4mA 8mA 12mA 16mA	12mA	Pads drive current
Flash model config
Instr bus mode	Single mode Dual mode Quad mode Octa mode	Single mode	The bus mode of the instruction phase
Bus mode	Single mode Dual mode Quad mode Octa mode	Quad mode	The bus mode of all phases apart from the instruction phase which is determined by instr_bus_mode
Instruction size	1byte 2byte	1byte	Flash instruction size
Read opcode	Read command for automode	0xEB	Read opcode.
Erase opcode	Erase command for automode	0x20	Erase opcode.
Suspend opcode	Suspend command for automode	0x75	Suspend opcode.
Resume opcode	Resume command for automode	0x7A	Resume opcode.
Read status opcode	Read status command for automode	0x05	Read status opcode.
Write enable opcode	Read status command for automode	0x06	Write enable opcode.
Dummy cycles	Dummy cycles	0x02	Dummy cycles for fast read(it is related with read opcode).
Address size	24bit address size 32bit address size	24bit address size	Flash address size.
Instruction mode	Anytime Once	Once	Instruction mode in auto access mode. Anytime : Transmit instruction at any burst access Once : Transmit instruction only in the first access after the selection of Auto Mode
Extra byte setting	Enable Disable	Enable	Enable/Disable the extra byte phase in automode. Disable : Don't send the extra byte Enable : Send the extra byte
Extra byte value	Extra byte vaule	0xA0	The value of an extra byte that will be transferred after address phase (if enabled)
Busy bit	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Write Status Command.

Note

The default flash model of the RA6W1/RA6W2 EVK is AT25SL641.

Clock Configuration

The RA6W1/RA6W2 starts with 40Mhz of OSPI clock. and it can be up to 80Mhz after the PLL turn on. The OSPI_CLK frequencies can be set on the Clocks tab of the RA6W1/RA6W2 Configuration editor.

Pin Configuration

The following pins are available to connect to an external OSPI device:

• OQSPI_CLK: OSPI clock output
• OQSPI_CS: OSPI device select
• OQSPI_D0: Data 0 I/O
• OQSPI_D1: Data 1 I/O
• OQSPI_D2: Data 2 I/O
• OQSPI_D3: Data 3 I/O
• OQSPI_D4: Data 4 I/O
• OQSPI_D5: Data 5 I/O
• OQSPI_D6: Data 6 I/O
• OQSPI_D7: Data 7 I/O

Note

Data pins 4 to 7 could be used for GPIO when the RA6W1/RA6W2 uses QUAD flash model.

Usage Notes

Usage Notes for xSPI support

After R_OSPI_W_Open() completes successfully, the xSPI device contents are mapped to address 0x2A000000 and can be read like on-chip flash.

Auto-calibration

RA6W1/RA6W2 does not support this feature.

XiP Support

OSPI_W supports eXecute in Place (XiP) modes of operation. This can be used for read-only memory-mapped accesses to reduce overall read latency by skipping the command sequence in the xSPI transaction. Separate XiP enter and exit codes may be specified for either attached target device. Upon calling R_OSPI_W_XipEnter(), the associated memory region for the target device is switched to read-only mode and the enter code sent to the device. Calling R_OSPI_W_XipExit() will transmit the exit code and transition the memory region back to read-write access.

Only one flash device should be used after entering XiP mode. Once entered, XiP codes will be transmitted to all attached devices.

xSPI Commands

DOTF Support

Decryption-On-The-Fly feature is enabled if the RA6W1/RA6W2 is in secure-mode.

Limitations

Developers should be aware of the following limitations when using the OSPI_W driver:

OSPI_W

• All of APIs that related with OSPI_W should be located on the SRAM in RA6W1/RA6W2.

Examples

OSPI Flash:

Basic Example

This is a basic example of minimal use of the OSPI in an application with OctaFlash(QuadFlash).

void ospi_w_example(void)
{

    /* Open the OSPI instancee */
    err = R_OSPI_W_Open(&g_ospi_ctrl, &g_ospi_cfg);


    /* Read Chip ID*/
    read_chipID();

    /* Read Flash contents. it might be filled with all 0xff */
    read_flash(example_buffer, AT25SL641_TEST_ADDRESS, AT25SL641_TEST_LENGTH);

    /* erase flash */
    erase_flash(AT25SL641_TEST_ADDRESS, AT25SL641_TEST_LENGTH);

    /* write flash */
    for (uint32_t i = 0; i < AT25SL641_TEST_LENGTH; i++) {
        /* make ramp data */
        example_buffer[i] = (uint8_t)i;
    }
    write_flash(example_buffer, AT25SL641_TEST_ADDRESS, AT25SL641_TEST_LENGTH);

    /* Read back Flash contents. it might be filled with example_buffer */
    read_flash(example_check_buffer, AT25SL641_TEST_ADDRESS, AT25SL641_TEST_LENGTH);
    assert(memcmp((void*)example_buffer, (void*)example_check_buffer, AT25SL641_TEST_LENGTH) == 0);

    /* Auto erase */
    erase_flash_auto(AT25SL641_TEST_ADDRESS, AT25SL641_TEST_LENGTH);

    /* example END*/
    return ;
}

Reading Flash JEDEC ID Example (R_OSPI_W_DirectTransfer)

This is an example of using R_OSPI_W_DirectTransfer. it read the JEDEC ID of the flash.

/* Read chip ID
   flash control APIs should be located on the RAM */
BSP_PLACE_CODE_IN_RAM void read_chipID(void) {
    uint8_t chip_id[3];
    /* EVK runs under XIP */
    err = R_OSPI_W_Open(&g_ospi_ctrl, &g_ospi_cfg);
    assert(FSP_SUCCESS == err);

    GLOBAL_INT_DISABLE();       /* Once XipExit called, it cannot excute the ISR code on the flash */
    err = R_OSPI_W_XipExit(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);

    /* RA6W1/RA6W2 EVK flash model */
    transfer.command = AT25SL_READ_ID_CMD;
    transfer.address = 0x00;
    transfer.address_length = 0;
    transfer.data_u64 = 0; /*Clear buffer */
    transfer.data_length = AT25SL_ID_LENGTH;
    direction = SPI_FLASH_DIRECT_TRANSFER_DIR_READ;

    err = R_OSPI_W_DirectTransfer(&g_ospi_ctrl, &transfer, direction);
    assert(FSP_SUCCESS == err);

    memcpy((void*)chip_id, (void*)(&transfer.data),3);

    printf("RA6W1/RA6W2 EVK flash ID %02x %02x %02x\r\n", chip_id[0], chip_id[1], chip_id[2]);

    err = R_OSPI_W_XipEnter(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);
    GLOBAL_INT_RESTORE();
}

Reading Flash contents

Flash contents can be read out by memcpy. During automode, flash address are mapped at 0x2A000000.

BSP_PLACE_CODE_IN_RAM void read_flash(uint8_t* buffer, uint32_t address, uint32_t length)
{
    /* RA6W1/RA6W2 runs on the XIP it can read the flash contents through the memcpy() function */
    memcpy((void*)buffer, (void*)(address|OSPI_W_AUTOMODE_BASE_ADD), length);
}

Erasing flash Example (R_OSPI_W_Erase)

This is an example of erasing flash.

BSP_PLACE_CODE_IN_RAM void erase_flash(uint32_t address, uint32_t length)
{
    GLOBAL_INT_DISABLE();
    R_OSPI_W_XipExit(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_Erase(&g_ospi_ctrl, (uint8_t *)address, length);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_XipEnter(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);
    GLOBAL_INT_RESTORE();
}

Auto-erasing flash Example (R_OSPI_W_Erase)

The OSPI_W supports an auto-erase function. If the R_OSPI_W_XipExit() is not called before the R_OSPI_W_Erase(), it tries to erase in auto-mode, which means that there is no need to disable interrupts for flash erasing. When an interrupt occurs during the erase or the code is operated in another task, the OSPI_W automatically sends a suspend command. When the code operation is over, it sends a resume command to complete the erase. For using this feature, the flash configuration should be filled through the FSP.

BSP_PLACE_CODE_IN_RAM void erase_flash_auto(uint32_t address, uint32_t length)
{
    R_OSPI_W_Erase(&g_ospi_ctrl, (uint8_t *)address, length);
    assert(FSP_SUCCESS == err);
}

Writing data to flash (R_OSPI_W_Write)

This is an example of writing data to flash.

BSP_PLACE_CODE_IN_RAM void write_flash(uint8_t *buffer, uint32_t address, uint32_t length)
{
    GLOBAL_INT_DISABLE();
    R_OSPI_W_XipExit(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_Write(&g_ospi_ctrl, buffer, (uint8_t*)address,length);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_XipEnter(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);
    GLOBAL_INT_RESTORE();
}

Data Structures
struct	ospi_w_device_config_t
struct	ospi_w_device_read_instr_config_t
struct	ospi_w_device_erase_instr_config_t
struct	ospi_w_device_read_status_config_t
struct	ospi_w_device_write_enable_instr_config_t
struct	ospi_w_device_suspend_resume_instr_config_t
struct	ospi_w_xspi_command_set_t
struct	ospi_w_extended_cfg_t
struct	ospi_w_instance_ctrl_t

Enumerations
enum	ospi_w_device_clk_div
enum	ospi_w_device_bus_mode
enum	ospi_w_device_access_mode
enum	ospi_w_device_clk_mode
enum	ospi_w_device_io_dir
enum	ospi_w_device_io_value
enum	ospi_w_device_io4_7_value
enum	ospi_w_device_hready_mode
enum	ospi_w_device_sampling_edge
enum	ospi_w_device_read_pipe
enum	ospi_w_device_read_pipe_delay
enum	ospi_w_device_addr_size
enum	ospi_w_device_instruct_sz
enum	ospi_w_device_dummy_mode
enum	ospi_w_device_slew_rate
enum	ospi_w_device_drive_current
enum	ospi_w_device_extra_byte
enum	ospi_w_device_instr_mode
enum	ospi_w_device_number_t
enum	ospi_w_command_bytes_t
enum	ospi_w_command_interval_clocks_t
enum	ospi_w_command_cs_pullup_clocks_t
enum	ospi_w_command_cs_pulldown_clocks_t

---

Data Structure Documentation

ospi_w_device_config_t

struct ospi_w_device_config_t

OSPI_W configuration structure

Data Fields
ospi_w_device_clk_div	clk_div: 2	Clock divider value.
ospi_w_device_bus_mode	bus_mode: 3	Read bus mode.
ospi_w_device_access_mode	access_mode: 1	Access mode.
ospi_w_device_clk_mode	clock_mode: 1	Clock mode.
ospi_w_device_io_dir	io2_dir: 1	IO2 direction.
ospi_w_device_io_value	io2_value: 1	IO2 value.
ospi_w_device_io_dir	io3_dir: 1	IO3 direction.
ospi_w_device_io_value	io3_value: 1	IO3 value.
ospi_w_device_io_dir	io4_7_dir: 1	IO4-7 direction.
ospi_w_device_io4_7_value	io4_7_value: 4	IO4-7 value.
ospi_w_device_hready_mode	hready_mode: 1	HREADY mode.
ospi_w_device_sampling_edge	sampling_edge: 1	Sampling_edge.
ospi_w_device_read_pipe	read_pipe: 1	Read pipe setting.
ospi_w_device_read_pipe_delay	read_pipe_delay: 3	Read pipe delay value.
ospi_w_device_addr_size	address_size: 1	Flash address size.
ospi_w_device_dummy_mode	dummy_mode: 1	Dummy mode.
ospi_w_device_slew_rate	slew_rate: 2	Slew rate.
ospi_w_device_drive_current	drive_current: 2	Drive current.
ospi_w_device_manualmode_config_t	manualmode_config
ospi_w_device_automode_config_t	automode_config

ospi_w_device_read_instr_config_t

struct ospi_w_device_read_instr_config_t

OSPI_W read instruction configuration structure (auto access mode)

Data Fields
bool	enable	Enable read instruction
uint8_t	instr	Instruction code for Incremental Burst or Single read access. Also used when wrapping burst is not supported.
uint8_t	instr_extra_byte	Extra byte instruction. Usually the Mode Bits in Dual/Quad/ Octal SPI I/O instructions
ospi_w_device_bus_mode	instr_bus_mode	Bus mode during the instruction phase
ospi_w_device_bus_mode	addr_bus_mode	Bus mode during the address phase
ospi_w_device_bus_mode	extra_byte_bus_mode	Bus mode during the extra byte phase
ospi_w_device_bus_mode	dummy_bus_mode	Bus mode during the dummy phase
ospi_w_device_bus_mode	data_bus_mode	Bus mode during the data phase
ospi_w_device_extra_byte	extra_byte_cfg	Extra byte enable/disable
ospi_w_device_extra_byte_half	extra_byte_half_cfg	Enable/disable of extra byte half setting
uint8_t	dummy_bytes	The number of dummy bytes (0..32)
ospi_w_device_instr_mode	instr_mode
ospi_w_device_idle_state_duration	idle_state_duration

ospi_w_device_erase_instr_config_t

struct ospi_w_device_erase_instr_config_t

OSPI_W erase instruction configuration structure (auto access mode)

Data Fields
bool	enable	Enable erase instruction
uint8_t	instr	Erase instruction code
ospi_w_device_bus_mode	instr_bus_mode	Bus mode during the instruction phase
ospi_w_device_bus_mode	addr_bus_mode	Bus mode during the address phase
uint8_t	hclk_cycles	The number of AMBA AHB hclk cycles (0..15) without memory read requests before the controller can execute erase or erase resume instructions
uint8_t	cs_hi_cycles	The minimum number of QSPI bus clock cycles (0..31) that OSPI_CS remains high after the execution of write enable, erase, erase suspend and erase resume instructions.

ospi_w_device_read_status_config_t

struct ospi_w_device_read_status_config_t

OSPI_W read status instruction configuration structure (auto access mode)

Data Fields
bool	enable	Enable read status instruction
uint8_t	instr	Read status instruction code
ospi_w_device_bus_mode	instr_bus_mode	Bus mode during the instruction phase
ospi_w_device_bus_mode	receive_bus_mode	Bus mode during the receive status phase
ospi_w_device_bus_mode	dummy_bus_mode	Bus mode during the dummy bytes phase
uint8_t	busy_pos	The position of the Busy bit in the status register (0 - 7)
ospi_w_device_busy	busy_val	Busy status setting
uint8_t	read_stat_del	The minimum time distance between the read status instruction and previous erase or erase/resume instructions. 0: don't wait. The controller can read the memory status register immediately. 1..63 - the controller waits at least this number of QSPI_CLK cycles before reading the memory status register following the end of a previous erase or erase resume
ospi_w_device_read_status_reg_cnt	read_stat_reg_cnt
uint8_t	dummy_bytes	The number of dummy bytes (0..16)
ospi_w_device_read_status_dummy_val	dummy_val	Dummy bytes value

ospi_w_device_write_enable_instr_config_t

struct ospi_w_device_write_enable_instr_config_t

OSPI_W write enable instruction configuration structure (auto access mode)

Data Fields
bool	enable	Enable write enable instruction
uint8_t	instr	Write enable instruction code
ospi_w_device_bus_mode	instr_bus_mode	Bus mode during the instruction phase

ospi_w_device_suspend_resume_instr_config_t

struct ospi_w_device_suspend_resume_instr_config_t

OSPI_W erase suspend/resume instruction structure

Data Fields
bool	enable	Enable erase suspend/resume instruction
uint8_t	suspend_instr	Erase suspend instruction code
uint8_t	resume_instr	Erase resume instruction code
ospi_w_device_bus_mode	suspend_bus_mode	Bus mode during the erase suspend instruction phase
ospi_w_device_bus_mode	resume_bus_mode	Bus mode during the erase resume instruction phase
uint8_t	read_stat_del	The minimum time distance between the read status instruction and the previous erase or erase/resume instructions. 0: don't wait. The controller can read the memory status register immediately. 1..255 - the controller waits at least this number of OSPI_CLK cycles before reading the memory status register

ospi_w_xspi_command_set_t

struct ospi_w_xspi_command_set_t

Command set used for a protocol mode other than normal (1S-1S-1S) SPI.

Data Fields
spi_flash_protocol_t	protocol	Protocol mode associated with this command set.
ospi_w_command_bytes_t	command_bytes	Number of command bytes for each command code.
uint16_t	read_command	Read command.
uint16_t	page_program_command	Page program/write command.
uint16_t	write_enable_command	Command to enable write or erase, set to 0x00 to ignore.
uint16_t	status_command	Command to read the write status, set to 0x00 to ignore.
uint8_t	read_dummy_cycles	Dummy cycles to be inserted for read commands.
uint8_t	program_dummy_cycles	Dummy cycles to be inserted for page program commands.
uint8_t	status_dummy_cycles	Dummy cycles to be inserted for status read commands.
uint8_t	erase_command_list_length	Length of erase command list.
spi_flash_erase_command_t const *	p_erase_command_list	List of all erase commands and associated sizes.

ospi_w_extended_cfg_t

struct ospi_w_extended_cfg_t

OSPI_W Extended configuration.

Data Fields
ospi_w_device_number_t	channel	Device number to be used for memory device.
ospi_w_timing_setting_t const *	p_timing_settings	Memory-mapped timing settings.
ospi_w_xspi_command_set_t const *	p_xspi_command_set_list	Additional protocol command sets; if additional protocol commands set are not used set this to NULL.
uint8_t	xspi_command_set_list_length	Number of additional protocol command set defined.
uint8_t *	p_autocalibration_preamble_pattern_addr	OctaFlash memory address holding the preamble pattern.
uint8_t	data_latch_delay_clocks	Specify delay between OM_DQS and OM_DQS Strobe. Set to 0 to auto-calibrate. Typical value is 0x80.
ospi_w_device_config_t *	p_ospi_w_device_cfg	OSPI_W HW configuration.
ospi_w_device_read_instr_config_t *	p_read_instr_cfg	Automode read instruction configuration.
ospi_w_device_wrap_burst_instr_config_t *	p_wrap_burst_instr_cfg	Wrap burst instruction configuration.
ospi_w_device_read_status_config_t *	p_read_status_instr_cfg	Automode read status instruction configuration.
ospi_w_device_erase_instr_config_t *	p_erase_instr_cfg	Automode erase instruction configuration.
ospi_w_device_write_enable_instr_config_t *	p_write_enable_instr_cfg	Automode write enable instruction configuration.
ospi_w_device_suspend_resume_instr_config_t *	p_suspend_resume_instr_cfg	Automode suspend and resume instruction configuration.

ospi_w_instance_ctrl_t

struct ospi_w_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called

Data Fields
spi_flash_cfg_t const *	p_cfg	Pointer to initial configuration.
uint32_t	open	Whether or not driver is open.
spi_flash_protocol_t	spi_protocol	Current OSPI protocol selected.
ospi_w_device_number_t	channel	Device number to be used for memory device.
ospi_w_xspi_command_set_t const *	p_cmd_set	Command set for the active protocol mode.

Enumeration Type Documentation

ospi_w_device_clk_div

enum ospi_w_device_clk_div

OSPI_W clock divider

Enumerator
OSPI_W_DEVICE_CLK_DIV_1	divide by 1
OSPI_W_DEVICE_CLK_DIV_2	divide by 2
OSPI_W_DEVICE_CLK_DIV_4	divide by 4
OSPI_W_DEVICE_CLK_DIV_8	divide by 8

ospi_w_device_bus_mode

enum ospi_w_device_bus_mode

OSPI_W bus mode

Enumerator
OSPI_W_DEVICE_BUS_MODE_NOT_SET	Bus mode not set
OSPI_W_DEVICE_BUS_MODE_SINGLE	Bus mode in single mode
OSPI_W_DEVICE_BUS_MODE_DUAL	Bus mode in dual mode
OSPI_W_DEVICE_BUS_MODE_QUAD	Bus mode in quad mode
OSPI_W_DEVICE_BUS_MODE_OCTA	Bus mode in octa mode

ospi_w_device_access_mode

enum ospi_w_device_access_mode

OSPI_W memory access mode

Enumerator
OSPI_W_DEVICE_ACCESS_MODE_MANUAL	Manual Mode is selected
OSPI_W_DEVICE_ACCESS_MODE_AUTO	Auto Mode is selected

ospi_w_device_clk_mode

enum ospi_w_device_clk_mode

OSPI_W clock mode

Enumerator
OSPI_W_DEVICE_CLK_MODE_LOW	Mode 0: OSPI_SCK is low when OSPI_CS is high.
OSPI_W_DEVICE_CLK_MODE_HIGH	Mode 3: OSPI_SCK is high when OSPI_CS is high.

ospi_w_device_io_dir

enum ospi_w_device_io_dir

OSPI_W pad direction

Enumerator
OSPI_W_DEVICE_IO_DIR_AUTO_SEL	The OQSPI pad is determined by the controller.
OSPI_W_DEVICE_IO_DIR_OUTPUT	The OQSPI pad is output

ospi_w_device_io_value

enum ospi_w_device_io_value

OSPI_W IO2/IO3 pad value

ospi_w_device_io4_7_value

enum ospi_w_device_io4_7_value

OSPI_W IO4-7 pads values

ospi_w_device_hready_mode

enum ospi_w_device_hready_mode

OSPI_W HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers

Enumerator
OSPI_W_DEVICE_HREADY_MODE_WAIT	Adds wait states via hready signal when an accessing the OSPIC_WRITEDATA, OSPIC_READDATA and OSPIC_DUMMYDATA registers.
OSPI_W_DEVICE_HREADY_MODE_NO_WAIT	Don't add wait states via the HREADY signal

ospi_w_device_sampling_edge

enum ospi_w_device_sampling_edge

OSPI_W clock edge setting for the sampling of the incoming data when the read pipe is disabled

Enumerator
OSPI_W_DEVICE_SAMPLING_EDGE_POS	The incoming data sampling is triggered by the positive edge of OSPI_W clock signal
OSPI_W_DEVICE_SAMPLING_EDGE_NEG	The incoming data sampling is triggered by the negative edge of OSPI_W clock signal

ospi_w_device_read_pipe

enum ospi_w_device_read_pipe

OSPI_W read pipe setting When read pipe is disabled the sampling clock is determined by ospi_w_device_sampling_edge while when is enabled by ospi_w_device_read_pipe_delay. In ASIC is always recommended to enable read pipe and set the ospi_w_device_read_pipe_delay to the optimal value.

ospi_w_device_read_pipe_delay

enum ospi_w_device_read_pipe_delay

OSPI_W Read pipe clock delay in relation to the falling edge of OSPI_SCK

ospi_w_device_addr_size

enum ospi_w_device_addr_size

OSPI_W memory address size

Enumerator
OSPI_W_DEVICE_ADDR_SIZE_24	24 bits address
OSPI_W_DEVICE_ADDR_SIZE_32	32 bits address

ospi_w_device_instruct_sz

enum ospi_w_device_instruct_sz

OSPI_W number of bytes of the instruction code in automode

Enumerator
OSPI_W_DEVICE_INSTRUCT_SZ_1_BYTE	The instruction code is one byte
OSPI_W_DEVICE_INSTRUCT_SZ_2_BYTES	The instruction code is two bytes. The second byte equals to the inverse value of the first byte

ospi_w_device_dummy_mode

enum ospi_w_device_dummy_mode

OSPI_W clock cycle where the bus switches to Hi-Z during the transmission of dummy bytes

Enumerator
OSPI_W_DEVICE_DUMMY_MODE_LAST_CLK	Switch to Hi-Z on the last clock
OSPI_W_DEVICE_DUMMY_MODE_LAST_2_CLK	Switch to Hi-Z on the last two clocks

ospi_w_device_slew_rate

enum ospi_w_device_slew_rate

OSPI_W pads slew rate control

Enumerator
OSPI_W_DEVICE_SLEW_RATE_0	Rise = 1.7 V/ns, Fall = 1.9 V/ns (weak)
OSPI_W_DEVICE_SLEW_RATE_1	Rise = 2.0 V/ns, Fall = 2.3 V/ns
OSPI_W_DEVICE_SLEW_RATE_2	Rise = 2.3 V/ns, Fall = 2.6 V/ns
OSPI_W_DEVICE_SLEW_RATE_3	Rise = 2.4 V/ns, Fall = 2.7 V/ns (strong)

ospi_w_device_drive_current

enum ospi_w_device_drive_current

OSPI_W pads drive current

Enumerator
OSPI_W_DEVICE_DRIVE_CURRENT_4	4 mA
OSPI_W_DEVICE_DRIVE_CURRENT_8	8 mA
OSPI_W_DEVICE_DRIVE_CURRENT_12	12 mA
OSPI_W_DEVICE_DRIVE_CURRENT_16	16 mA

ospi_w_device_extra_byte

enum ospi_w_device_extra_byte

OSPI_W extra byte setting in auto access mode

Enumerator
OSPI_W_DEVICE_EXTRA_BYTE_DISABLE	Don't send the extra byte
OSPI_W_DEVICE_EXTRA_BYTE_ENABLE	Send the extra byte

ospi_w_device_instr_mode

enum ospi_w_device_instr_mode

OSPI_W Instruction mode in auto access mode

Enumerator
OSPI_W_DEVICE_INSTR_MODE_SEND_ANYTIME	Transmit instruction at any burst access
OSPI_W_DEVICE_INSTR_MODE_SEND_ONCE	Transmit instruction only in the first access after the selection of Auto Mode

ospi_w_device_number_t

enum ospi_w_device_number_t

Enumerator
OSPI_W_DEVICE_NUMBER_0	Device connected to Chip-Select 0.

ospi_w_command_bytes_t

enum ospi_w_command_bytes_t

Enumerator
OSPI_W_COMMAND_BYTES_1	Command codes are 1 byte long.
OSPI_W_COMMAND_BYTES_2	Command codes are 2 bytes long.

ospi_w_command_interval_clocks_t

enum ospi_w_command_interval_clocks_t

Enumerator
OSPI_W_COMMAND_INTERVAL_CLOCKS_1	1 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_2	2 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_3	3 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_4	4 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_5	5 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_6	6 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_7	7 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_8	8 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_9	9 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_10	10 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_11	11 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_12	12 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_13	13 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_14	14 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_15	15 interval clocks
OSPI_W_COMMAND_INTERVAL_CLOCKS_16	16 interval clocks

ospi_w_command_cs_pullup_clocks_t

enum ospi_w_command_cs_pullup_clocks_t

Enumerator
OSPI_W_COMMAND_CS_PULLUP_CLOCKS_NO_EXTENSION	CS asserting No extension.
OSPI_W_COMMAND_CS_PULLUP_CLOCKS_1	CS asserting Extend 1 cycle.

ospi_w_command_cs_pulldown_clocks_t

enum ospi_w_command_cs_pulldown_clocks_t

Enumerator
OSPI_W_COMMAND_CS_PULLDOWN_CLOCKS_NO_EXTENSION	CS negating No extension.
OSPI_W_COMMAND_CS_PULLDOWN_CLOCKS_1	CS negating Extend 1 cycle.

Function Documentation

R_OSPI_W_Open()

fsp_err_t R_OSPI_W_Open	(	spi_flash_ctrl_t *const	p_ctrl,
		spi_flash_cfg_t const *const	p_cfg
	)

Open the OSPI driver module. After the driver is open, the OSPI can be accessed like internal flash memory.

Implements spi_flash_api_t::open.

Example:

    /* Open the OSPI instancee */
    err = R_OSPI_W_Open(&g_ospi_ctrl, &g_ospi_cfg);

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	The parameter p_ctrl or p_cfg is NULL.
FSP_ERR_ALREADY_OPEN	Driver has already been opened with the same p_ctrl.
FSP_ERR_INVALID_ARGUMENT	Attempting to open the driver with an invalid SPI protocol for OctaRAM.

R_OSPI_W_Close()

fsp_err_t R_OSPI_W_Close

(

spi_flash_ctrl_t *const

p_ctrl

)

Close the OSPI driver module.

Implements spi_flash_api_t::close.

Return values

FSP_SUCCESS	Configuration was successful.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_W_DirectWrite()

fsp_err_t R_OSPI_W_DirectWrite	(	spi_flash_ctrl_t *const	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

Writes raw data directly to the OctaFlash. API not supported. Use R_OSPI_W_DirectTransfer

Implements spi_flash_api_t::directWrite.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI.

R_OSPI_W_DirectRead()

fsp_err_t R_OSPI_W_DirectRead	(	spi_flash_ctrl_t *const	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the OctaFlash. API not supported. Use R_OSPI_W_DirectTransfer.

Implements spi_flash_api_t::directRead.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI.

R_OSPI_W_DirectTransfer()

fsp_err_t R_OSPI_W_DirectTransfer	(	spi_flash_ctrl_t *const	p_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the OctaFlash.

Implements spi_flash_api_t::directTransfer.

Example:

/* Read chip ID
   flash control APIs should be located on the RAM */
BSP_PLACE_CODE_IN_RAM void read_chipID(void) {
    uint8_t chip_id[3];
    /* EVK runs under XIP */
    err = R_OSPI_W_Open(&g_ospi_ctrl, &g_ospi_cfg);
    assert(FSP_SUCCESS == err);

    GLOBAL_INT_DISABLE();       /* Once XipExit called, it cannot excute the ISR code on the flash */
    err = R_OSPI_W_XipExit(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);

    /* RA6W1/RA6W2 EVK flash model */
    transfer.command = AT25SL_READ_ID_CMD;
    transfer.address = 0x00;
    transfer.address_length = 0;
    transfer.data_u64 = 0; /*Clear buffer */
    transfer.data_length = AT25SL_ID_LENGTH;
    direction = SPI_FLASH_DIRECT_TRANSFER_DIR_READ;

    err = R_OSPI_W_DirectTransfer(&g_ospi_ctrl, &transfer, direction);
    assert(FSP_SUCCESS == err);

    memcpy((void*)chip_id, (void*)(&transfer.data),3);

    printf("RA6W1/RA6W2 EVK flash ID %02x %02x %02x\r\n", chip_id[0], chip_id[1], chip_id[2]);

    err = R_OSPI_W_XipEnter(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);
    GLOBAL_INT_RESTORE();
}

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_INVALID_ARGUMENT	The parameters are wrong.

R_OSPI_W_SpiProtocolSet()

fsp_err_t R_OSPI_W_SpiProtocolSet	(	spi_flash_ctrl_t *const	p_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol.

Implements spi_flash_api_t::spiProtocolSet.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI. Once the RA6W1/RA6W2 is running, it already be in automode by Booter.

R_OSPI_W_XipEnter()

fsp_err_t R_OSPI_W_XipEnter

(

spi_flash_ctrl_t *const

p_ctrl

)

Enters XIP (execute in place) mode.

Note

It need to enable the interrupt if it is disabled before.

Implements spi_flash_api_t::xipEnter.

Return values

FSP_SUCCESS	XiP mode was entered successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_UNSUPPORTED	XiP support is not enabled.

R_OSPI_W_XipExit()

fsp_err_t R_OSPI_W_XipExit

(

spi_flash_ctrl_t *const

p_ctrl

)

Exits XIP (execute in place) mode.

Note

Once R_OSPI_W_XipExit called, it cannot excute the ISR code on the flash. So, it need to disable all interrupt right before this function.

Implements spi_flash_api_t::xipExit.

Return values

FSP_SUCCESS	XiP mode was entered successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_UNSUPPORTED	XiP support is not enabled.
FSP_ERR_INVALID_MODE	Unsupport flash mode.

R_OSPI_W_Write()

fsp_err_t R_OSPI_W_Write	(	spi_flash_ctrl_t *const	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Example:

BSP_PLACE_CODE_IN_RAM void write_flash(uint8_t *buffer, uint32_t address, uint32_t length)
{
    GLOBAL_INT_DISABLE();
    R_OSPI_W_XipExit(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_Write(&g_ospi_ctrl, buffer, (uint8_t*)address,length);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_XipEnter(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);
    GLOBAL_INT_RESTORE();
}

• Return values

  FSP_SUCCESS	The flash was programmed successfully.
  FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
  FSP_ERR_NOT_OPEN	Driver is not opened.
  FSP_ERR_INVALID_SIZE	Insufficient space remaining in page or write length is not a multiple of CPU access size when not using the DMAC.
  FSP_ERR_DEVICE_BUSY	Another Write/Erase transaction is in progress.
  FSP_ERR_WRITE_FAILED	Write operation failed.
  FSP_ERR_INVALID_ADDRESS	Destination or source is not aligned to CPU access alignment when not using the DMAC.

R_OSPI_W_Erase()

fsp_err_t R_OSPI_W_Erase	(	spi_flash_ctrl_t *const	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE. If it was opened with auto-erase configuration, it could be called without XIP_Exit() function. Implements spi_flash_api_t::erase.

Example:

BSP_PLACE_CODE_IN_RAM void erase_flash(uint32_t address, uint32_t length)
{
    GLOBAL_INT_DISABLE();
    R_OSPI_W_XipExit(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_Erase(&g_ospi_ctrl, (uint8_t *)address, length);
    assert(FSP_SUCCESS == err);

    R_OSPI_W_XipEnter(&g_ospi_ctrl);
    assert(FSP_SUCCESS == err);
    GLOBAL_INT_RESTORE();
}

BSP_PLACE_CODE_IN_RAM void erase_flash_auto(uint32_t address, uint32_t length)
{
    R_OSPI_W_Erase(&g_ospi_ctrl, (uint8_t *)address, length);
    assert(FSP_SUCCESS == err);
}

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, byte_count doesn't match an erase size defined in spi_flash_cfg_t, or byte_count is set to 0.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.
FSP_ERR_WRITE_FAILED	Write operation failed.
FSP_ERR_INVALID_ARGUMENT	The parameters are wrong.

R_OSPI_W_StatusGet()

fsp_err_t R_OSPI_W_StatusGet	(	spi_flash_ctrl_t *const	p_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_W_BankSet()

fsp_err_t R_OSPI_W_BankSet	(	spi_flash_ctrl_t *const	p_ctrl,
		uint32_t	bank
	)

Selects the bank to access. Use ospi_w_bank_select_t as the bank value.

Implements spi_flash_api_t::bankSet.

Return values

FSP_ERR_UNSUPPORTED

This function is unsupported.

R_OSPI_W_AutoCalibrate()

fsp_err_t R_OSPI_W_AutoCalibrate

(

spi_flash_ctrl_t *const

p_ctrl

)

AutoCalibrate the OSPI_W DS signal.

Implements spi_flash_api_t::autoCalibrate.

Return values

FSP_ERR_UNSUPPORTED

Autocalibration support is not enabled.