Functions
fsp_err_t	R_FSP_VersionGet (fsp_pack_version_t *const p_version)

void	Default_Handler (void)

void	Reset_Handler (void)

BSP_WEAK_REFERENCE __NO_RETURN void	_exit (int __status)

void	SystemInit (void)

void	R_BSP_WarmStart (bsp_warm_start_event_t event)

uint32_t	R_BSP_SourceClockHzGet (fsp_priv_source_clock_t clock)

void	R_BSP_SourceClockHzSet (fsp_priv_source_clock_t clock, uint32_t freq)

__STATIC_FORCEINLINE IRQn_Type	R_FSP_CurrentIrqGet (void)

__STATIC_INLINE ahb_clk_div_t	bsp_clock_ahb_div_get (void)
	Get the Sys_clk divider for HCLK. More...

__STATIC_INLINE uint32_t	R_FSP_SystemClockHzGet (fsp_priv_clock_t clock)

__STATIC_INLINE uint32_t	R_FSP_ClockDividerGet (uint32_t ckdivcr)

__STATIC_INLINE bsp_unique_id_t const *	R_BSP_UniqueIdGet (void)

__STATIC_INLINE void	R_BSP_FlashCacheDisable (void)

__STATIC_INLINE void	R_BSP_FlashCacheEnable (void)

void *	fast_memcpy (void dest, const void src, size_t n)

void *	fast_memset (void *b, int c, size_t len)

BSP_PLACE_CODE_IN_RAM void	R_BSP_SoftwareDelay (uint32_t delay, bsp_delay_units_t units)

fsp_err_t	R_BSP_GroupIrqWrite (bsp_grp_irq_t irq, void(*p_callback)(bsp_grp_irq_t irq))

fsp_err_t	R_BSP_GroupNmiWrite (void(p_callback)(const uint32_t p_exception_args))

BSP_WEAK_REFERENCE void	NMI_HandlerC (unsigned long *exception_args)

void	bsp_pd_init (void)

BSP_PLACE_CODE_IN_RAM void	bsp_pd_use (uint32_t pd_id)

BSP_PLACE_CODE_IN_RAM void	bsp_pd_unuse (uint32_t pd_id)

BSP_PLACE_CODE_IN_RAM bool	bsp_pd_used_check (uint32_t pd_id)

bool	bsp_pd_is_up_check (uint32_t pd_id)

BSP_PLACE_CODE_IN_RAM void	bsp_pd_enable (uint32_t pd_id)

BSP_PLACE_CODE_IN_RAM void	bsp_pd_disable (uint32_t pd_id)

__STATIC_INLINE bool	R_BSP_DMAC_IsEdgeSensitiveTrigger (bsp_dmac_trig_t trigger)

__STATIC_INLINE void	R_BSP_DMAC_ChannelInterruptsEnable (uint8_t channel)

__STATIC_INLINE void	R_BSP_DMAC_ChannelInterruptsDisable (uint8_t channel)

__STATIC_INLINE void	R_BSP_PeripheralFreeze (bsp_freeze_peripheral_t peripheral)

__STATIC_INLINE bool	R_BSP_IsPeripheralFrozen (bsp_freeze_peripheral_t peripheral)

__STATIC_INLINE void	R_BSP_PeripheralUnFreeze (bsp_freeze_peripheral_t peripheral)

void	R_BSP_RetainedIoRecovery (uint16_t clear)

bool	R_BSP_RetainedIoExecute (void)

__STATIC_FORCEINLINE void	bsp_otpc_set_speed (bsp_otpc_clk_freq_t clk_speed)

__STATIC_FORCEINLINE volatile uint32_t *	bsp_prv_otpc_addr (uint32_t cell_offset)

__STATIC_FORCEINLINE void	bsp_prv_otp_mode_set (bsp_otpc_mode_t mode)

__STATIC_FORCEINLINE void	bsp_prv_otp_mode_wait_until_set (bsp_otpc_mode_t mode)

__STATIC_FORCEINLINE void	bsp_otpc_wait_while_busy_programming (void)

void	bsp_otp_init (void)

void	bsp_otp_timings_set (uint32_t sysclk_freq_MHz)

void	bsp_otp_mode_set (uint32_t mode)

uint32_t	bsp_otp_word_read (uint32_t cell_offset)

void	bsp_otp_read (uint32_t *p_data, uint32_t cell_offset, uint32_t num_words)

uint32_t	bsp_otp_word_prog (uint32_t data, uint32_t cell_offset)

void	bsp_otp_prog (const uint32_t *p_data, uint32_t cell_offset, uint32_t num_words)

bool	bsp_otp_prog_and_verify (const uint32_t *p_data, uint32_t cell_offset, uint32_t num_words)

uint32_t	bsp_otp_lock (uint8_t cell_region)

uint32_t	bsp_otp_get_lock_region (void)

void	bsp_otp_close (void)

void	bsp_prv_pd_masks_get (bsp_power_domain_t power_domain, uint32_t sleep_mask, uint32_t is_up_mask)
	Get the SLEEP/IS_UP register-field masks of a power domain. More...

BSP_PLACE_CODE_IN_RAM void	SystemWakeupSourceUpdate (void)

BSP_PLACE_CODE_IN_RAM bsp_wakeup_source_mask_t	R_BSP_WakeupSourceGet (void)

void	R_BSP_WakeupSourceClear (bool clear)

bsp_io_wakeup_pin_t	R_BSP_WakeupSourcePinGet (void)

void	R_BSP_WakeupSourcePinClear (void)

void	R_BSP_WakeupSourcePinSet (bsp_io_wakeup_pin_t pin, bsp_io_wakeup_edge_t edge)

void	R_BSP_WakeupSourcePinSetRetained (bsp_io_wakeup_pin_t pin, bsp_io_wakeup_edge_t edge)

void	R_BSP_WakeupSourcePinUnSet (bsp_io_wakeup_pin_t pin)

bsp_io_wakeup_pin_t	bsp_prv_port_pin_to_wakeup_gpio (bsp_io_port_pin_t port_pin)
	Convert PORT_PIN to WAKEUP_GPIO. More...

bsp_io_port_pin_t	bsp_prv_wakeup_pin_to_port_pin (bsp_io_wakeup_pin_t wakeup_gpio)
	Convert WAKEUP_GPIO to PORT_PIN. More...

BSP_PLACE_CODE_IN_RAM void	R_BSP_RetainedMemFlagSet (void)

BSP_PLACE_CODE_IN_RAM void	R_BSP_RetainedMemFlagClear (void)

BSP_PLACE_CODE_IN_RAM uint32_t	R_BSP_RetainedMemFlagGet (void)

Detailed Description

The BSP is responsible for getting the MCU from reset to the user's application. Before reaching the user's application, the BSP sets up the stacks, heap, clocks, interrupts, C runtime environment, and stack monitor.

BSP Features
BSP Clock Configuration
System Interrupts
Group Interrupts
External and Peripheral Interrupts
Error Logging
BSP Weak Symbols
Warm Start Callbacks
Sub Clock Stabilization Wait Callback
C Runtime Initialization
Register Protection
ID Codes
TrustZone Security Attribution Registers
Software Delay
Trignometric Function
Digital Signal Processing with 32-bit Multiply-Accumulator
Octal-SPI Clock Update
Limited D-Cache Support
Non-Cacheable Buffer Placement Example
Configuration

Overview

BSP Features

BSP Clock Configuration

All system clocks are set up during BSP initialization based on the settings in bsp_clock_cfg.h. These settings are derived from clock configuration information provided from the FSP Configuration editor Clocks tab.

Clock configuration is performed prior to initializing the C runtime environment to speed up the startup process, as it is possible to start up on a relatively slow clock.
The BSP implements the required delays to allow the selected clock to stabilize.
The BSP will configure the CMSIS SystemCoreClock variable after clock initialization with the current system clock frequency.

System Interrupts

As RA for Wireless (RAFW)MCUs are based on the Arm Cortex-M architecture, the NVIC Nested Vectored Interrupt Controller (NVIC) handles exceptions and interrupt configuration, prioritization and interrupt masking. In the Arm architecture, the NVIC handles exceptions. Some exceptions are known as System Exceptions. System exceptions are statically located at the "top" of the vector table and occupy vector numbers 1 to 15. Vector zero is reserved for the MSP Main Stack Pointer (MSP). The remaining 15 system exceptions are shown below:

Reset
NMI
Cortex-M33 Hard Fault Handler
Cortex-M33 MPU Fault Handler
Cortex-M33 Bus Fault Handler
Cortex-M33 Usage Fault Handler
Reserved
Reserved
Reserved
Reserved
Cortex-M33 SVCall Handler
Cortex-M33 Debug Monitor Handler
Reserved
Cortex-M33 PendSV Handler
Cortex-M33 SysTick Handler

NMI and Hard Fault exceptions are enabled out of reset and have fixed priorities. Other exceptions have configurable priorities and some can be disabled.

Group Interrupts

Group interrupt is the term used to describe the various sources that can trigger the Non-Maskable Interrupt (NMI), on the devices that have multiple NMI sources. If supported by the HW, when an NMI occurs the NMI Handler examines the ICU_NMISR_REG (status register) to determine the source of the interrupt. NMI interrupts take precedence over all interrupts, are usable only as CPU interrupts, and cannot activate the RAFW peripherals Data Transfer Controller (DTC) or Direct Memory Access Controller (DMAC).

Possible group interrupt sources include:

VBAT monitor Interrupt
NMI pin
TrustZone Filter Error A user may enable notification for one or more group interrupts by registering a callback using the BSP API function R_BSP_GroupIrqWrite(). When an NMI interrupt occurs, the NMI handler checks to see if there is a callback registered for the cause of the interrupt and if so calls the registered callback function.

External and Peripheral Interrupts

User configurable interrupts begin with slot 16. These may be external, or peripheral generated interrupts.

Although the number of available slots for the NVIC interrupt vector table may seem small, the BSP defines up to 512 events that are capable of generating an interrupt. By using Event Mapping, the BSP maps user-enabled events to NVIC interrupts, on specific devices. For an RRQ431 SoC, only 60 of these events may be active at any one time, but the user has flexibility by choosing which events generate the active event.

By allowing the user to select only the events they are interested in as interrupt sources, we are able to provide an interrupt service routine that is fast and event specific.

On other microcontrollers a standard NVIC interrupt vector table might contain a single vector entry for the UART (Serial Communications Interface) peripheral. The interrupt service routine for this would have to check a status register for the 'real' source of the interrupt. In the RAFW implementation there is a vector entry for each of the SCI0 events that we are interested in.

BSP Weak Symbols

You might wonder how the BSP is able to place ISR addresses in the NVIC table without the user having explicitly defined one. All that is required by the BSP is that the interrupt event be given a priority.

This is accomplished through the use of the 'weak' attribute. The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. A weak symbol is one that can be overridden by an accompanying strong reference with the same name. When the BSP declares a function as weak, user code can define the same function and it will be used in place of the BSP function. By defining all possible interrupt sources as weak, the vector table can be built at compile time and any user declarations (strong references) will be used at runtime.

Weak symbols are supported for ELF targets and also for a.out targets when using the GNU assembler and linker.

Note that in CMSIS system.c, there is also a weak definition (and a function body) for the Warm Start callback function R_BSP_WarmStart(). Because this function is defined in the same file as the weak declaration, it will be called as the 'default' implementation. The function may be overridden by the user by copying the body into their user application and modifying it as necessary. The linker identifies this as the 'strong' reference and uses it.

Warm Start Callbacks

As the BSP is in the process of bringing up the board out of reset, there are three points where the user can request a callback. These are defined as the 'Pre Clock Init', 'Post Clock Init' and 'Post C' warm start callbacks.

As described above, this function is already weakly defined as R_BSP_WarmStart(), so it is a simple matter of redefining the function or copying the existing body from CMSIS system.c into the application code to get a callback. R_BSP_WarmStart() takes an event parameter of type bsp_warm_start_event_t which describes the type of warm start callback being made.

This function is not enabled/disabled and is always called for both events as part of the BSP startup. Therefore it needs a function body, which will not be called if the user is overriding it. The function body is located in system.c. To use this function just copy this function into your own code and modify it to meet your needs.

\[WIP\] Sub Clock Stabilization Wait Callback

When Sub-Clock oscillator is populated in the application, the BSP startup code waits for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. Enabling the watchdog (IWDT or WDT) timer with Auto start mode in an application using Sub-clock may cause system to generate Reset or NMI interrupt before reaching the application code if watchdog refresh register is not updated in the configured refresh Window. To overcome this problem a weakly defined callback R_BSP_SubClockStabilizeWait() can be overridden. Redefine the callback function in the application code and add code to update the watchdog refresh register. R_BSP_SubClockStabilizeWait() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.

\[WIP\] Sub Clock Stabilization Wait After Reset callback

After Power-On-Reset, the BSP startup code may have to wait for some time(sub-clock stabilization time) to allow Sub-clock to stabilize. This can cause problem to RTC in case device is to be reset frequently. If Sub-Clock registers are not initialized during a reset, BSP actually does not have to wait for Sub-clock to stabilize. To overcome this problem, a weakly defined callback R_BSP_SubClockStabilizeWaitAfterReset() is provided. Reimplement the callback function in the application code to determine whether BSP has to wait for stabilization time based on the current reset type. R_BSP_SubClockStabilizeWaitAfterReset() takes a parameter delay of type uint32_t which describes the time in milliseconds required to stabilize the sub-clock.

C Runtime Initialization

This BSP configuration allows the user to skip the FSP C runtime initialization code by setting the "C Runtime Initialization" to "Disabled" on the BSP tab of the FSP Configuration editor. Disabling this option is useful in cases where a non-standard linker script is being used or other modifications to the runtime initialization are desired. If this macro is disabled, the user must use the 'Post Clock Init' event from the warm start (described above) to run their own runtime initialization code.

Heap Allocation

The relatively low amount of on-chip SRAM available and lack of memory protection in an MCU means that heap use must be very carefully controlled to avoid memory leaks, overruns and attempted overallocation. Further, many RTOSes provide their own dynamic memory allocation system. For these reasons the default heap size is set at 0 bytes, effectively disabling dynamic memory. If it is required for an application setting a positive value to the "Heap size (bytes)" option in the RAFW Common configurations on the BSP tab will allocate a heap.

Note: When using printf/sprintf (and other variants) to output floating point numbers a heap is required. A minimum size of 0x1000 (4096) bytes is recommended when starting development in this case.

Error Logging

When error logging is enabled, the error logging function can be redefined on the command line by defining FSP_ERROR_LOG(err) to the desired function call. The default function implementation is FSP_ERROR_LOG(err)=fsp_error_log(err, FILE, LINE). This implementation uses the predefined macros FILE and LINE to help identify the location where the error occurred. Removing the line from the function call can reduce code size when error logging is enabled. Some compilers may support other predefined macros like FUNCTION, which could be helpful for customizing the error logger.

TrustZone Security Attribution Registers

On devices that support TrustZone, Security Attribution Registers for modules used in the Secure project are configured to allow Secure access only as part of the startup code of the Secure project. This logic is skipped for Flat projects.

Software Delay

Implements a blocking software delay. A delay can be specified in microseconds, milliseconds or seconds. The delay is implemented based on the system clock rate.

    /* Delay at least 1 second. Depending on the number of wait states required for the region of memory
     * that the software_delay_loop has been linked in this could take longer. The default is 4 cycles per loop.
     * This can be modified by redefining DELAY_LOOP_CYCLES. BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS,
     * and BSP_DELAY_UNITS_MICROSECONDS can all be used with R_BSP_SoftwareDelay. */
    R_BSP_SoftwareDelay(1, BSP_DELAY_UNITS_SECONDS);

\[WIP\] Digital Signal Processing With 32-bit Multiply-Accumulator

Implements DSP (digital signal processing) functions via MACL (32-bit Multiply-Accumulator) hardware. These functions will support CMSIS DSP APIs to perform the calculation, the activation of MACL can be controlled by stack MACL (rm_cmsis_dsp) in the FSP Configuration editor.

When stack MACL (rm_cmsis_dsp) is added, the CMSIS DSP APIs will generate normal functions which overrides weak functions of Arm and use hardware for calculating. When stack MACL (rm_cmsis_dsp) is not added, CMSIS DSP APIs will perform the calculation by using software.

For examples, how to use the CMSIS DSP APIs refer to the link: https://github.com/ARM-software/CMSIS-DSP/tree/main/Examples/ARM.

CMSIS APIs supported by MACL list:

No	CMSIS DSP API	MACL BSP API	Description
1	arm_mult_q31	R_BSP_MaclMulQ31	Q31 vector multiplication
2	arm_scale_q31	R_BSP_MaclScaleQ31	Multiplies a Q31 vector by a scalar
3	arm_mat_mult_q31	R_BSP_MaclMatMultQ31	Q31 matrix multiplication
4	arm_mat_vec_mult_q31	R_BSP_MaclMatVecMulQ31	Q31 matrix and vector multiplication
5	arm_mat_scale_q31	R_BSP_MaclMatScaleQ31	Q31 matrix scaling
6	arm_biquad_cascade_df1_q31	R_BSP_MaclBiquadCsdDf1Q31	Processing function for the Q31 Biquad cascade filter
7	arm_conv_partial_q31	R_BSP_MaclConvPartialQ31	Partial convolution of Q31 sequences
8	arm_conv_q31	R_BSP_MaclConvQ31	Convolution of Q31 sequences
9	arm_correlate_q31	R_BSP_MaclCorrelateQ31	Correlation of Q31 sequences
10	arm_fir_decimate_q31	R_BSP_MaclFirDecimateQ31	Processing function for the Q31 FIR decimator
11	arm_fir_interpolate_q31	R_BSP_MaclFirInterpolateQ31	Processing function for the Q31 FIR interpolator
12	arm_fir_q31	R_BSP_MaclFirQ31	Processing function for Q31 FIR filter
13	arm_fir_sparse_q31	R_BSP_MaclFirSparseQ31	Processing function for the Q31 sparse FIR filter
14	arm_lms_norm_q31	R_BSP_MaclLmsNormQ31	Processing function for Q31 normalized LMS filter
15	arm_lms_q31	R_BSP_MaclLmsQ31	Processing function for Q31 LMS filter

Note: Refer to the MCU hardware user's manual or datasheet to determine if it has MACL support.

Critical Section Macros

Implements a critical section. Some MCUs (MCUs with the BASEPRI register) support allowing high priority interrupts to execute during critical sections. On these MCUs, interrupts with priority less than or equal to BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION are not serviced in critical sections. Interrupts with higher priority than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION still execute in critical sections.

    FSP_CRITICAL_SECTION_DEFINE;
    /* Store the current interrupt posture. */
    FSP_CRITICAL_SECTION_ENTER;
    /* Interrupts cannot run in this section unless their priority is less than BSP_CFG_IRQ_MASK_LEVEL_FOR_CRITICAL_SECTION. */
    /* Restore saved interrupt posture. */
    FSP_CRITICAL_SECTION_EXIT;

\[WIP\] Sealing the Main Stack (TrustZone Secure Projects)

In TrustZone secure projects, the BSP seals the main stack by placing the value 0xFEF5EDA5 above the stack top. For more information, refer to section 3.5 "Sealing a Stack" in "Secure software guidelines for ARMv8-M": https://developer.arm.com/documentation/100720/0300.

\[WIP\] Non-Cacheable Buffer Placement Example

The predefined non-cacheable regions configured by the MPU when D-Cache is enabled can be used to contain data that should not be cached, ensuring data coherency for that data. To use the predefined non-cacheable regions, place the data into the corresponding non-cacheable section defined by the linker script for the chosen toolchain. The predefined non-cacheable regions are not initialized by the BSP.

Use one of the .nocache sections to place non-cacheable data.

uint8_t uncached_uninitialized_buffer_sram[1024] BSP_PLACE_IN_SECTION(".nocache");

Section names differ by data region and compiler. Names predefined by the BSP are shown below.

Region	Name (GCC, IAR, LLVM)	Name (AC6)
SRAM	`.nocache`	`.bss.nocache`
SDRAM	`.nocache_sdram`	`.bss.nocache_sdram`

Configuration

The BSP is heavily data driven with most features and functionality being configured based on the content from configuration files. Configuration files represent the settings specified by the user and are generated when the project is built and/or when the Generate Project Content button is clicked in the FSP Configuration editor.

Build Time Configurations for fsp_common

The following build time configurations are defined in fsp_cfg/bsp/bsp_cfg.h:

Configuration	Options	Default	Description
Main stack size (bytes)	Value must be an integer multiple of 8 and between 8 and 0xFFFFFFFF	0x400	Set the size of the main program stack. NOTE: This entry is for the main stack. When using an RTOS, thread stacks can be configured in the properties for each thread.
Heap size (bytes)	Value must be 0 or an integer multiple of 8 between 8 and 0xFFFFFFFF.	0	The main heap is disabled by default. Set the heap size to a positive integer divisible by 8 to enable it. A minimum of 4K (0x1000) is recommended if standard library functions are to be used.
NVM size (bytes)	Value must be 0x180000.	0x180000	The size of the NVM is 1536kB for RRQ431XX. Cannot be modified currently.
Parameter checking	Enabled Disabled	Disabled	When enabled, parameter checking for the BSP is turned on. In addition, any modules whose parameter checking configuration is set to 'Default (BSP)' will perform parameter checking as well.
Assert Failures	Return FSP_ERR_ASSERTION Call fsp_error_log then Return FSP_ERR_ASSERTION Use assert() to Halt Execution Disable checks that would return FSP_ERR_ASSERTION	Return FSP_ERR_ASSERTION	Define the behavior of the FSP_ASSERT() macro.
Error Log	No Error Log Errors Logged via fsp_error_log	No Error Log	Specify error logging behavior.
Wakeup Reset Handler Enable	Enable Disable	Enable	If enabled, the default Reset Handler is substituted with an SRAM-based version of it that can be used in applications that utilise the Low-Power modes.
Clock Registers not Reset Values during Startup	Disabled Enabled	Disabled	If enabled, registers are assumed to be set to their reset value during startup. Enable this if another application such as a bootloader or Secure project has already configured the clocks before the startup code runs.
C Runtime Initialization	Enabled Disabled	Enabled	Select if the C runtime initialization in the BSP is to be used. If disabled, use the BSP_WARM_START_POST_CLOCK event to run user defined equivalent.
Early BSP Initialization	Enabled Disabled	Disabled	Enable this option to use BSP functions before C runtime initialization (BSP_WARM_START_RESET or BSP_WARM_START_POST_CLOCK).
Main Oscillator (XtalM) Populated	Populated Not Populated	Populated	Select whether or not there is a main oscillator (XTAL??M) on the board. This setting can be overridden in board_cfg.h.
Main Oscillator (XtalM) Stabilization Time (us)	Value must be non-negative. If 0, the stabilization time is auto-detected.	0	Select the main oscillator stabilization time. This is used in the startup code and is also used by R_CGC. This setting can be overridden in board_cfg.h
Subclock (XtalK) Populated	Populated Not Populated	Populated	Select whether or not there is a subclock crystal on the board. This setting can be overridden in board_cfg.h.
Subclock (XtalK) Stabilization Time (ms)	Value must be non-negative.	600	Select the subclock oscillator stabilization time. This is only used in the startup code if the subclock is selected as the system clock on the Clocks tab and is also used by R_CGC. This setting can be overridden in board_cfg.h
Clock Calibration Cycles	Value must between 1 and 65535	25	The number of cycles used when calibrating the low-power clock. The accuracy of the measurement is proportional to the number of cycles selected, but a higher number of cycles introduces a greater latency in the startup sequence.
Image Header Version	Value must be between 0 and 0xFFFFFFFF.	0x00000000	The Image Header Version is in Little-Endian format so version 01.02.03.04 should be set as 0x04030201.
Headerless Mode	True False	False	Select whether or not the product and image header will be included in the generated file.

Macros
#define	BSP_IRQ_DISABLED

#define	FSP_LOG_PRINT(X)

#define	FSP_RETURN(err)

#define	FSP_ERROR_LOG(err)

#define	FSP_ASSERT(a)

#define	FSP_ERROR_RETURN(a, err)

#define	BSP_PUSH_SCRATCH_REGISTERS

#define	BSP_GET_SP()

#define	BSP_CHECK_DEBUG(a)
	Stop execution if a condition is false, in non-production builds. More...

#define	BSP_CHECK_FATAL(a)
	Stop execution if a condition is false. More...

#define	FSP_REG_VAR_FIELD_GET(base, reg, field, var)

#define	FSP_REG_VAR_FIELD_SET(base, reg, field, var, val)

#define	FSP_REG_SET_MASKED(base, reg, mask, value)
	Sets register bits, indicated by the mask, to a value. More...

#define	FSP_MEM_GET_MASKED(addr, mask)
	Return the value of a memory field using a mask. More...

#define	FSP_REG_ADDR_GET_INDEXED(base, reg, stride, index)
	Get the address of a register value by index (provided a register stride) More...

#define	FSP_REG_FIELD_GET_INDEXED(base, reg, field, stride, index)
	Return the value of a register field by index (provided a register stride). More...

#define	FSP_MEM_SET_MASKED(addr, mask, value)
	Sets memory bits, indicated by the mask, to a value. More...

#define	FSP_REG_FIELD_SET_BITS32(base, reg, field, v)

#define	FSP_REG_MSK(base, reg, field)

#define	FSP_SWAP32(a)

#define	FSP_SWAP16(a)

#define	FSP_CRITICAL_SECTION_ENTER

#define	FSP_CRITICAL_SECTION_EXIT

#define	FSP_INVALID_VECTOR

#define	BSP_DEBUGGER_ENABLE

#define	BSP_DEBUGGER_DISABLE

#define	BSP_CFG_HANDLE_UNRECOVERABLE_ERROR(x)

#define	BSP_STACK_ALIGNMENT

#define	R_BSP_MODULE_START(ip, channel)

#define	R_BSP_MODULE_STOP(ip, channel)

Enumerations
enum	bsp_warm_start_event_t

enum	ahb_clk_div_t
	The AMBA High-Performance Bus (AHB) clock divider. More...

enum	fsp_priv_source_clock_t

enum	bsp_delay_units_t

enum	bsp_grp_irq_t

enum	fsp_ip_t

enum	fsp_signal_t

Variables
uint32_t SystemCoreClock	BSP_SECTION_EARLY_INIT

Macro Definition Documentation

◆ BSP_IRQ_DISABLED

#define BSP_IRQ_DISABLED

Used to signify that an ELC event is not able to be used as an interrupt.

◆ FSP_LOG_PRINT

#define FSP_LOG_PRINT ( X )

Macro that can be defined in order to enable logging in FSP modules.

◆ FSP_RETURN

#define FSP_RETURN ( err )

Macro to log and return error without an assertion.

◆ FSP_ERROR_LOG

#define FSP_ERROR_LOG ( err )

This function is called before returning an error code. To stop on a runtime error, define fsp_error_log in user code and do required debugging (breakpoints, stack dump, etc) in this function.

◆ FSP_ASSERT

#define FSP_ASSERT ( a )

Default assertion calls FSP_ERROR_RETURN if condition "a" is false. Used to identify incorrect use of API's in FSP functions.

◆ FSP_ERROR_RETURN

#define FSP_ERROR_RETURN	(	a,
		err
	)

All FSP error codes are returned using this macro. Calls FSP_ERROR_LOG function if condition "a" is false. Used to identify runtime errors in FSP functions.

◆ BSP_PUSH_SCRATCH_REGISTERS

#define BSP_PUSH_SCRATCH_REGISTERS

Push ARM Cortex-M scratch registers on stack.

◆ BSP_GET_SP

#define BSP_GET_SP ( )

Get the value of the stack pointer.

◆ BSP_CHECK_DEBUG

#define BSP_CHECK_DEBUG ( a )

Stop execution if a condition is false, in non-production builds.

Used to detect an unexpected state at run-time during development.

Note: In non-production builds, if the condition is false, g_halt_impl() is called.; In production builds, the condition is evaluated but nothing else happens, regardless of the outcome.

◆ BSP_CHECK_FATAL

#define BSP_CHECK_FATAL ( a )

Stop execution if a condition is false.

Used to log and recover from a fatal state at run-time.

Note: In non-production builds, if the condition is false, g_halt_impl() is called, which is identical to the behavior of BSP_CHECK_DEBUG().; In production builds, if the condition is false, interrupts are disabled and a SW breakpoint is issued. If a debugger is attached execution will halt. If a debugger is not attached, the breakpoint will be escalated to a Hard_Fault.

◆ FSP_REG_VAR_FIELD_GET

#define FSP_REG_VAR_FIELD_GET	(	base,
		reg,
		field,
		var
	)

Return the value of a register field, with the register value being stored in a variable e.g.

uint16_t tmp;
int counter;
tmp = CRG_TOP->TRIM_CTRL_REG;
counter = FSP_REG_VAR_FIELD_GET(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp);
...

◆ FSP_REG_VAR_FIELD_SET

#define FSP_REG_VAR_FIELD_SET	(	base,
		reg,
		field,
		var,
		val
	)

Set the value of a register field, with the register value being stored in a variable e.g.

uint16_t tmp;
tmp = CRG_TOP->TRIM_CTRL_REG;
FSP_REG_VAR_FIELD_SET(CRG_TOP, TRIM_CTRL_REG, XTAL_COUNT_N, tmp, 10);
FSP_REG_VAR_FIELD_SET(CRG_TOP, TRIM_CTRL_REG, XTAL_TRIM_SELECT, tmp, 2);
CRG_TOP->TRIM_CTRL_REG = tmp;
...

◆ FSP_REG_SET_MASKED

#define FSP_REG_SET_MASKED	(	base,
		reg,
		mask,
		value
	)

Sets register bits, indicated by the mask, to a value.

e.g.

FSP_REG_SET_MASKED(RFCU_POWER, RF_CNTRL_TIMER_5_REG, 0xFF00, 0x1818);

◆ FSP_MEM_GET_MASKED

#define FSP_MEM_GET_MASKED	(	addr,
		mask
	)

Return the value of a memory field using a mask.

e.g.

uint32_t val;
val = FSP_MEM_GET_MASKED(0x50000000, 0x1UL);
...

◆ FSP_REG_ADDR_GET_INDEXED

#define FSP_REG_ADDR_GET_INDEXED	(	base,
		reg,
		stride,
		index
	)

Get the address of a register value by index (provided a register stride)

Note: The register stride should be an exact multiple of the register's base size. For example, if the register size is 32-bit, then the stride should be 0x4, 0x8, etc. Otherwise, the result will be undefined. The stride value must be in bytes. The index value (0,1,2...) is multiplied by the stride value (in bytes) to find the actual offset of the register.

Returns a register address value by index

◆ FSP_REG_FIELD_GET_INDEXED

#define FSP_REG_FIELD_GET_INDEXED	(	base,
		reg,
		field,
		stride,
		index
	)

Return the value of a register field by index (provided a register stride).

e.g.

uint16_t val;
uint16_t index = 2
val = REG_GETF_INDEXED(FTDF, FTDF_LONG_ADDR_0_0_REG, REG_EXP_SA_L, 0x10, index)
...

Note: The register stride should be an exact multiple of the register's base size. For example, if the register size is 32-bit, then the stride should be 0x4, 0x8, etc. Otherwise, the result will be undefined. The stride value must be in bytes. The index value (0,1,2...) is multiplied by the stride value (in bytes) to find the actual offset of the register.

◆ FSP_MEM_SET_MASKED

#define FSP_MEM_SET_MASKED	(	addr,
		mask,
		value
	)

Sets memory bits, indicated by the mask, to a value.

e.g.

FSP_MEM_SET_MASKED(0x50000000, 0xFF00, 0x1818);

◆ FSP_REG_FIELD_SET_BITS32

#define FSP_REG_FIELD_SET_BITS32	(	base,
		reg,
		field,
		v
	)

Sets 32-bit wide register bits, indicated by the field, to a value v.

◆ FSP_REG_MSK

#define FSP_REG_MSK	(	base,
		reg,
		field
	)

Access register field mask.

Returns a register field mask (aimed to be used with local variables). e.g.

uint16_t tmp;
tmp = CRG_TOP->SYS_STAT_REG;
if (tmp & FSP_REG_MSK(CRG_TOP, SYS_STAT_REG, XTAL16_TRIM_READY)) {
...

◆ FSP_SWAP32

#define FSP_SWAP32 ( a )

Macro to swap the bytes of a 32-bit variable

Parameters

[in] a The 32-bit variable

◆ FSP_SWAP16

#define FSP_SWAP16 ( a )

Macro to swap the bytes of a 16-bit variable

Parameters

[in] a The 16-bit variable

◆ FSP_CRITICAL_SECTION_ENTER

#define FSP_CRITICAL_SECTION_ENTER

This macro temporarily saves the current interrupt state and disables interrupts.

◆ FSP_CRITICAL_SECTION_EXIT

#define FSP_CRITICAL_SECTION_EXIT

This macro restores the previously saved interrupt state, reenabling interrupts.

◆ FSP_INVALID_VECTOR

#define FSP_INVALID_VECTOR

Used to signify that the requested IRQ vector is not defined in this system.

◆ BSP_DEBUGGER_ENABLE

#define BSP_DEBUGGER_ENABLE

Macro to enable the debugger

◆ BSP_DEBUGGER_DISABLE

#define BSP_DEBUGGER_DISABLE

Macro to disable the debugger

◆ BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

#define BSP_CFG_HANDLE_UNRECOVERABLE_ERROR ( x )

In the event of an unrecoverable error the BSP will by default call the __BKPT() intrinsic function which will alert the user of the error. The user can override this default behavior by defining their own BSP_CFG_HANDLE_UNRECOVERABLE_ERROR or CUSTOM_BSP_CFG_HANDLE_UNRECOVERABLE_ERROR macro.

◆ BSP_STACK_ALIGNMENT

#define BSP_STACK_ALIGNMENT

Stacks (and heap) must be sized and aligned to an integer multiple of this number.

◆ R_BSP_MODULE_START

#define R_BSP_MODULE_START	(	ip,
		channel
	)

Cancels the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
channel	The channel. Use channel 0 for modules without channels.

◆ R_BSP_MODULE_STOP

#define R_BSP_MODULE_STOP	(	ip,
		channel
	)

Enables the module stop state.

Parameters

ip	fsp_ip_t enum value for the module to be stopped
channel	The channel. Use channel 0 for modules without channels.

Enumeration Type Documentation

◆ bsp_warm_start_event_t

enum bsp_warm_start_event_t

Different warm start entry locations in the BSP.

Enumerator
BSP_WARM_START_RESET	Called almost immediately after reset. No C runtime environment, clocks, or IRQs.
BSP_WARM_START_POST_CLOCK	Called after clock initialization. No C runtime environment or IRQs.
BSP_WARM_START_POST_C	Called after clocks and C runtime environment have been set up.
BSP_WARM_PM_WOKENUP	Called after wake up when power management module is used.
BSP_WARM_PM_SLEEP	Called before sleep when power management module is used.

◆ ahb_clk_div_t

enum ahb_clk_div_t

The AMBA High-Performance Bus (AHB) clock divider.

Enumerator
BSP_AHB_CLK_DIV1	Divide by 1.
BSP_AHB_CLK_DIV2	Divide by 2.
BSP_AHB_CLK_DIV4	Divide by 4.
BSP_AHB_CLK_DIV8	Divide by 8.
BSP_AHB_CLK_DIV16	Divide by 16.

◆ fsp_priv_source_clock_t

enum fsp_priv_source_clock_t

Enumerator
FSP_PRIV_CLOCK_RCHS	The high-speed on-chip oscillator (RCHS)
FSP_PRIV_CLOCK_XTALM	The main oscillator (XTAL32M)
FSP_PRIV_CLOCK_XTALM_DBLR	The main oscillator (XTAL64M)
FSP_PRIV_CLOCK_PLL	The PLL oscillator.
FSP_PRIV_CLOCK_RCLP	The middle-speed on-chip oscillator (RCLP)
FSP_PRIV_CLOCK_RCX	The low-speed on-chip oscillator (RCX)
FSP_PRIV_CLOCK_XTALK	The subclock oscillator (XTAL32K)
FSP_PRIV_CLOCK_DIGITAL	The subclock oscillator (externally supplied digital clock)

◆ bsp_delay_units_t

enum bsp_delay_units_t

Available delay units for R_BSP_SoftwareDelay(). These are ultimately used to calculate a total # of microseconds

Enumerator
BSP_DELAY_UNITS_SECONDS	Requested delay amount is in seconds.
BSP_DELAY_UNITS_MILLISECONDS	Requested delay amount is in milliseconds.
BSP_DELAY_UNITS_MICROSECONDS	Requested delay amount is in microseconds.

◆ bsp_grp_irq_t

enum bsp_grp_irq_t

Which interrupts can have callbacks registered.

Enumerator
BSP_GRP_IRQ_WDT_ERROR	WDT underflow/refresh error has occurred.
BSP_GRP_IRQ_VBATT	VBATT monitor interrupt.
BSP_GRP_IRQ_TRUSTZONE	MPU Stack Error.

◆ fsp_ip_t

enum fsp_ip_t

Available modules.

Enumerator
FSP_IP_CFLASH	Code Flash.
FSP_IP_DFLASH	Data Flash.
FSP_IP_RAM	RAM.
FSP_IP_LVD	Low Voltage Detection.
FSP_IP_CGC	Clock Generation Circuit.
FSP_IP_LPM	Low Power Modes.
FSP_IP_FCU	Flash Control Unit.
FSP_IP_ICU	Interrupt Control Unit.
FSP_IP_DMAC	DMA Controller.
FSP_IP_DTC	Data Transfer Controller.
FSP_IP_IOPORT	I/O Ports.
FSP_IP_PFS	Pin Function Select.
FSP_IP_ELC	Event Link Controller.
FSP_IP_MPU	Memory Protection Unit.
FSP_IP_MSTP	Module Stop.
FSP_IP_MMF	Memory Mirror Function.
FSP_IP_KEY	Key Interrupt Function.
FSP_IP_CAC	Clock Frequency Accuracy Measurement Circuit.
FSP_IP_DOC	Data Operation Circuit.
FSP_IP_CRC	Cyclic Redundancy Check Calculator.
FSP_IP_SCI	Serial Communications Interface.
FSP_IP_IIC	I2C Bus Interface.
FSP_IP_SPI	Serial Peripheral Interface.
FSP_IP_CTSU	Capacitive Touch Sensing Unit.
FSP_IP_SCE	Secure Cryptographic Engine.
FSP_IP_SLCDC	Segment LCD Controller.
FSP_IP_AES	Advanced Encryption Standard.
FSP_IP_TRNG	True Random Number Generator.
FSP_IP_FCACHE	Flash Cache.
FSP_IP_SRAM	SRAM.
FSP_IP_ADC	A/D Converter.
FSP_IP_DAC	12-Bit D/A Converter
FSP_IP_TSN	Temperature Sensor.
FSP_IP_DAAD	D/A A/D Synchronous Unit.
FSP_IP_ACMPHS	High Speed Analog Comparator.
FSP_IP_ACMPLP	Low Power Analog Comparator.
FSP_IP_OPAMP	Operational Amplifier.
FSP_IP_SDADC	Sigma Delta A/D Converter.
FSP_IP_RTC	Real Time Clock.
FSP_IP_WDT	Watch Dog Timer.
FSP_IP_IWDT	Independent Watch Dog Timer.
FSP_IP_GPT	General PWM Timer.
FSP_IP_POEG	Port Output Enable for GPT.
FSP_IP_OPS	Output Phase Switch.
FSP_IP_AGT	Asynchronous General-Purpose Timer.
FSP_IP_CAN	Controller Area Network.
FSP_IP_IRDA	Infrared Data Association.
FSP_IP_QSPI	Quad Serial Peripheral Interface.
FSP_IP_USBFS	USB Full Speed.
FSP_IP_SDHI	SD/MMC Host Interface.
FSP_IP_SRC	Sampling Rate Converter.
FSP_IP_SSI	Serial Sound Interface.
FSP_IP_DALI	Digital Addressable Lighting Interface.
FSP_IP_ETHER	Ethernet MAC Controller.
FSP_IP_EDMAC	Ethernet DMA Controller.
FSP_IP_EPTPC	Ethernet PTP Controller.
FSP_IP_PDC	Parallel Data Capture Unit.
FSP_IP_GLCDC	Graphics LCD Controller.
FSP_IP_DRW	2D Drawing Engine
FSP_IP_JPEG	JPEG.
FSP_IP_DAC8	8-Bit D/A Converter
FSP_IP_USBHS	USB High Speed.
FSP_IP_OSPI	Octa Serial Peripheral Interface.
FSP_IP_CEC	HDMI CEC.
FSP_IP_TFU	Trigonometric Function Unit.
FSP_IP_IIRFA	IIR Filter Accelerator.
FSP_IP_CANFD	CAN-FD.
FSP_IP_ULPT	Ultra Low Power Timer ULPT.
FSP_IP_SAU	Serial Array Unit.
FSP_IP_IICA	Serial Interface IICA.
FSP_IP_UARTA	Serial Interface UARTA.
FSP_IP_TAU	Timer Array Unit.
FSP_IP_TML	32-bit Interval Timer
FSP_IP_MACL	32-bit Multiply-Accumulator
FSP_IP_USBCC	USB Type-C Controller.

◆ fsp_signal_t

enum fsp_signal_t

Signals that can be mapped to an interrupt.

Enumerator
FSP_SIGNAL_ADC_COMPARE_MATCH	ADC COMPARE MATCH.
FSP_SIGNAL_ADC_COMPARE_MISMATCH	ADC COMPARE MISMATCH.
FSP_SIGNAL_ADC_SCAN_END	ADC SCAN END.
FSP_SIGNAL_ADC_SCAN_END_B	ADC SCAN END B.
FSP_SIGNAL_ADC_WINDOW_A	ADC WINDOW A.
FSP_SIGNAL_ADC_WINDOW_B	ADC WINDOW B.
FSP_SIGNAL_AES_RDREQ	AES RDREQ.
FSP_SIGNAL_AES_WRREQ	AES WRREQ.
FSP_SIGNAL_AGT_COMPARE_A	AGT COMPARE A.
FSP_SIGNAL_AGT_COMPARE_B	AGT COMPARE B.
FSP_SIGNAL_AGT_INT	AGT INT.
FSP_SIGNAL_CAC_FREQUENCY_ERROR	CAC FREQUENCY ERROR.
FSP_SIGNAL_CAC_MEASUREMENT_END	CAC MEASUREMENT END.
FSP_SIGNAL_CAC_OVERFLOW	CAC OVERFLOW.
FSP_SIGNAL_CAN_ERROR	CAN ERROR.
FSP_SIGNAL_CAN_FIFO_RX	CAN FIFO RX.
FSP_SIGNAL_CAN_FIFO_TX	CAN FIFO TX.
FSP_SIGNAL_CAN_MAILBOX_RX	CAN MAILBOX RX.
FSP_SIGNAL_CAN_MAILBOX_TX	CAN MAILBOX TX.
FSP_SIGNAL_CGC_MOSC_STOP	CGC MOSC STOP.
FSP_SIGNAL_LPM_SNOOZE_REQUEST	LPM SNOOZE REQUEST.
FSP_SIGNAL_LVD_LVD1	LVD LVD1.
FSP_SIGNAL_LVD_LVD2	LVD LVD2.
FSP_SIGNAL_VBATT_LVD	VBATT LVD.
FSP_SIGNAL_LVD_VBATT	LVD VBATT.
FSP_SIGNAL_ACMPHS_INT	ACMPHS INT.
FSP_SIGNAL_ACMPLP_INT	ACMPLP INT.
FSP_SIGNAL_CTSU_END	CTSU END.
FSP_SIGNAL_CTSU_READ	CTSU READ.
FSP_SIGNAL_CTSU_WRITE	CTSU WRITE.
FSP_SIGNAL_DALI_DEI	DALI DEI.
FSP_SIGNAL_DALI_CLI	DALI CLI.
FSP_SIGNAL_DALI_SDI	DALI SDI.
FSP_SIGNAL_DALI_BPI	DALI BPI.
FSP_SIGNAL_DALI_FEI	DALI FEI.
FSP_SIGNAL_DALI_SDI_OR_BPI	DALI SDI OR BPI.
FSP_SIGNAL_DMAC_INT	DMAC INT.
FSP_SIGNAL_DOC_INT	DOC INT.
FSP_SIGNAL_DRW_INT	DRW INT.
FSP_SIGNAL_DTC_COMPLETE	DTC COMPLETE.
FSP_SIGNAL_DTC_END	DTC END.
FSP_SIGNAL_EDMAC_EINT	EDMAC EINT.
FSP_SIGNAL_ELC_SOFTWARE_EVENT_0	ELC SOFTWARE EVENT 0.
FSP_SIGNAL_ELC_SOFTWARE_EVENT_1	ELC SOFTWARE EVENT 1.
FSP_SIGNAL_EPTPC_IPLS	EPTPC IPLS.
FSP_SIGNAL_EPTPC_MINT	EPTPC MINT.
FSP_SIGNAL_EPTPC_PINT	EPTPC PINT.
FSP_SIGNAL_EPTPC_TIMER0_FALL	EPTPC TIMER0 FALL.
FSP_SIGNAL_EPTPC_TIMER0_RISE	EPTPC TIMER0 RISE.
FSP_SIGNAL_EPTPC_TIMER1_FALL	EPTPC TIMER1 FALL.
FSP_SIGNAL_EPTPC_TIMER1_RISE	EPTPC TIMER1 RISE.
FSP_SIGNAL_EPTPC_TIMER2_FALL	EPTPC TIMER2 FALL.
FSP_SIGNAL_EPTPC_TIMER2_RISE	EPTPC TIMER2 RISE.
FSP_SIGNAL_EPTPC_TIMER3_FALL	EPTPC TIMER3 FALL.
FSP_SIGNAL_EPTPC_TIMER3_RISE	EPTPC TIMER3 RISE.
FSP_SIGNAL_EPTPC_TIMER4_FALL	EPTPC TIMER4 FALL.
FSP_SIGNAL_EPTPC_TIMER4_RISE	EPTPC TIMER4 RISE.
FSP_SIGNAL_EPTPC_TIMER5_FALL	EPTPC TIMER5 FALL.
FSP_SIGNAL_EPTPC_TIMER5_RISE	EPTPC TIMER5 RISE.
FSP_SIGNAL_FCU_FIFERR	FCU FIFERR.
FSP_SIGNAL_FCU_FRDYI	FCU FRDYI.
FSP_SIGNAL_GLCDC_LINE_DETECT	GLCDC LINE DETECT.
FSP_SIGNAL_GLCDC_UNDERFLOW_1	GLCDC UNDERFLOW 1.
FSP_SIGNAL_GLCDC_UNDERFLOW_2	GLCDC UNDERFLOW 2.
FSP_SIGNAL_GPT_CAPTURE_COMPARE_A	GPT CAPTURE COMPARE A.
FSP_SIGNAL_GPT_CAPTURE_COMPARE_B	GPT CAPTURE COMPARE B.
FSP_SIGNAL_GPT_COMPARE_C	GPT COMPARE C.
FSP_SIGNAL_GPT_COMPARE_D	GPT COMPARE D.
FSP_SIGNAL_GPT_COMPARE_E	GPT COMPARE E.
FSP_SIGNAL_GPT_COMPARE_F	GPT COMPARE F.
FSP_SIGNAL_GPT_COUNTER_OVERFLOW	GPT COUNTER OVERFLOW.
FSP_SIGNAL_GPT_COUNTER_UNDERFLOW	GPT COUNTER UNDERFLOW.
FSP_SIGNAL_GPT_AD_TRIG_A	GPT AD TRIG A.
FSP_SIGNAL_GPT_AD_TRIG_B	GPT AD TRIG B.
FSP_SIGNAL_OPS_UVW_EDGE	OPS UVW EDGE.
FSP_SIGNAL_ICU_IRQ0	ICU IRQ0.
FSP_SIGNAL_ICU_IRQ1	ICU IRQ1.
FSP_SIGNAL_ICU_IRQ2	ICU IRQ2.
FSP_SIGNAL_ICU_IRQ3	ICU IRQ3.
FSP_SIGNAL_ICU_IRQ4	ICU IRQ4.
FSP_SIGNAL_ICU_IRQ5	ICU IRQ5.
FSP_SIGNAL_ICU_IRQ6	ICU IRQ6.
FSP_SIGNAL_ICU_IRQ7	ICU IRQ7.
FSP_SIGNAL_ICU_IRQ8	ICU IRQ8.
FSP_SIGNAL_ICU_IRQ9	ICU IRQ9.
FSP_SIGNAL_ICU_IRQ10	ICU IRQ10.
FSP_SIGNAL_ICU_IRQ11	ICU IRQ11.
FSP_SIGNAL_ICU_IRQ12	ICU IRQ12.
FSP_SIGNAL_ICU_IRQ13	ICU IRQ13.
FSP_SIGNAL_ICU_IRQ14	ICU IRQ14.
FSP_SIGNAL_ICU_IRQ15	ICU IRQ15.
FSP_SIGNAL_ICU_SNOOZE_CANCEL	ICU SNOOZE CANCEL.
FSP_SIGNAL_IIC_ERI	IIC ERI.
FSP_SIGNAL_IIC_RXI	IIC RXI.
FSP_SIGNAL_IIC_TEI	IIC TEI.
FSP_SIGNAL_IIC_TXI	IIC TXI.
FSP_SIGNAL_IIC_WUI	IIC WUI.
FSP_SIGNAL_IOPORT_EVENT_1	IOPORT EVENT 1.
FSP_SIGNAL_IOPORT_EVENT_2	IOPORT EVENT 2.
FSP_SIGNAL_IOPORT_EVENT_3	IOPORT EVENT 3.
FSP_SIGNAL_IOPORT_EVENT_4	IOPORT EVENT 4.
FSP_SIGNAL_IOPORT_EVENT_B	IOPORT EVENT B.
FSP_SIGNAL_IOPORT_EVENT_C	IOPORT EVENT C.
FSP_SIGNAL_IOPORT_EVENT_D	IOPORT EVENT D.
FSP_SIGNAL_IOPORT_EVENT_E	IOPORT EVENT E.
FSP_SIGNAL_IWDT_UNDERFLOW	IWDT UNDERFLOW.
FSP_SIGNAL_JPEG_JDTI	JPEG JDTI.
FSP_SIGNAL_JPEG_JEDI	JPEG JEDI.
FSP_SIGNAL_KEY_INT	KEY INT.
FSP_SIGNAL_PDC_FRAME_END	PDC FRAME END.
FSP_SIGNAL_PDC_INT	PDC INT.
FSP_SIGNAL_PDC_RECEIVE_DATA_READY	PDC RECEIVE DATA READY.
FSP_SIGNAL_POEG_EVENT	POEG EVENT.
FSP_SIGNAL_QSPI_INT	QSPI INT.
FSP_SIGNAL_RTC_ALARM	RTC ALARM.
FSP_SIGNAL_RTC_PERIOD	RTC PERIOD.
FSP_SIGNAL_RTC_CARRY	RTC CARRY.
FSP_SIGNAL_SCE_INTEGRATE_RDRDY	SCE INTEGRATE RDRDY.
FSP_SIGNAL_SCE_INTEGRATE_WRRDY	SCE INTEGRATE WRRDY.
FSP_SIGNAL_SCE_LONG_PLG	SCE LONG PLG.
FSP_SIGNAL_SCE_PROC_BUSY	SCE PROC BUSY.
FSP_SIGNAL_SCE_RDRDY_0	SCE RDRDY 0.
FSP_SIGNAL_SCE_RDRDY_1	SCE RDRDY 1.
FSP_SIGNAL_SCE_ROMOK	SCE ROMOK.
FSP_SIGNAL_SCE_TEST_BUSY	SCE TEST BUSY.
FSP_SIGNAL_SCE_WRRDY_0	SCE WRRDY 0.
FSP_SIGNAL_SCE_WRRDY_1	SCE WRRDY 1.
FSP_SIGNAL_SCE_WRRDY_4	SCE WRRDY 4.
FSP_SIGNAL_SCI_AM	SCI AM.
FSP_SIGNAL_SCI_ERI	SCI ERI.
FSP_SIGNAL_SCI_RXI	SCI RXI.
FSP_SIGNAL_SCI_RXI_OR_ERI	SCI RXI OR ERI.
FSP_SIGNAL_SCI_TEI	SCI TEI.
FSP_SIGNAL_SCI_TXI	SCI TXI.
FSP_SIGNAL_SDADC_ADI	SDADC ADI.
FSP_SIGNAL_SDADC_SCANEND	SDADC SCANEND.
FSP_SIGNAL_SDADC_CALIEND	SDADC CALIEND.
FSP_SIGNAL_SDHIMMC_ACCS	SDHIMMC ACCS.
FSP_SIGNAL_SDHIMMC_CARD	SDHIMMC CARD.
FSP_SIGNAL_SDHIMMC_DMA_REQ	SDHIMMC DMA REQ.
FSP_SIGNAL_SDHIMMC_SDIO	SDHIMMC SDIO.
FSP_SIGNAL_SPI_ERI	SPI ERI.
FSP_SIGNAL_SPI_IDLE	SPI IDLE.
FSP_SIGNAL_SPI_RXI	SPI RXI.
FSP_SIGNAL_SPI_TEI	SPI TEI.
FSP_SIGNAL_SPI_TXI	SPI TXI.
FSP_SIGNAL_SRC_CONVERSION_END	SRC CONVERSION END.
FSP_SIGNAL_SRC_INPUT_FIFO_EMPTY	SRC INPUT FIFO EMPTY.
FSP_SIGNAL_SRC_OUTPUT_FIFO_FULL	SRC OUTPUT FIFO FULL.
FSP_SIGNAL_SRC_OUTPUT_FIFO_OVERFLOW	SRC OUTPUT FIFO OVERFLOW.
FSP_SIGNAL_SRC_OUTPUT_FIFO_UNDERFLOW	SRC OUTPUT FIFO UNDERFLOW.
FSP_SIGNAL_SSI_INT	SSI INT.
FSP_SIGNAL_SSI_RXI	SSI RXI.
FSP_SIGNAL_SSI_TXI	SSI TXI.
FSP_SIGNAL_SSI_TXI_RXI	SSI TXI RXI.
FSP_SIGNAL_TRNG_RDREQ	TRNG RDREQ.
FSP_SIGNAL_USB_FIFO_0	USB FIFO 0.
FSP_SIGNAL_USB_FIFO_1	USB FIFO 1.
FSP_SIGNAL_USB_INT	USB INT.
FSP_SIGNAL_USB_RESUME	USB RESUME.
FSP_SIGNAL_USB_USB_INT_RESUME	USB USB INT RESUME.
FSP_SIGNAL_WDT_UNDERFLOW	WDT UNDERFLOW.
FSP_SIGNAL_ULPT_COMPARE_A	ULPT COMPARE A.
FSP_SIGNAL_ULPT_COMPARE_B	ULPT COMPARE B.
FSP_SIGNAL_ULPT_INT	ULPT INT.

Function Documentation

◆ R_FSP_VersionGet()

fsp_err_t R_FSP_VersionGet ( fsp_pack_version_t *const p_version )

Get the FSP version based on compile time macros.

Parameters

[out] p_version Memory address to return version information to.

Return values

FSP_SUCCESS	Version information stored.
FSP_ERR_ASSERTION	The parameter p_version is NULL.

◆ Default_Handler()

void Default_Handler ( void )

Default exception handler.

◆ Reset_Handler()

void Reset_Handler ( void )

MCU starts executing here out of reset. Main stack pointer is set up already.

◆ _exit()

void _exit ( int __status )

Disable TRNG circuit to prevent unnecessary current draw which may otherwise occur when the Crypto module is not in use. Fallback weak implemenation of _exit(), which just hangs.

◆ SystemInit()

void SystemInit ( void )

Initialize the MCU and the runtime environment.

◆ R_BSP_WarmStart()

void R_BSP_WarmStart ( bsp_warm_start_event_t event )

This function is called at various points during the startup process. This function is declared as a weak symbol higher up in this file because it is meant to be overridden by a user implemented version. One of the main uses for this function is to call functional safety code during the startup process. To use this function just copy this function into your own code and modify it to meet your needs.

Parameters

[in] event Where the code currently is in the start up process

◆ R_BSP_SourceClockHzGet()

uint32_t R_BSP_SourceClockHzGet ( fsp_priv_source_clock_t clock )

Gets the frequency of a source clock.

Parameters

[in] clock Pointer to Octaclk setting structure which provides information regarding Octaclk source and divider settings to be applied.

Returns: Frequency of requested clock in Hertz.

◆ R_BSP_SourceClockHzSet()

void R_BSP_SourceClockHzSet	(	fsp_priv_source_clock_t	clock,
		uint32_t	freq
	)

Sets the frequency of a source clock.

Parameters

[in]	clock	Pointer to Octaclk setting structure which provides information regarding Octaclk source and divider settings to be applied.
[in]	freq	Frequency of requested clock in Hertz.

◆ R_FSP_CurrentIrqGet()

__STATIC_FORCEINLINE IRQn_Type R_FSP_CurrentIrqGet ( void )

Return active interrupt vector number value

Returns: Active interrupt vector number value

◆ bsp_clock_ahb_div_get()

__STATIC_INLINE ahb_clk_div_t bsp_clock_ahb_div_get ( void )

Get the Sys_clk divider for HCLK.

Returns: current HCLK_DIV value

◆ R_FSP_SystemClockHzGet()

__STATIC_INLINE uint32_t R_FSP_SystemClockHzGet ( fsp_priv_clock_t clock )

Gets the frequency of a system clock.

Returns: Frequency of requested clock in Hertz.

◆ R_FSP_ClockDividerGet()

__STATIC_INLINE uint32_t R_FSP_ClockDividerGet ( uint32_t ckdivcr )

Converts a clock's CKDIVCR register value to a clock divider (Eg: SPICKDIVCR).

Returns: Clock Divider

◆ R_BSP_UniqueIdGet()

__STATIC_INLINE bsp_unique_id_t const* R_BSP_UniqueIdGet ( void )

Get unique ID for this device.

Returns: A pointer to the unique identifier structure

◆ R_BSP_FlashCacheDisable()

__STATIC_INLINE void R_BSP_FlashCacheDisable ( void )

Disables the flash cache.

◆ R_BSP_FlashCacheEnable()

__STATIC_INLINE void R_BSP_FlashCacheEnable ( void )

Enables the flash cache.

◆ fast_memcpy()

void* fast_memcpy	(	void *	dest,
		const void *	src,
		size_t	n
	)

Streamlined version of memcpy().

It is optimized for the following cases:

dest and src are 32-bit aligned
if n is larger than 32, blocks of 32 bytes are copied, to the extent possible
if n is larger than 16, blocks of 16 bytes are copied, to the extent possible

◆ fast_memset()

void* fast_memset	(	void *	b,
		int	c,
		size_t	len
	)

Streamlined version of memset().

It is optimized for the following cases:

if n is larger than 32, blocks of 32 bytes are set, to the extent possible
if n is larger than 16, blocks of 16 bytes are set, to the extent possible

◆ R_BSP_SoftwareDelay()

BSP_PLACE_CODE_IN_RAM void R_BSP_SoftwareDelay	(	uint32_t	delay,
		bsp_delay_units_t	units
	)

Delay for at least the specified duration in units and return.

Parameters

[in]	delay	The number of 'units' to delay.
[in]	units	The 'base' (bsp_delay_units_t) for the units specified. Valid values are: BSP_DELAY_UNITS_SECONDS, BSP_DELAY_UNITS_MILLISECONDS, BSP_DELAY_UNITS_MICROSECONDS.

Note: This function calls bsp_cpu_clock_get() which ultimately calls R_CGC_SystemClockFreqGet() and therefore requires that the BSP has already initialized the CGC (which it does as part of the Sysinit). Care should be taken to ensure this remains the case if in the future this function were to be called as part of the BSP initialization.; Delays may be longer than expected when compiler optimization is turned off.

◆ R_BSP_GroupIrqWrite()

fsp_err_t R_BSP_GroupIrqWrite	(	bsp_grp_irq_t	irq,
		void(*)(bsp_grp_irq_t irq)	p_callback
	)

Register a callback function for supported interrupts. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.

Parameters

[in]	irq	Interrupt for which to register a callback.
[in]	p_callback	Pointer to function to call when interrupt occurs.

Return values

FSP_SUCCESS	Callback registered
FSP_ERR_ASSERTION	Callback pointer is NULL

◆ R_BSP_GroupNmiWrite()

fsp_err_t R_BSP_GroupNmiWrite ( void(*)(const uint32_t *p_exception_args) p_callback )

Register a callback function for NMI. If NULL is passed for the callback argument then any previously registered callbacks are unregistered.

Parameters

[in] p_callback Pointer to function to call when NMI occurs.

Return values

FSP_SUCCESS	Callback registered
FSP_ERR_ASSERTION	Callback pointer is NULL

◆ NMI_HandlerC()

BSP_WEAK_REFERENCE void NMI_HandlerC ( unsigned long * exception_args )

Non-maskable interrupt handler. This exception is defined by the BSP, unlike other system exceptions, because there are many sources that map to the NMI exception.

Note: NMI exception is caused due to watchdog timeout for DA1469x and hence the registered callback function for handling the WDT error is directly referred

◆ bsp_pd_init()

void bsp_pd_init ( void )

Initialize (zero) the reference counters of all power domains

◆ bsp_pd_use()

BSP_PLACE_CODE_IN_RAM void bsp_pd_use ( uint32_t pd_id )

Denote starting the use of a power domain

If the power domain pd_id was previously unused, it will be enabled. A per-power-domain reference counter is used to allow for nested calls of this function.

Parameters

[in] pd_id ID of the power domain to start using

See also: bsp_pd_unuse

◆ bsp_pd_unuse()

BSP_PLACE_CODE_IN_RAM void bsp_pd_unuse ( uint32_t pd_id )

Denote ending the use of a power domain

A per-power-domain reference counter is used to allow for nested calls of this function. If the reference counter of the power domain pd_id reaches zero, the power domain will be disabled.

Parameters

[in] pd_id ID of the power domain to stop using

See also: bsp_pd_use

◆ bsp_pd_used_check()

BSP_PLACE_CODE_IN_RAM bool bsp_pd_used_check ( uint32_t pd_id )

Check is a power domain is denoted as used (i.e. its reference counter is non-zero)

Parameters

[in] pd_id ID of the power domain to check

◆ bsp_pd_is_up_check()

bool bsp_pd_is_up_check ( uint32_t pd_id )

Return the "IS_UP" status of a power domain

Parameters

[in] pd_id ID of the power domain to check

Return values

true	if the power domain is up (activated)
false	if the power domain is down (deactivated)

◆ bsp_pd_enable()

BSP_PLACE_CODE_IN_RAM void bsp_pd_enable ( uint32_t pd_id )

Enable (i.e. take out of power-down) a power domain

Parameters

[in] pd_id ID of the power domain to enable

◆ bsp_pd_disable()

BSP_PLACE_CODE_IN_RAM void bsp_pd_disable ( uint32_t pd_id )

Disable (i.e. put in power-down) a power domain

Parameters

[in] pd_id ID of the power domain to disable

◆ R_BSP_DMAC_IsEdgeSensitiveTrigger()

__STATIC_INLINE bool R_BSP_DMAC_IsEdgeSensitiveTrigger ( bsp_dmac_trig_t trigger )

Check whether specified DMA trigger is edge sensitive or not.

Parameters

[in] trigger DMA trigger.

Return values

true	Trigger is (positive) edge-sensitive.
false	Trigger is level-sensitive.

◆ R_BSP_DMAC_ChannelInterruptsEnable()

__STATIC_INLINE void R_BSP_DMAC_ChannelInterruptsEnable ( uint8_t channel )

Enable interrupt generation by specified DMA channel.

Parameters

[in] channel DMA channel.

◆ R_BSP_DMAC_ChannelInterruptsDisable()

__STATIC_INLINE void R_BSP_DMAC_ChannelInterruptsDisable ( uint8_t channel )

Disable interrupt generation by specified DMA channel.

Parameters

[in] channel DMA channel.

◆ R_BSP_PeripheralFreeze()

__STATIC_INLINE void R_BSP_PeripheralFreeze ( bsp_freeze_peripheral_t peripheral )

Suspend activity of specified peripheral on MCU.

Parameters

[in] peripheral Peripheral to freeze.

◆ R_BSP_IsPeripheralFrozen()

__STATIC_INLINE bool R_BSP_IsPeripheralFrozen ( bsp_freeze_peripheral_t peripheral )

Check whether specified peripheral is frozen or not.

Parameters

[in] peripheral Peripheral to check.

Return values

true	Peripheral is frozen.
false	Peripheral is active.

◆ R_BSP_PeripheralUnFreeze()

__STATIC_INLINE void R_BSP_PeripheralUnFreeze ( bsp_freeze_peripheral_t peripheral )

Resume activity of specified peripheral on MCU.

Parameters

[in] peripheral Peripheral to unfreeze.

◆ R_BSP_RetainedIoRecovery()

void R_BSP_RetainedIoRecovery ( uint16_t clear )

This function release setting retain pio and recovery pio status by setting user

Parameters

[in] clear clear retention information in retain memory.

Returns: true/false

◆ R_BSP_RetainedIoExecute()

bool R_BSP_RetainedIoExecute ( void )

This function execute to retain GPIO as using hw_gpio_retention_pin_set.

Returns: true/false

◆ bsp_otpc_set_speed()

__STATIC_FORCEINLINE void bsp_otpc_set_speed ( bsp_otpc_clk_freq_t clk_speed )

Set OTP cell timing parameters.

Parameters

[in] clk_speed OTPC clock speed.

◆ bsp_prv_otpc_addr()

__STATIC_FORCEINLINE volatile uint32_t* bsp_prv_otpc_addr ( uint32_t cell_offset )

Get OTP cell address.

Parameters

[in] cell_offset OTP cell offset.

Returns: OTP cell address.

◆ bsp_prv_otp_mode_set()

__STATIC_FORCEINLINE void bsp_prv_otp_mode_set ( bsp_otpc_mode_t mode )

Set OTP mode.

Parameters

[in] mode The new OTP mode.

◆ bsp_prv_otp_mode_wait_until_set()

__STATIC_FORCEINLINE void bsp_prv_otp_mode_wait_until_set ( bsp_otpc_mode_t mode )

Set OTP mode and wait for it to be applied.

Parameters

[in] mode The new OTP mode.

◆ bsp_otpc_wait_while_busy_programming()

__STATIC_FORCEINLINE void bsp_otpc_wait_while_busy_programming ( void )

Wait for OTP programming to finish.

◆ bsp_otp_init()

void bsp_otp_init ( void )

Initialize the OTP controller.

Note: Among other things, it enables the clock of the OTP controller. TODO this shall not be the case, see WIFISWTIN-1591.

◆ bsp_otp_timings_set()

void bsp_otp_timings_set ( uint32_t sysclk_freq_MHz )

Set OTP timing for the given sysclk frequency.

Parameters

[in] sysclk_freq_MHz The target sysclk frequency, in MHz.

Note: Only specific frequencies are supported, depending on the device. TODO this function shall be updated/deleted, see WIFISWTIN-1591.

◆ bsp_otp_mode_set()

void bsp_otp_mode_set ( uint32_t mode )

Set OTP mode and wait for the change to finish.

Parameters

[in] mode The new OTP mode.

◆ bsp_otp_word_read()

uint32_t bsp_otp_word_read ( uint32_t cell_offset )

Read word from OTP.

Parameters

[in] cell_offset OTP cell offset.

Returns: word read from OTP.

◆ bsp_otp_read()

void bsp_otp_read	(	uint32_t *	p_data,
		uint32_t	cell_offset,
		uint32_t	num_words
	)

Read data from OTP.

Parameters

[out]	p_data	A pointer to the buffer to store OTP data into. It shall be at least of (num_words * 4) bytes long.
[in]	cell_offset	OTP cell offset to start reading from.
[in]	num_words	Number of words to read from OTP.

◆ bsp_otp_word_prog()

uint32_t bsp_otp_word_prog	(	uint32_t	data,
		uint32_t	cell_offset
	)

Program word to OTP.

Parameters

[in]	data	A word to be programmed to OTP.
[in]	cell_offset	OTP cell offset to start programming into.

◆ bsp_otp_prog()

void bsp_otp_prog	(	const uint32_t *	p_data,
		uint32_t	cell_offset,
		uint32_t	num_words
	)

Program data to OTP.

Parameters

[in]	p_data	A pointer to the data to be programmed to OTP. It shall be at least of (num_words * 4) bytes long.
[in]	cell_offset	OTP cell offset to start programming into.
[in]	num_words	Number of words to program to OTP.

◆ bsp_otp_prog_and_verify()

bool bsp_otp_prog_and_verify	(	const uint32_t *	p_data,
		uint32_t	cell_offset,
		uint32_t	num_words
	)

Program data to OTP and verify it has been programmed successfully.

Parameters

[in]	p_data	A pointer to the data to be programmed to OTP. It shall be at least of (num_words * 4) bytes long.
[in]	cell_offset	OTP cell offset to start programming into.
[in]	num_words	Number of words to program to OTP.

◆ bsp_otp_lock()

uint32_t bsp_otp_lock ( uint8_t cell_region )

Lock OTP cell region.

Parameters

[in] cell_region OTP cell region to lock.

Returns: OTP lock region > 0 on success, 0 on failure (invalid cell_region).

◆ bsp_otp_get_lock_region()

uint32_t bsp_otp_get_lock_region ( void )

Get OTP lock region.

Returns: OTP lock region > 0.

◆ bsp_otp_close()

void bsp_otp_close ( void )

Put OTP controller in standby mode and disable it.

◆ bsp_prv_pd_masks_get()

void bsp_prv_pd_masks_get	(	bsp_power_domain_t	power_domain,
		uint32_t *	sleep_mask,
		uint32_t *	is_up_mask
	)

Get the SLEEP/IS_UP register-field masks of a power domain.

Parameters

[in]	power_domain	power domain
[out]	sleep_mask	mask for the power domain's SLEEP status bit
[out]	is_up_mask	mask for the power domain's IS_UP status bit

Note: If power_domain is invalid, 0 is returned for both masks

◆ SystemWakeupSourceUpdate()

BSP_PLACE_CODE_IN_RAM void SystemWakeupSourceUpdate ( void )

Updates the SystemCoreWakeupSource and SystemCoreWakeupSourcePin variables based on the current state of the RTC registers.

◆ R_BSP_WakeupSourceGet()

BSP_PLACE_CODE_IN_RAM bsp_wakeup_source_mask_t R_BSP_WakeupSourceGet ( void )

Gets the wakeup source stored in the SystemCoreWakeupSource variable.

Returns: The wakeup source.

Note: Since the wakeup source may change after booting, the value is stored in SystemCoreWakeupSource during the initialization process (through SystemWakeupSourceUpdate), and it is checked as a static value.

◆ R_BSP_WakeupSourceClear()

void R_BSP_WakeupSourceClear ( bool clear )

Clears the specified wakeup source.

Parameters

[in] clear Boolean indicating whether to clear the wakeup source.

◆ R_BSP_WakeupSourcePinGet()

bsp_io_wakeup_pin_t R_BSP_WakeupSourcePinGet ( void )

Gets the wakeup source pin mask stored in the SystemCoreWakeupSourcePin variable.

Returns: The wakeup pin mask.

Note: Since the wakeup pin may change after booting, the value is stored in SystemCoreWakeupSourcePin during the initialization process (through SystemWakeupSourceUpdate), and it is checked as a static value.

◆ R_BSP_WakeupSourcePinClear()

void R_BSP_WakeupSourcePinClear ( void )

Clears the wakeup source pin mask.

◆ R_BSP_WakeupSourcePinSet()

void R_BSP_WakeupSourcePinSet	(	bsp_io_wakeup_pin_t	pin,
		bsp_io_wakeup_edge_t	edge
	)

Sets the specified GPIO pin as a wakeup source.

Parameters

[in]	pin	The GPIO pin to set as a wakeup source.
[in]	edge	The edge type (active high or active low) for the wakeup source.

◆ R_BSP_WakeupSourcePinSetRetained()

void R_BSP_WakeupSourcePinSetRetained	(	bsp_io_wakeup_pin_t	pin,
		bsp_io_wakeup_edge_t	edge
	)

Sets the specified GPIO pin as a wakeup source.

Parameters

[in]	pin	The GPIO pin to set as a wakeup source.
[in]	edge	The edge type (active high or active low) for the wakeup source.

◆ R_BSP_WakeupSourcePinUnSet()

void R_BSP_WakeupSourcePinUnSet ( bsp_io_wakeup_pin_t pin )

Unsets the specified GPIO pin as a wakeup source.

Parameters

[in] pin The GPIO pin to unset as a wakeup source.

◆ bsp_prv_port_pin_to_wakeup_gpio()

bsp_io_wakeup_pin_t bsp_prv_port_pin_to_wakeup_gpio ( bsp_io_port_pin_t port_pin )

Convert PORT_PIN to WAKEUP_GPIO.

Parameters

[in] port_pin bsp_io_port_pin_t

Returns: bsp_io_wakeup_pin_t

◆ bsp_prv_wakeup_pin_to_port_pin()

bsp_io_port_pin_t bsp_prv_wakeup_pin_to_port_pin ( bsp_io_wakeup_pin_t wakeup_gpio )

Convert WAKEUP_GPIO to PORT_PIN.

Parameters

[in] wakeup_gpio bsp_io_wakeup_pin_t

Returns: bsp_io_port_pin_t

◆ R_BSP_RetainedMemFlagSet()

BSP_PLACE_CODE_IN_RAM void R_BSP_RetainedMemFlagSet ( void )

Sets the retention flag in the RTC register to indicate that retention memory is being used.

Note: During sleep, the RTC register is always on. The software records the status in the RTM_INFO register to indicate whether retention memory is being used. When reading the wakeup source, set RTM_INFO to bit 7 to check this.

◆ R_BSP_RetainedMemFlagClear()

BSP_PLACE_CODE_IN_RAM void R_BSP_RetainedMemFlagClear ( void )

Clears the retention memory flag in the RTC register.

◆ R_BSP_RetainedMemFlagGet()

BSP_PLACE_CODE_IN_RAM uint32_t R_BSP_RetainedMemFlagGet ( void )

Gets the retention memory flag.

Returns: The retention memory flag.

Variable Documentation

◆ BSP_SECTION_EARLY_INIT

uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT

System Clock Frequency (Core Clock)

Functions

Detailed Description

Overview

BSP Features

BSP Clock Configuration

System Interrupts

Group Interrupts

External and Peripheral Interrupts

BSP Weak Symbols

Warm Start Callbacks

\[WIP\] Sub Clock Stabilization Wait Callback

\[WIP\] Sub Clock Stabilization Wait After Reset callback

C Runtime Initialization

Heap Allocation

Error Logging

TrustZone Security Attribution Registers

Software Delay

\[WIP\] Digital Signal Processing With 32-bit Multiply-Accumulator

Critical Section Macros

\[WIP\] Sealing the Main Stack (TrustZone Secure Projects)

\[WIP\] Non-Cacheable Buffer Placement Example

Configuration

Build Time Configurations for fsp_common

Macros

Enumerations

Variables

Macro Definition Documentation

◆ BSP_IRQ_DISABLED

◆ FSP_LOG_PRINT

◆ FSP_RETURN

◆ FSP_ERROR_LOG

◆ FSP_ASSERT

◆ FSP_ERROR_RETURN

◆ BSP_PUSH_SCRATCH_REGISTERS

◆ BSP_GET_SP

◆ BSP_CHECK_DEBUG

◆ BSP_CHECK_FATAL

◆ FSP_REG_VAR_FIELD_GET

◆ FSP_REG_VAR_FIELD_SET

◆ FSP_REG_SET_MASKED

◆ FSP_MEM_GET_MASKED

◆ FSP_REG_ADDR_GET_INDEXED

◆ FSP_REG_FIELD_GET_INDEXED

◆ FSP_MEM_SET_MASKED

◆ FSP_REG_FIELD_SET_BITS32

◆ FSP_REG_MSK

◆ FSP_SWAP32

◆ FSP_SWAP16

◆ FSP_CRITICAL_SECTION_ENTER

◆ FSP_CRITICAL_SECTION_EXIT

◆ FSP_INVALID_VECTOR

◆ BSP_DEBUGGER_ENABLE

◆ BSP_DEBUGGER_DISABLE

◆ BSP_CFG_HANDLE_UNRECOVERABLE_ERROR

◆ BSP_STACK_ALIGNMENT

◆ R_BSP_MODULE_START

◆ R_BSP_MODULE_STOP

Enumeration Type Documentation

◆ bsp_warm_start_event_t

◆ ahb_clk_div_t

◆ fsp_priv_source_clock_t

◆ bsp_delay_units_t

◆ bsp_grp_irq_t

◆ fsp_ip_t

◆ fsp_signal_t

Function Documentation

◆ R_FSP_VersionGet()

◆ Default_Handler()

◆ Reset_Handler()

◆ _exit()

◆ SystemInit()

◆ R_BSP_WarmStart()

◆ R_BSP_SourceClockHzGet()

◆ R_BSP_SourceClockHzSet()

◆ R_FSP_CurrentIrqGet()

◆ bsp_clock_ahb_div_get()

◆ R_FSP_SystemClockHzGet()

◆ R_FSP_ClockDividerGet()

◆ R_BSP_UniqueIdGet()

◆ R_BSP_FlashCacheDisable()