Functions
fsp_err_t	R_SPI_W_Open (spi_ctrl_t p_api_ctrl, spi_cfg_t const const p_cfg)

fsp_err_t	R_SPI_W_Read (spi_ctrl_t const p_api_ctrl, void p_dest, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SPI_W_Write (spi_ctrl_t const p_api_ctrl, void const p_src, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SPI_W_WriteRead (spi_ctrl_t const p_api_ctrl, void const p_src, void *p_dest, uint32_t const length, spi_bit_width_t const bit_width)

fsp_err_t	R_SPI_W_CallbackSet (spi_ctrl_t const p_api_ctrl, void(p_callback)(spi_callback_args_t ), void const p_context, spi_callback_args_t *const p_callback_memory)

fsp_err_t	R_SPI_W_Close (spi_ctrl_t *const p_api_ctrl)

fsp_err_t	R_SPI_W_CalculateBitrate (uint32_t bitrate, uint8_t *spck_div, uint8_t channel)

Detailed Description

Driver for the SPI_W peripheral on RA for Wireless MCUs. This module implements the SPI Interface.

Overview

Features

Standard SPI_W Modes
- Master and slave modes for each SPI channel
- Configurable bitrate with Master clock line speed
- Clock Polarity (CPOL)
  - CPOL=0 SCLK is low when idle
  - CPOL=1 SCLK is high when idle
- Clock Phase (CPHA)
  - CPHA=0 Data is sampled at an odd edge and changes at an even edge
  - CPHA=1 Data changes at an odd edge and is sampled at an even edge
- MSB first
- 4-bit to 32-bit data frames
  - Hardware endian swap in 16-bit and 32-bit modes
- CS level keep (burst transfer) supported if available
- Clock edge to capture data
  - Current
  - Next (Used only for timing adjustments in master mode at high bitrate)
Interrupt generation based on configurable TX or RX FIFO thresholds
Support Full Duplex Mode
DTC Support (RA6B1, RA6W3, RA6U1)
DMAC Support
Callback Events
- Transfer Complete
- RX Overflow Error (The SPI shift register is copied to the data register before previous data was read)

Configuration

Build Time Configurations for r_spi_w

The following build time configurations are defined in fsp_cfg/r_spi_w_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.
Enable Transfer Support for using a transfer API	DTC DMAC Disabled	Disabled	If enabled, transfer instances will be included in the build for both transmission and reception.
Enable Transmitting from Receive Interrupt	Enabled Disabled	Disabled	If enabled, all operations will be handled from the RX (receive) interrupt. This setting only provides a performance boost when neither DTC nor DMAC is used. In addition, Transmit Only mode is not supported when this configuration is enabled.
Enable Fast Read	Enabled Disabled	Disabled	If enabled, R_SPI_W_FastRead() will be included in the build.

Configurations for Connectivity > SPI_W (r_spi_w)

This module can be added to the Stacks tab via New Stack > Connectivity > SPI_W (r_spi_w). Non-secure callable guard functions can be generated for this module by right clicking the module in the RA Configuration tool and checking the "Non-secure Callable" box.

Configuration	Options	Default	Description
Name	Name must be a valid C symbol	g_spi_w0	Module name.
Channel	Value must be an integer greater than 0	1	Select the SPI channel.
Generic Interrupt Priority	MCU Specific Options		Select the generic interrupt priority.
Idle Interrupt Priority	MCU Specific Options		Select the interrupt priority for all SPI interrupts.
Receive Interrupt Priority	MCU Specific Options		Select the receive interrupt priority.
Transmit Buffer Empty Interrupt Priority	MCU Specific Options		Select the transmit buffer empty interrupt priority.
Error Interrupt Priority	MCU Specific Options		Select the interrupt priority for all SPI interrupts.
Operating Mode	Master Slave	Master	Select the SPI operating mode.
Clock Phase	Data sampling on odd edge, data variation on even edge Data sampling on even edge, data variation on odd edge	Data sampling on odd edge, data variation on even edge	Select the clock edge to sample data.
Clock Polarity	Low when idle High when idle	Low when idle	Select clock level when idle.
Mode Fault Error	Disable	Disable	Detect master/slave mode conflicts. Mode fault error is not supported.
Bit Order	MSB First	MSB First	Select the data bit order. LSB First is not supported.
Callback	Name must be a valid C symbol	spi_callback	A user callback function can be provided. If this callback function is provided, it will be called from the interrupt service routine (ISR).
Select Chip(Chip Select)	CS0 CS1	CS0	Select which slave to use.
Byte Swapping	Disable Enable	Disable	Select the byte swap mode for 16/32-Bit Data Frames.
Capture Edge	Current Next	Current	Select clock edge to capture data. If there is an error in the received data in Master mode at high bitrate, it may be improved by setting Next. Otherwise, set Current.
Rx FIFO level	Value must be a non-negative integer	0	Select the SPI Rx FIFO threshold level.
Tx FIFO level	Value must be a non-negative integer	0	Select the SPI Tx FIFO threshold level.
Bitrate	Value must be an integer greater than 0	5000000	Enter the desired bitrate, change the bitrate to a value supported by MCU. If the requested bitrate cannot be achieved, the settings with the largest possible value that is less than or equal to the requested bitrate is used. The theoretical bitrate is printed in a comment in the generated spi_w_extended_cfg_t structure.
Enable skipping SPI disablement.	Enabled Disabled	Disabled	If enabled, SPI will not be disabled after a read/write cycle for fast reaction.
Enable skipping SPI busy checks on read.	Enabled Disabled	Disabled	If enabled, SPI will not check for busy state when reading.

Clock Configuration

(RA6W1/RA6W2) The clock for SPI can be configured via the Clocks tab of the RA6W1/RA6W2 Configuration editor or by using the CGC Interface at run-time.

(RA6B1/RA6W3/RA6U1) The driver's clock for each SPI channel is controlled by DivN, derived from the SYSCLK. You can adjust the clock frequency for each channel by setting the desired bitrate. The driver will automatically compute and set the closest achievable clock frequency to match your specified bitrate. The formula used to calculate the divider value is:

Divider = Input Clock Frequency / Desired Bitrate

This formula ensures efficient operation of the SPI interface at the desired data rate by adjusting the clock frequency appropriately.

Pin Configuration

This module uses SPIn_DO, SPIn_DI, SPIn_CLK, and SPIn_CSm pins to communicate with on board devices.

Note: At high bitrates it may be necessary to configure the pins with IOPORT_CFG_DRIVE_HIGH to maintain signal integrity.

Usage Notes

Performance

At high bitrates, interrupts may not be able to service transfers fast enough. In master mode this means there will be a delay between each data frame. In slave mode this could result in RX Overflow errors.

In order to improve performance at high bitrates, it is recommended that the instance be configured to service transfers using the DTC or DMAC.

Performance can also be improved by changing TX and RX threshold levels or by setting SPI capturing data at next clock edge (Master-Mode only, recommended at high bitrate).

Another way to improve performance is to transfer the data in 16/32 bit wide data frames when possible. A typical use-case where this is possible is when reading/writing to a block device.

Transmit From RXI Interrupt

After every data frame the SPI peripheral generates a transmit buffer empty interrupt and a receive buffer full interrupt. It is possible to configure the driver to handle transmit buffer empty interrupts in the receive buffer full ISR. This only improves performance when neither the DTC nor DMAC is being used.

Note: Configuring the module to use both RX DTC/DMAC instance and TX DTC/DMAC instance or neither the instances is required when transmit from RXI interrupt is enabled. Otherwise, it results in an invalid configuration.

Clock Auto-Stopping

In master mode, if the Receive Buffer Full Interrupts are not handled fast enough, instead of generating a RX Overflow error, the last clock cycle will be stretched until the receive buffer is read.

Parity Mode

No parity mode support in this SPI version.

Limitations

Developers should be aware of the following limitations when using the SPI:

The behavior for Byte Swap operation is not guaranteed for data frames other than 8-bit, 16-bit and 32bit.

Examples

Basic Example

This is a basic example of minimal use of the SPI in an application.

static volatile bool g_transfer_complete = false;
void spi_w_basic_example (void)
{
    uint8_t tx_buffer[TRANSFER_SIZE];
    uint8_t rx_buffer[TRANSFER_SIZE];
    fsp_err_t err = FSP_SUCCESS;
    FSP_PARAMETER_NOT_USED(err);
    /* Initialize the SPI module. */
    err = R_SPI_W_Open(&g_spi_ctrl, &g_spi_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
#ifdef NDEBUG
    (void) err;
#endif
    /* Start a write/read transfer */
    err = R_SPI_W_WriteRead(&g_spi_ctrl, tx_buffer, rx_buffer, TRANSFER_SIZE, SPI_BIT_WIDTH_8_BITS);
    assert(FSP_SUCCESS == err);
    /* Wait for SPI_EVENT_TRANSFER_COMPLETE callback event. */
    while (false == g_transfer_complete)
    {
        ;
    }
}
static void spi_w_callback (spi_callback_args_t * p_args)
{
    if (SPI_EVENT_TRANSFER_COMPLETE == p_args->event)
    {
        g_transfer_complete = true;
    }
}

Configuring the SPI Clock Divider Registers

This example demonstrates how to set the SPI clock divisors at runtime.

void spi_w_bitrate_example (void)
{
    fsp_err_t err = FSP_SUCCESS;
    FSP_PARAMETER_NOT_USED(err);
    g_spi_cfg.p_extend = &g_spi_extended_cfg;
    /* Configure SPI Clock divider to achieve largest bitrate less than or equal to the desired bitrate. */
    err = R_SPI_W_CalculateBitrate(BITRATE, &(g_spi_extended_cfg.spck_div), g_spi_cfg.channel);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
#ifdef NDEBUG
    (void) err;
#endif
    /* Initialize the SPI module. */
    err = R_SPI_W_Open(&g_spi_ctrl, &g_spi_cfg);
    /* Handle any errors. This function should be defined by the user. */
    assert(FSP_SUCCESS == err);
}

Data Structures
struct	spi_w_extended_cfg_t

struct	spi_w_instance_ctrl_t

Macros
#define	SPI_W_RX_FIFO_MAX_SIZE_BYTE

Enumerations
enum	spi_w_cs_select_t

enum	spi_w_byte_swap_t

enum	spi_w_capture_edge_t

Data Structure Documentation

◆ spi_w_extended_cfg_t

struct spi_w_extended_cfg_t

Extended SPI interface configuration

Data Fields
spi_w_cs_select_t	cs_select	Select which slave to use: 0-CS0, 1-CS1.
spi_w_byte_swap_t	byte_swap	Select byte swap mode.
spi_w_capture_edge_t	cap_edge	Select capture clock edge.
uint32_t	rx_fifo_lvl_thres	Set fifo level threshold for rx.
uint32_t	tx_fifo_lvl_thres	Set fifo level threshold for tx.
uint8_t	spck_div	Register value for configuring the SPI Clock Divider.
uint8_t	gen_ipl	Generic interrupt priority.
IRQn_Type	gen_irq	Generic interrrupt IRQ number.
bool	skip_busy_check	If true, SPI will not check for busy state on read.

◆ spi_w_instance_ctrl_t

struct spi_w_instance_ctrl_t

Channel control block. DO NOT INITIALIZE. Initialization occurs when spi_api_t::open is called.

Data Fields
uint32_t	open
	Indicates whether the open() API has been successfully called.

spi_cfg_t const *	p_cfg
	Pointer to instance configuration.

SPI_Type *	p_regs
	Base register for this channel.

void const *	p_tx_data
	Buffer to transmit.

void *	p_rx_data
	Buffer to receive.

uint32_t	tx_count
	Number of Data Frames to transmit (8-bit, 16-bit, 32-bit).

uint32_t	rx_count
	Number of Data Frames to receive (8-bit, 16-bit, 32-bit).

uint32_t	count
	Number of Data Frames to transfer (8-bit, 16-bit, 32-bit).

spi_bit_width_t	bit_width
	Bits per Data frame.

uint32_t	mask_width
	Bit width mask for data.

uint8_t	wordsize
	Word size of current transmit.

Macro Definition Documentation

◆ SPI_W_RX_FIFO_MAX_SIZE_BYTE

#define SPI_W_RX_FIFO_MAX_SIZE_BYTE

Offset to make the SPI HW channels 0-based for the r_spi driver.

Enumeration Type Documentation

◆ spi_w_cs_select_t

enum spi_w_cs_select_t

The Chip Select Line.

Enumerator
SPI_W_CS_SELECT_CS0	Select CS0.
SPI_W_CS_SELECT_CS1	Select CS1.

◆ spi_w_byte_swap_t

enum spi_w_byte_swap_t

Byte Swapping Enable/Disable.

Enumerator
SPI_W_BYTE_SWAP_DISABLE	Disable Byte swapping for 16/32-Bit transfers.
SPI_W_BYTE_SWAP_ENABLE	Enable Byte swapping for 16/32-Bit transfers.

◆ spi_w_capture_edge_t

enum spi_w_capture_edge_t

Capture data at current/next clock edge.

Enumerator
SPI_W_CAPTURE_CURRENT_EDGE	SPI captures data at current clock edge.
SPI_W_CAPTURE_NEXT_EDGE	SPI captures data at next clock edge. (only for Master mode & high bitrate).

Function Documentation

◆ R_SPI_W_Open()

fsp_err_t R_SPI_W_Open	(	spi_ctrl_t *	p_api_ctrl,
		spi_cfg_t const *const	p_cfg
	)

This functions initializes a channel for SPI communication mode. Implements spi_api_t::open.

This function performs the following tasks:

Performs parameter checking and processes error conditions.
Configures the peripheral registers according to the configuration.
Initialize the control structure for use in other SPI Interface functions.

Parameters

[in]	p_api_ctrl	Pointer to the instance control structure.
[in]	p_cfg	Configuration structure which contains all the user provided configurations.

Return values

FSP_SUCCESS	Channel initialized successfully.
FSP_ERR_ALREADY_OPEN	Instance was already initialized.
FSP_ERR_ASSERTION	An invalid argument was given in the configuration structure.
FSP_ERR_UNSUPPORTED	A requested setting is not possible on this device with the current build configuration.
FSP_ERR_IP_CHANNEL_NOT_PRESENT	The channel number is invalid.

Returns: See Common Error Codes or functions called by this function for other possible return codes. This function calls: transfer_api_t::open

Note: This function is reentrant.

◆ R_SPI_W_Read()

fsp_err_t R_SPI_W_Read	(	spi_ctrl_t *const	p_api_ctrl,
		void *	p_dest,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

This function receives data from a SPI device. Implements spi_api_t::read.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Sets up the instance to complete a SPI read operation.

Parameters

[in]	p_api_ctrl	Pointer to the instance control structure.
[out]	p_dest	Reference to receiving buffer.
[in]	length	No of transfers.
[in]	bit_width	Data frame width.

Return values

FSP_SUCCESS	Read operation successfully completed.
FSP_ERR_ASSERTION	NULL pointer to control or destination parameters or transfer length is zero.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open channel first.
FSP_ERR_IN_USE	A transfer is already in progress.

◆ R_SPI_W_Write()

fsp_err_t R_SPI_W_Write	(	spi_ctrl_t *const	p_api_ctrl,
		void const *	p_src,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

This function transmits data to a SPI device. Implements spi_api_t::write.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Sets up the instance to complete a SPI write operation.

Parameters

[in]	p_api_ctrl	Pointer to the instance control structure.
[in]	p_src	Reference to transmitting buffer.
[in]	length	No of transfers.
[in]	bit_width	Data frame width.

Return values

FSP_SUCCESS	Write operation successfully completed.
FSP_ERR_ASSERTION	NULL pointer to control or source parameters or transfer length is zero.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_IN_USE	A transfer is already in progress.

◆ R_SPI_W_WriteRead()

fsp_err_t R_SPI_W_WriteRead	(	spi_ctrl_t *const	p_api_ctrl,
		void const *	p_src,
		void *	p_dest,
		uint32_t const	length,
		spi_bit_width_t const	bit_width
	)

This function simultaneously transmits and receive data. Implements spi_api_t::writeRead.

The function performs the following tasks:

Performs parameter checking and processes error conditions.
Sets up the instance to complete a SPI writeRead operation.

Parameters

[in]	p_api_ctrl	Pointer to the instance control structure.
[in]	p_src	Reference to transmitting buffer.
[out]	p_dest	Reference to receiving buffer.
[in]	length	No of transfers.
[in]	bit_width	Data frame width.

Return values

FSP_SUCCESS	WriteRead operation successfully completed.
FSP_ERR_ASSERTION	NULL pointer to control, source or destination parameters or transfer length is zero.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.
FSP_ERR_IN_USE	A transfer is already in progress.

◆ R_SPI_W_CallbackSet()

fsp_err_t R_SPI_W_CallbackSet	(	spi_ctrl_t *const	p_api_ctrl,
		void()(spi_callback_args_t )	p_callback,
		void *const	p_context,
		spi_callback_args_t *const	p_callback_memory
	)

Updates the user callback and has option of providing memory for callback structure. Implements spi_api_t::callbackSet

Parameters

[in]	p_api_ctrl	Pointer to the instance control structure.
[in]	p_callback	Pointer to user callback function.
[in]	p_context	User defined context passed to callback function.
[in]	p_callback_memory	Pointer to volatile memory where callback structure can be allocated.

Return values

FSP_SUCCESS	Callback updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	The control block has not been opened.

◆ R_SPI_W_Close()

fsp_err_t R_SPI_W_Close ( spi_ctrl_t *const p_api_ctrl )

This function manages the closing of a channel by the following task. Implements spi_api_t::close.

Disables SPI operations by disabling the SPI bus.

Disables the SPI peripheral.
Disables all the associated interrupts.
Update control structure so it will not work with SPI Interface functions.

Parameters

[in] p_api_ctrl Pointer to the instance control structure.

Return values

FSP_SUCCESS	Channel successfully closed.
FSP_ERR_ASSERTION	A required pointer argument is NULL.
FSP_ERR_NOT_OPEN	The channel has not been opened. Open the channel first.

◆ R_SPI_W_CalculateBitrate()

fsp_err_t R_SPI_W_CalculateBitrate	(	uint32_t	bitrate,
		uint8_t *	spck_div,
		uint8_t	channel
	)

Calculates the SPI_CLOCK_REG register value (the closest quantized value) for a desired bitrate. If the desired bitrate is faster than the maximum bitrate, then the bitrate is set to the maximum bitrate. If the desired bitrate is slower than the minimum bitrate, an error is returned.

Parameters

[in]	bitrate	Desired bitrate.
[out]	spck_div	Memory location to store bitrate register settings.
[in]	channel	Selected channel.

Return values

FSP_SUCCESS	Valid clkdiv value was calculated.
FSP_ERR_UNSUPPORTED	Bitrate is not achievable.

Functions

Detailed Description

Overview

Features

Configuration

Build Time Configurations for r_spi_w

Configurations for Connectivity > SPI_W (r_spi_w)

Clock Configuration

Pin Configuration

Usage Notes

Performance

Transmit From RXI Interrupt

Clock Auto-Stopping

Parity Mode

Limitations

Examples

Basic Example

Configuring the SPI Clock Divider Registers

Data Structures

Macros

Enumerations

Data Structure Documentation

◆ spi_w_extended_cfg_t

◆ spi_w_instance_ctrl_t

Data Fields

Macro Definition Documentation

◆ SPI_W_RX_FIFO_MAX_SIZE_BYTE

Enumeration Type Documentation

◆ spi_w_cs_select_t

◆ spi_w_byte_swap_t

◆ spi_w_capture_edge_t

Function Documentation

◆ R_SPI_W_Open()

◆ R_SPI_W_Read()

◆ R_SPI_W_Write()

◆ R_SPI_W_WriteRead()

◆ R_SPI_W_CallbackSet()

◆ R_SPI_W_Close()

◆ R_SPI_W_CalculateBitrate()