RA6W1

Detailed Description

Build Time Configurations for ra6w1_fsp

The following build time configurations are defined in fsp_cfg/bsp/bsp_mcu_family_cfg.h:

Configuration	Options	Default	Description
Security
Security > Exceptions
Exception Response	Non-Maskable Interrupt Reset	Non-Maskable Interrupt	Configure the result of a TrustZone Filter exception. This exception is generated when a the TrustZone Filter detects access to a protected region. This setting is only valid when building projects with TrustZone.
BusFault, HardFault, and NMI Target	Non-Secure State Secure State	Secure State	Value for SCB->AIRCR register bit BFHFNMINS. Defines whether BusFault and NMI exceptions are Non-secure, and whether exceptions target the Non-secure HardFault exception. This setting is only valid when building projects with TrustZone.
Prioritize Secure Exceptions	Enabled Disabled	Disabled	Value for SCB->AIRCR register bit PRIS. When enabled, all Non-secure interrupt priorities are automatically demoted by right shifting their priority by one then setting the most significant bit. As there is effectively one less bit care must be taken to ensure the prioritization of non-secure interrupts is correct. This setting is only valid when building projects with TrustZone.
Security > SRAM Accessibility
SRAM Protection	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether SRAMPRCR is write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
SRAM ECC	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether SRAM ECC registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Standby RAM	Regions 7-0 are all Secure. Region 7 is Non-secure. Regions 6-0 are Secure. Regions 7-6 are Non-secure. Regions 5-0 are Secure. Regions 7-5 are Non-secure. Regions 4-0 are Secure. Regions 7-4 are Non-secure. Regions 3-0 are Secure. Regions 7-3 are Non-secure. Regions 2-0 are Secure. Regions 7-2 are Non-secure. Regions 1-0 are Secure. Regions 7-1 are Non-secure. Region 0 is Secure. Regions 7-0 are all Non-secure.	config.bsp.fsp.tz.stbramsar.both	Defines whether Standby RAM registers are accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Security > BUS Accessibility
Bus Security Attribution Register A	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Slave Bus Control Registers (BUSSCNT<slave>) are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
Bus Security Attribution Register B	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Bus and DMAC/DTC Error Clear Registers are write accessible for the Non-secure application. This setting is only valid when building projects with TrustZone.
System Reset Request Accessibility	Both Secure and Non-Secure State Secure State	Secure State	Value for SCB->AIRCR register bit SYSRESETREQS. Defines whether the SYSRESETREQ bit is functional for Non-secure use. This setting is only valid when building projects with TrustZone.
Cache Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the Cache registers are write accessible for the Non-secure application. This setting is only valid when building protjects with TrustZone.
System Reset Status Accessibility	Both Secure and Non-Secure State Secure State	Both Secure and Non-Secure State	Defines whether the reset status registers (RSTSRn) can be cleared from the Non-secure application. This setting is only valid when building projects with TrustZone.
Uninitialized Non-Secure Application Fallback	Enable Uninitialized Non-Secure Application Fallback Disable Uninitialized Non-Secure Application Fallback	Enable Uninitialized Non-Secure Application Fallback	If enabled, the secure application checks if the non-secure application has been programmed in non-secure flash before branching. If the non-secure application has not been programmed, then the secure application branches to an infinite loop in non-secure RAM. This prevents an issue where the debugger may not connect if the MCU is configured in the NSECSD lifecycle state.
General
Copy IVT to SRAM	Disable	Disable	Enable allows for the copying of the IVT to the start of SRAM and the update of VTOR.
Use Radio clock manager	Enable Disable	Disable	Defines whether the use of clock manager should be enabled or disabled for Radio
Enable XTAL PPM compensation	Enable Disable	Disable	Defines whether temperature-driven XTAL PPM compensation is enabled for ATE TX flows.
XTAL PPM recompensation period (ms)	Manual Entry	8000U	Defines the recompensation interval in milliseconds while long-running ATE TX commands are active.
8-lines OQSPI support	Enable Disable	Disable	Defines whether OQSPI can operate at full 8-lines configuration and use PIN1_00-PIN1_03 as OQSPI D7-D4 or not (default). If disabled OQSPI can operate only at 4-lines mode, PIN1_00-PIN1_03 in this case are working as regular GPIOs.

Enumerations
enum	bsp_io_clk_output_t
enum	bsp_io_clk_func_t

Enumeration Type Documentation

bsp_io_clk_output_t

enum bsp_io_clk_output_t

Clocks that can be mapped to dedicated BSP_IO

Enumerator
BSP_IO_CLK_XTAL40M_OUT	Map clock XTAL40M to dedicated GPIO
BSP_IO_CLK_RC10M_OUT	Map clock RC10M to dedicated GPIO
BSP_IO_CLK_XTAL32K_OUT	Map clock XTAL32K to dedicated GPIO
BSP_IO_CLK_OSC32K_OUT	Map clock OSC32K to dedicated GPIO
BSP_IO_CLK_FPLL98M_OUT	Map clock FPLL98M to dedicated GPIO
BSP_IO_CLK_DPLL480M_OUT	Map clock FPLL98M to dedicated GPIO
BSP_IO_CLK_MCLK_OUT	Map clock MCLK to dedicated GPIO

bsp_io_clk_func_t

enum bsp_io_clk_func_t

Clocks that can be mapped to GPIO function FUNC_CLOCK

Enumerator
BSP_IO_CLK_XTAL40M_FUNC	Map clock XTAL40M to GPIO function FUNC_CLOCK
BSP_IO_CLK_RC10M_FUNC	Map clock RC10M to GPIO function FUNC_CLOCK
BSP_IO_CLK_XTAL32K_FUNC	Map clock XTAL32K to GPIO function FUNC_CLOCK
BSP_IO_CLK_OSC32K_FUNC	Map clock OSC32K to GPIO function FUNC_CLOCK
BSP_IO_CLK_FPLL98M_FUNC	Map clock FPLL98M to GPIO function FUNC_CLOCK
BSP_IO_CLK_DPLL480M_FUNC	Map clock DPLL480M to GPIO function FUNC_CLOCK
BSP_IO_CLK_DIVN_FUNC	Map clock DIVn to GPIO function FUNC_CLOCK