OSPI_W (r_ospi_w)

Functions
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_DirectWrite (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint32_t const bytes, bool const read_after_write)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_DirectRead (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_dest, uint32_t const bytes)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_DirectTransfer (spi_flash_ctrl_t *p_ctrl, spi_flash_direct_transfer_t *const p_transfer, spi_flash_direct_transfer_dir_t direction)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_XipEnter (spi_flash_ctrl_t *p_ctrl)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_XipExit (spi_flash_ctrl_t *p_ctrl)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_Write (spi_flash_ctrl_t *p_ctrl, uint8_t const *const p_src, uint8_t *const p_dest, uint32_t byte_count)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_Erase (spi_flash_ctrl_t *p_ctrl, uint8_t *const p_device_address, uint32_t byte_count)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_StatusGet (spi_flash_ctrl_t *p_ctrl, spi_flash_status_t *const p_status)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_BankSet (spi_flash_ctrl_t *p_ctrl, uint32_t bank)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_SpiProtocolSet (spi_flash_ctrl_t *p_ctrl, spi_flash_protocol_t spi_protocol)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_AutoCalibrate (spi_flash_ctrl_t *p_ctrl)
BSP_PLACE_CODE_IN_RAM fsp_err_t	R_OSPI_W_Close (spi_flash_ctrl_t *p_ctrl)

Detailed Description

Driver for the OSPI peripheral on RRQ MCUs. This module implements the SPI Flash Interface.

Overview

Features

The OSPI driver has the following key features:

• Memory mapped read access to the OSPI flash
• Programming the OSPI flash device
• Erasing the OSPI flash device
• Sending device specific commands and reading back responses
• Entering and exiting QPI mode
• Entering and exiting XIP mode
• 3 or 4 byte addressing

Configuration

Build Time Configurations for r_ospi_w

The following build time configurations are defined in fsp_cfg/r_ospi_w_cfg.h:

Configuration	Options	Default	Description
Parameter Checking	Default (BSP) Enabled Disabled	Default (BSP)	If selected code for parameter checking is included in the build.

Configurations for Storage > OSPI FLASH (r_ospi_w)

This module can be added to the Stacks tab via New Stack > Storage > OSPI FLASH (r_ospi_w).

Configuration	Options	Default	Description
General
Name	Name must be a valid C symbol	g_ospi_w0	Module name.
Channel	Value must be a non-negative integer	0	Module Channel.
Address Bytes	3 4	3	Select the number of address bytes. Selecting '4 with 4-byte read code' converts the default read code determined in Read Mode to the 4-byte version. If 4-byte mode is selected without using 4-byte commands, the application must issue the EN4B command using R_OSPI_W_Direct().
Page Size Bytes	Must be an integer greater than 0	256	The maximum number of bytes allowed for a single write.
Select Mode	MCU Specific Options		Select OSPI Mode.
Drive Current	MCU Specific Options		Set the Drive Strength of the OSPI Controller.
Slew Rate	MCU Specific Options		Set the Slew Rate of the OSPI Controller.
SPI Clock Mode	Low High	High	Select the polarity of OSPI_W_CLK when OSPI_W_CS is high.
Wrap Mode	MCU Specific Options		Select if Wrapping Burst is enabled.
Memory Burst Length	MCU Specific Options		Set the external memory burst length of the OSPI Controller.
Instructions Bus Lines	1 4	1	Select the number of lines to use for instructions during operations. This can be determined by referencing the datasheet for the external flash. It should either be 1 or match the number of data lines used for memory mapped fast read operations.
Address and Data Bus Lines	1 2 4	4	Select the number of lines to use for the address and data bytes during operations. This can be determined by referencing the datasheet for the external flash. It should either be 1 or match the number of data lines used for memory mapped fast read operations.
Flash Boot Configuration Command
Flash Boot Configuration Command > Command definition
Flash Boot Configuration Command > Command definition > Command0
Opcode	Must be an 8-bit command under Command Definitions	0x31	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x02	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	2	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command1
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command2
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command3
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command4
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command5
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command6
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Flash Boot Configuration Command > Command definition > Command7
Opcode	Must be an 8-bit command under Command Definitions	0x00	An operation code for a command sent to the FLASH connected at boot time.
Data0-3	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (0–3 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Data4-7	Must be an 8-bit array and 4 bytes or less in size.	0x00	Command data (4–7 bytes). These are byte arrays, not integers. Example: 0x001234 -> [0x00, 0x12, 0x34], 0x001 -> [0x00, 0x01].
Opcode+Data Length	The valid range is 0 to 9.	0	Number of command bytes to be send to the FLASH.(Opcode+Data) If set to 0, this command is disabled.
Command Definitions
Command Definitions > Read Command
Read Mode Opcode	Must be an integer between 0 and 255	0xEB	Select the read mode for memory mapped access.
Read Mode Wrapping Burst Opcode	Must be an integer between 0 and 255	0	Enter the read opcode for wrapping burst memory mapped access.
Extra Byte Value	Must be an integer between 0 and 255	0xFF	Enter the value for the extra byte. The extra byte value is overwritten by the XIP Enter and XIP Exit commands when the xipEnter and xipExit APIs are called.
Extra Byte Enable	Disabled Enabled	Enabled	Enable the transmission of the extra byte.
CS High Minimum Cycles	Must be an integer between 0 and 31	1	Between the transmissions of two different instructions to the memory device, the SPI bus stays in idle state (OSPI_CS high) for at least this number of OSPI_SCK clock cycles.
Dummy Clocks	MCU Specific Options		Select the number of dummy clocks including extra byte for fast read operations.
Instruction Mode	TX Instr At Any Burst Access TX Instr Only At First Access (Enter XIP mode by default)	TX Instr Only At First Access (Enter XIP mode by default)	Select whether you want to transmit instruction at any burst access or only in the first access after the selection of Auto Mode.
Length of Wrapping Burst	MCU Specific Options		Select Length of Wrapping Burst.
Data Size of Wrapping Burst	MCU Specific Options		Select Data Size of Wrapping Burst.
Command Definitions > Page Program Command
Page Program Command Opcode	Must be an integer between 0 and 255	0x32	The command to program a page. If 'Support Multiple Line Program in Extended SPI Mode' is Enabled, this command must use the same number of data lines as the selected read mode.
Page Program Command Wrapping Burst Opcode	Must be an integer between 0 and 255	0	Enter the page program opcode for wrapping burst memory mapped access.
Address Lines	1 2 4	1	Select the number of lines to use for the address bytes during page program operations.
Dummy Clock Lines	1 2 4	1	Select the number of lines to use for the dummy clock during page program operations.
Data Lines	1 2 4	4	Select the number of lines to use for the data bytes during page program operations.
CS High Minimum Cycles	Must be an integer between 0 and 31	1	After the execution of the write command, the OSPI_CS remains high for at least this number of OSPI_SCK clock cycles.
Dummy Clocks	MCU Specific Options		Select the number of dummy clocks for page program operations.
Command Definitions > Status Command
Opcode	Must be an integer between 0 and 255	0x05	The command to query the status of a write or erase command.
Write Status Bit Pos	Must be an integer between 0 and 7	0	Which bit contains the write in progress status returned from the Write Status Command.
Write Status Level	0 1	1	Select the Write Status bit value indicating a busy state.
Command Definitions > Write Enable Command
Opcode	Must be an integer between 0 and 255	0x06	The command to enable write.
Write Enable Bit Pos	Must be an integer between 0 and 7	1	This bit will wait until the write data to be available before to start sending the write command sequence.
Command Definitions > Erase Command
Sector Erase Opcode	Must be an integer between 0 and 255	0x20	The command to erase a sector. Set Sector Erase Size to 0 if unused.
Sector Erase Size	Must be an integer greater than or equal to 0	4096	The sector erase size. Set Sector Erase Size to 0 if Sector Erase is not supported.
Block Erase Opcode	Must be an integer between 0 and 255	0xD8	The command to erase a block. Set Block Erase Size to 0 if unused.
Block Erase Size	Must be an integer greater than or equal to 0	65536	The block erase size. Set Block Erase Size to 0 if Block Erase is not supported.
Block Erase 32KB Opcode	Must be an integer between 0 and 255	0x52	The command to erase a 32KB block. Set Block Erase Size to 0 if unused.
Block Erase 32KB Size	Must be an integer greater than or equal to 0	32768	The block erase 32KB size. Set Block Erase 32KB Size to 0 if Block Erase 32KB is not supported.
Chip Erase Opcode	Must be an integer between 0 and 255	0xC7	The command to erase the entire chip. Set Chip Erase Command to 0 if unused.
Command Definitions > XIP Command
Enter Command	Must be an integer between 0 and 255	0xA5	How to set M7-M0 to enter XIP mode.
Exit Command	Must be an integer between 0 and 255	0xFF	How to set M7-M0 exit XIP mode.
Command Definitions > QPI Command
QPI Enter Opcode	Must be an 8-bit OSPI QPI Enter command under Command Definitions	0x38	The command to enter QPI mode.
QPI Exit Opcode	Must be an 8-bit OSPI QPI Exit command under Command Definitions	0xFF	The command to exit QPI mode.

Clock Configuration

The OSPI clock is derived from SYS_CLK.

Pin Configuration

The following pins are available to connect to an external OSPI device:

• OSPICLK: OSPI clock output
• OSPICS: OSPI Chip select
• OSPID0: Data 0 I/O
• OSPID1: Data 1 I/O
• OSPID2: Data 2 I/O
• OSPID3: Data 3 I/O
• OSPID4: Data 4 I/O
• OSPID5: Data 5 I/O
• OSPID6: Data 6 I/O
• OSPID7: Data 7 I/O

Usage Notes

OSPI Memory Mapped Access

The contents of the external flash device are mapped to the address defined by BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS and can be read.

Limitations

The OSPI driver does not support Octa flash yet. It supports QSPI and SPI flash.

Examples

Basic Example

This is a basic example of minimal use of the OSPI in an application.

void r_ospi_w_basic_example (void)
{

    /* Open the OSPI instance. */
    fsp_err_t err = R_OSPI_W_Open(&g_ospi0_ctrl, &g_ospi0_cfg);

    assert(FSP_SUCCESS == err);

    /* (Optional) Send device specific initialization commands. */
    r_ospi_w_example_init();

    FSP_PARAMETER_NOT_USED(err);
}

Initialization Command Structure Example

This is an example of the types of commands that can be used to initialize the OSPI.

#define OSPI_W_COMMAND_WRITE_ENABLE             (0x06U)
#define OSPI_W_COMMAND_WRITE_STATUS_REGISTER    (0x01U)

#define OSPI_W_EXAMPLE_STATUS_REGISTER_1        (0x40)
#define OSPI_W_EXAMPLE_STATUS_REGISTER_2        (0x00)

static void r_ospi_w_example_init (void)
{
    fsp_err_t err;

    /* Write status registers */
    /* Write one byte to enable writing to the status register, then deassert CS. */
    spi_flash_direct_transfer_t transfer = { 0 };
    transfer.command_length = 1;
    transfer.command        = OSPI_W_COMMAND_WRITE_ENABLE;
    err                     = R_OSPI_W_DirectTransfer(&g_ospi0_ctrl, &transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    assert(FSP_SUCCESS == err);

    /* Write 3 bytes, including the write status register command followed by values for both status registers. In the
     * status registers, set QE to 1 and other bits to their default setting. After all data is written, deassert the
     * CS line. */
    transfer.command_length = 1;
    transfer.command        = OSPI_W_COMMAND_WRITE_STATUS_REGISTER;
    transfer.data_length    = 2;
    transfer.data           = OSPI_W_EXAMPLE_STATUS_REGISTER_1 | (OSPI_W_EXAMPLE_STATUS_REGISTER_2 << 8);
    err                     = R_OSPI_W_DirectTransfer(&g_ospi0_ctrl, &transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_WRITE);
    assert(FSP_SUCCESS == err);

    FSP_PARAMETER_NOT_USED(err);
}

Reading Status Register Example (R_OSPI_W_DirectTransfer)

This is an example of using R_OSPI_W_DirectTransfer to send the read status register command and read back the status register from the device.

#define OSPI_W_COMMAND_READ_STATUS_REGISTER    (0x05U)

void r_ospi_w_direct_example (void)
{
    /* Read a status register. */

    /* Write 1-byte command and read 1-byte data to read the status register. */
    spi_flash_direct_transfer_t transfer = { 0 };
    fsp_err_t                   err;
    transfer.command_length = 1;
    transfer.command        = OSPI_W_COMMAND_READ_STATUS_REGISTER;
    transfer.data_length    = 1;
    err                     = R_OSPI_W_DirectTransfer(&g_ospi0_ctrl, &transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    /* Status register contents are available in variable 'transfer.data'. */
    FSP_PARAMETER_NOT_USED(err);
}

Querying Device Size Example (R_OSPI_W_DirectWrite, R_OSPI_W_DirectRead)

This is an example of using R_OSPI_W_DirectTransfer to query the device size.

#define OSPI_W_EXAMPLE_COMMAND_READ_ID      (0x9F)

void r_ospi_w_size_example (void)
{
    /* Many OSPI devices support more than one way to query the device size. Consult the datasheet for your
     * OSPI device to determine which of these methods are supported (if any). */
    uint32_t  device_size_bytes;
    fsp_err_t err;

#ifdef OSPI_W_EXAMPLE_COMMAND_READ_ID
    /* This example shows how to get the device size by reading the manufacturer ID.
       Read 3 bytes. The third byte often represents the size of the OSPI, where the size of the OSPI = 2 ^ N. */
    spi_flash_direct_transfer_t transfer = { 0 };
    transfer.command_length = 1;
    transfer.command        = OSPI_W_EXAMPLE_COMMAND_READ_ID;
    transfer.data_length    = 3;
    err                     = R_OSPI_W_DirectTransfer(&g_ospi0_ctrl, &transfer, SPI_FLASH_DIRECT_TRANSFER_DIR_READ);
    assert(FSP_SUCCESS == err);

    device_size_bytes = 1U << ((transfer.data >> 16) & 0xFF);
#endif

    FSP_PARAMETER_NOT_USED(device_size_bytes);
    FSP_PARAMETER_NOT_USED(err);
}

Data Structures
struct	ospi_w_read_instr_cfg_t
struct	ospi_w_read_status_instr_cfg_t
struct	ospi_w_erase_instr_cfg_t
struct	ospi_w_suspend_resume_instr_cfg_t
struct	ospi_w_break_instr_cfg_t
struct	ospi_w_memblen_cfg_t
struct	ospi_w_write_instr_cfg_t
struct	ospi_w_write_enable_instr_cfg_t
struct	ospi_w_ctrl_ddr_cfg_t
struct	ospi_w_extra_registers_cfg_t
struct	ospi_w_qpi_instr_cfg_t
struct	ospi_w_flash_cfg_t
struct	ospi_w_extended_cfg_t
struct	ospi_w_instance_ctrl_t

Enumerations
enum	ospi_w_access_mode_t
enum	ospi_w_bus_mode_t
enum	ospi_w_clk_div_t
enum	ospi_w_ers_t
enum	ospi_w_clk_mode_t
enum	ospi_w_drive_current_t
enum	ospi_w_read_pipe_t
enum	ospi_w_read_pipe_delay_t
enum	ospi_w_slew_rate_t
enum	ospi_w_hready_mode_t
enum	ospi_w_instr_md_t
enum	ospi_w_wrap_md_t
enum	ospi_w_wrap_wr_en_t
enum	ospi_w_rd_bend_md_t
enum	ospi_w_rd_rdb_en_t
enum	ospi_w_extra_byte_t
enum	ospi_w_extra_byte_half_t
enum	ospi_w_break_t
enum	ospi_w_break_sec_hf_t
enum	ospi_w_t_cem_t
enum	ospi_w_memblen_burst_t
enum	ospi_w_sampling_edge_t
enum	ospi_w_mode_t
enum	ospi_w_busy_level_t
enum	ospi_w_stsdly_sel_t
enum	ospi_w_dummy_value_t
enum	ospi_w_idx_bus_mode_t

---

Data Structure Documentation

ospi_w_read_instr_cfg_t

struct ospi_w_read_instr_cfg_t

Read instruction configuration structure (auto access mode).

Data Fields
uint8_t	opcode	Read command opcode for Incremental Burst or Single read access.
uint8_t	opcode_wb	Read command opcode for Wrapping Burst.
uint8_t	extra_byte_value	Extra Byte value.
ospi_w_bus_mode_t	opcode_bus_mode: 2	Bus mode of the opcode phase.
ospi_w_bus_mode_t	addr_bus_mode: 2	Bus mode of the address phase.
ospi_w_bus_mode_t	extra_byte_bus_mode: 2	Bus mode of the extra byte phase.
ospi_w_bus_mode_t	dummy_bus_mode: 2	Bus mode of the dummy phase.
ospi_w_bus_mode_t	data_bus_mode: 2	Bus mode of the data phase.
ospi_w_extra_byte_t	extra_byte_en: 1	Enable Extra Byte.
ospi_w_extra_byte_half_t	extra_byte_half_cfg: 1	Enable Extra Byte Half.
uint8_t	dummy_bytes: 5	The number of dummy bytes. Valid values are 0..31 i.e. 1..32 dummy bytes.
bool	dummy_en	Enable dummy bytes.
ospi_w_instr_md_t	instr_md: 1	Instruction mode.
ospi_w_wrap_md_t	wrap_md: 1	Wrap mode enable bit.
uint8_t	wrap_blen: 3	It describes the length in number of bytes of the selected wrapping burst(see also the register OSPIC_WRAP_MD).
uint8_t	wrap_size: 2	Selected data size of a wrapping burst.
ospi_w_wrap_wr_en_t	wrap_wr_en: 1	By setting (1) this bit, any write wrapping burst will be implemented by using a special write instruction.
uint8_t	cs_high_min_cycles: 5	The SPI bus stays in idle state (OSPI_CS high) for at least this number of OSPI_SCK clock cycles between two consecutive read commands.
ospi_w_rd_bend_md_t	rd_bend_md: 1	Defines the behavior of the controller when a read burst is terminated early in the AMBA bus.
ospi_w_rd_rdb_en_t	rd_rdb_en: 1	Write 1 to set the read pipeline in burst mode while are retrieved the data of the memory device.

ospi_w_read_status_instr_cfg_t

struct ospi_w_read_status_instr_cfg_t

OSPIF read status instruction configuration structure (auto access mode).

Data Fields
uint8_t	opcode	Read Status command opcode.
ospi_w_bus_mode_t	opcode_bus_mode: 2	The bus mode of the opcode phase.
ospi_w_bus_mode_t	receive_bus_mode: 2	The bus mode of the receive data phase.
uint32_t	busy_pos: 3	The position of the Busy bit in the status register (0 - 7).
uint8_t	delay_cycles: 7	The minimum delay in clock cycles between a Read Status command and the previous Erase command. Usually NOT needed thus is set equal to 0.
ospi_w_stsdly_sel_t	stsdly_sel: 1	Select the timer which is used to count the delay before reading the flash status register, after an erase or an erase resume command.
ospi_w_busy_level_t	busy_level: 1	Busy bit level.
uint8_t	rstat_dmy_num: 4	Number of dummy bytes (minus 1).
ospi_w_bus_mode_t	dummy_bus_mode: 2	The bus mode of the dummy data phase.
ospi_w_dummy_value_t	dummy_value: 1	Define the value that is transferred on the SPI bus during the phase of the dummy bytes.
bool	rstat_dmy_en	Enables the transmission of dummy bytes, immediately after the instruction code of the read status command.
bool	rstat_rdb_en	If enabled, sets the read pipeline in burst mode while is retrieved the status of the memory device.
bool	rstat_split_en	If enabled, a long sequence for the continuous reading of the status register will be divided into individual accesses.
bool	rstat_req	If enabled, the value of the status register of the memory device will be retrieved.

ospi_w_erase_instr_cfg_t

struct ospi_w_erase_instr_cfg_t

OSPIF Erase instruction configuration structure (auto access mode).

Data Fields
ospi_w_bus_mode_t	opcode_bus_mode: 2	Bus mode of the opcode phase.
ospi_w_bus_mode_t	addr_bus_mode: 2	Bus mode of the address phase.
uint32_t	hclk_cycles: 4	The number of AMBA AHB hclk cycles (0..15) without memory read requests before executing an erase or erase resume command. Use this setting to delay one of the aforementioned commands otherwise keep it 0.
uint8_t	opcode	Erase command opcode.
uint8_t	cs_idle_delay_cycles: 5	The minimum CS idle delay in clock cycles (< 32) between a Write Enable, Erase, Erase Suspend or Erase Resume command and the next consecutive command.

ospi_w_suspend_resume_instr_cfg_t

struct ospi_w_suspend_resume_instr_cfg_t

OSPIF Erase suspend/resume instruction structure (auto access mode).

Data Fields
ospi_w_bus_mode_t	suspend_bus_mode: 2	Bus mode during the erase suspend command phase.
ospi_w_bus_mode_t	resume_bus_mode: 2	Bus mode during the erase resume command phase.
uint8_t	suspend_opcode	Erase suspend instruction code.
uint8_t	resume_opcode	Erase resume instruction code.
uint8_t	res_sus_latency_clk_cycles: 6	The minimum required latency (clock cycles) between an erase resume and the next consequent erase suspend command.
uint8_t	sussts_dly: 6	Defines a timer that counts the minimum allowed delay between an erase suspend command and the next read status command.

ospi_w_break_instr_cfg_t

struct ospi_w_break_instr_cfg_t

OSPIF Read break sequence structure (auto access mode).

Data Fields
uint16_t	break_opcode	The code value of the read break instruction.
uint8_t	break_sz: 4	The size of Burst Break Sequence 1..16 bytes.
ospi_w_bus_mode_t	break_tx_md: 2	The mode of the OSPI Bus during the transmission of the burst break sequence.
ospi_w_break_sec_hf_t	break_sec_hf: 1	Disable output during the transmission of the second half.
ospi_w_break_t	break_en: 1	Controls the application of a special command (read burst break sequence) that is used in order to force the device to abandon the continuous read mode.

ospi_w_memblen_cfg_t

struct ospi_w_memblen_cfg_t

OSPIF External memory burst length configuration.

Data Fields
ospi_w_memblen_burst_t	memblen: 4	In this register is defined the expected behavior of the external memory device regarding the length of a burst operation.
uint16_t	tcem_cc: 12	Defines the maximum allowed time tCEM for which the OSPIC_CS can stay active (when tcem_en=1).
ospi_w_t_cem_t	tcem_en: 1	This bit enables the controlling of the maximum time tCEM for which the OSPI_CS remains active (auto mode and PSRAM).
bool	rd_lin_en: 1	By setting (1) in this bit the access limits that are set with the OSPIC_MEMBLEN are ignored for the read operation.
bool	keep_active: 1	By setting (1) in this bit the controller will keep the access active in order to serve consecutive accesses, without toggling the chip select of the memory,when this is possible.
bool	wcmd_hybrid: 1	By setting (1) in this bit, the special commands that used during wrap bursts.
uint8_t	dielen: 4	The size of each die from which the memory device is consisted.
uint8_t	active_thr: 4	Defines the maximum number of AHB clock cycles for which the memory should stay without access, before the active access to be aborted.

ospi_w_write_instr_cfg_t

struct ospi_w_write_instr_cfg_t

OSPIF Write instruction structure (manual & auto access mode).

Data Fields
uint8_t	write_opcode	The code value of the write instruction.
uint8_t	write_opcode_wb	The code value of the write instruction in wrapping burst.
ospi_w_bus_mode_t	opcode_bus_mode: 2	Bus mode of the opcode phase.
ospi_w_bus_mode_t	addr_bus_mode: 2	Bus mode of the address phase.
ospi_w_bus_mode_t	data_bus_mode: 2	Bus mode of the data phase.
ospi_w_bus_mode_t	dummy_bus_mode: 2	Bus mode of the dummy data phase.
uint8_t	dummy_bytes: 5	The number of dummy bytes. Valid values are 0..31 i.e. 1..32 dummy bytes.
bool	dummy_en	Enable dummy bytes.
bool	wdex_en	If enabled wait until the write data to be available before to start sending the write command sequence.
uint8_t	cs_hi_min_clk_cycles: 5	After the execution of the write command, the OSPI_CS remains high for at least this number of OSPI_SCK clock cycles.
bool	send_wen_req	If enabled the controller will apply the write enable command.

ospi_w_write_enable_instr_cfg_t

struct ospi_w_write_enable_instr_cfg_t

OSPIF write enable instruction configuration structure (auto access mode).

Data Fields
ospi_w_bus_mode_t	opcode_bus_mode: 2	Bus mode of the opcode phase.
uint8_t	opcode	Write Enable command opcode.

ospi_w_ctrl_ddr_cfg_t

struct ospi_w_ctrl_ddr_cfg_t

OSPIF Double Data Rate (DDR) configuration structure.

Data Fields
uint32_t	ctrl_ddra	DDR Control register A.
uint32_t	ctrl_ddrb	DDR Control register B.

ospi_w_extra_registers_cfg_t

struct ospi_w_extra_registers_cfg_t

OSPIF Extra registers configuration structure.

Data Fields
uint32_t	ctrl_mr_reg	Control MR register.
uint32_t	drst_cmd_reg	DRST command register.

ospi_w_qpi_instr_cfg_t

struct ospi_w_qpi_instr_cfg_t

OSPIF Enter/Exit QPI instruction configuration structure.

Data Fields
uint8_t	opcode_enter	Enter QPI command opcode.
uint8_t	opcode_exit	Exit QPI command opcode.

ospi_w_flash_cfg_t

struct ospi_w_flash_cfg_t

OSPI memory configuration structure.

This struct is used to define a driver for a specific OSPI memory.

Data Fields
ospi_w_clk_mode_t	clk_mode: 1	Clock Mode.
ospi_w_read_instr_cfg_t const *	p_read_instr_cfg	Read instruction configuration struct.
ospi_w_erase_instr_cfg_t const *	p_erase_instr_cfg	Erase instruction configuration struct.
ospi_w_suspend_resume_instr_cfg_t const *	p_suspend_resume_instr_cfg	Program and erase suspend/resume instruction.
ospi_w_write_enable_instr_cfg_t const *	p_write_enable_instr_cfg	Write enable instruction configuration.
ospi_w_read_status_instr_cfg_t const *	p_read_status_instr_cfg	Read status register instruction.
ospi_w_write_instr_cfg_t const *	p_write_instr_cfg	Write instruction configuration struct.
ospi_w_break_instr_cfg_t const *	p_break_instr_cfg	Burst break instruction configuration struct.
ospi_w_memblen_cfg_t const *	p_memblen_cfg	External memory burst length configuration struct.
ospi_w_ctrl_ddr_cfg_t const *	p_ctrl_ddr	OSPI DDR Control registers configuration struct.
ospi_w_extra_registers_cfg_t const *	p_extra_regs	OSPI Extra registers configuration struct.
ospi_w_qpi_instr_cfg_t const *	p_qpi_instr_cfg	Enter/Exit QPI instruction configuration struct.

ospi_w_extended_cfg_t

struct ospi_w_extended_cfg_t

Extended configuration for OSPIF.

Data Fields
uint8_t	channel	Channel number to be used (0..1).
ospi_w_mode_t	ospi_mode	OSPI DDR or SDR mode.
ospi_w_clk_div_t	ospi_clk_div	CLK divider.
ospi_w_drive_current_t	ospi_drive_current	Set the Drive Strength of the OSPI Controller.
ospi_w_slew_rate_t	ospi_slew_rate	Set the Slew Rate of the OSPI Controller.
ospi_w_flash_cfg_t const *	p_ospi_flash_cfg	Pointer to ospi controller configuration struct.

ospi_w_instance_ctrl_t

struct ospi_w_instance_ctrl_t

Instance control block. DO NOT INITIALIZE. Initialization occurs when spi_flash_api_t::open is called.

Data Fields
spi_flash_cfg_t const *	p_cfg	Pointer to initial configuration.
spi_flash_data_lines_t	data_lines	Data lines.
uint32_t	total_size_bytes	Total size of the flash in bytes.
uint32_t	open	Whether or not driver is open.
ospi_w_bus_mode_t	flash_opcode_bus_mode	Opcode Bus mode of flash.
ospi_w_bus_mode_t	manual_access_bus_mode[2]	Bus mode for mannual access.
uint8_t	manual_command_length	Command length for mannual access mode.
bool	xip_mode_is_enabled	XiP mode is enabled or disabled.

Enumeration Type Documentation

ospi_w_access_mode_t

enum ospi_w_access_mode_t

OSPI_W memory access mode.

Enumerator
OSPI_W_ACCESS_MODE_MANUAL	Direct register access using the OSPI_W register file.
OSPI_W_ACCESS_MODE_AUTO	Up to 32 MB memory-mapped access with 3- and 4-byte addressing modes.

ospi_w_bus_mode_t

enum ospi_w_bus_mode_t

OSPI_W Bus mode.

Enumerator
OSPI_W_BUS_MODE_SINGLE	Bus mode in single mode.
OSPI_W_BUS_MODE_DUAL	Bus mode in dual mode.
OSPI_W_BUS_MODE_QUAD	Bus mode in quad mode.
OSPI_W_BUS_MODE_OCTAL	Bus mode in octal mode.

ospi_w_clk_div_t

enum ospi_w_clk_div_t

OSPI_W CLK divider.

Enumerator
OSPI_W_CLK_DIV_1	OSPI CLK = CLK / 1.
OSPI_W_CLK_DIV_2	OSPI CLK = CLK / 2.
OSPI_W_CLK_DIV_4	OSPI CLK = CLK / 4.
OSPI_W_CLK_DIV_8	OSPI CLK = CLK / 8.

ospi_w_ers_t

enum ospi_w_ers_t

The progress of sector/block erasing.

Enumerator
OSPI_W_ERS_NO	No erase.
OSPI_W_ERS_PENDING	Pending erase request.
OSPI_W_ERS_RUNNING	Erase procedure is running.
OSPI_W_ERS_SUSPENDED	Suspended erase procedure.
OSPI_W_ERS_FINISHING	Finishing the erase procedure.

ospi_w_clk_mode_t

enum ospi_w_clk_mode_t

OSPI clock mode.

Enumerator
OSPI_W_CLK_MODE_LOW	OSPI_SCK is low when OSPI_CS is high.
OSPI_W_CLK_MODE_HIGH	OSPI_SCK is high when OSPI_CS is high.

ospi_w_drive_current_t

enum ospi_w_drive_current_t

OSPIF pads drive current strength. The current value depends on the device.

ospi_w_read_pipe_t

enum ospi_w_read_pipe_t

OSPIF read pipe setting.

When read pipe is disabled the sampling clock is determined by OSPI_W_SAMPLING_EDGE otherwise by OSPI_W_READ_PIPE_DELAY.

Enumerator
OSPI_W_READ_PIPE_DISABLE	Disable read pipe delay.
OSPI_W_READ_PIPE_ENABLE	Enable read pipe delay.

ospi_w_read_pipe_delay_t

enum ospi_w_read_pipe_delay_t

OSPIF Read pipe clock delay in relation to the falling edge of OSPI_SCK.

The read pipe delay should be set based on the voltage level of the power rail V12.

Enumerator
OSPI_W_READ_PIPE_DELAY_0	Set read pipe delay to 0.
OSPI_W_READ_PIPE_DELAY_1	Set read pipe delay to 1.
OSPI_W_READ_PIPE_DELAY_2	Set read pipe delay to 2.
OSPI_W_READ_PIPE_DELAY_3	Set read pipe delay to 3.
OSPI_W_READ_PIPE_DELAY_4	Set read pipe delay to 4.
OSPI_W_READ_PIPE_DELAY_5	Set read pipe delay to 5.
OSPI_W_READ_PIPE_DELAY_6	Set read pipe delay to 6.
OSPI_W_READ_PIPE_DELAY_7	Set read pipe delay to 7.

ospi_w_slew_rate_t

enum ospi_w_slew_rate_t

OSPIF pads slew rate.

Enumerator
OSPI_W_SLEW_RATE_0	Rise = 1.7 V/ns, Fall = 1.9 V/ns (weak).
OSPI_W_SLEW_RATE_1	Rise = 2.0 V/ns, Fall = 2.3 V/ns.
OSPI_W_SLEW_RATE_2	Rise = 2.3 V/ns, Fall = 2.6 V/ns.
OSPI_W_SLEW_RATE_3	Rise = 2.4 V/ns, Fall = 2.7 V/ns (strong)

ospi_w_hready_mode_t

enum ospi_w_hready_mode_t

OSPIF HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers.

This configuration is useful when the frequency of the OSPI clock is much lower than the clock of the AMBA bus, in order to avoid locking the AMBA bus for a long time. When is set to OSPI_W_HREADY_MODE_WAIT there is no need to check the OSPIC_BUSY for detecting completion of the requested access.

Enumerator
OSPI_W_HREADY_MODE_WAIT	Adds wait states via hready signal when accessing the OQSPIF_WRITEDATA, OQSPIF_READDATA and OQSPIF_DUMMYDATA registers.
OSPI_W_HREADY_MODE_NO_WAIT	Don't add wait states via the HREADY signal.

ospi_w_instr_md_t

enum ospi_w_instr_md_t

OSPIF instruction mode.

Enumerator
OSPI_W_INSTR_MD_TX_AT_ANY_BURST_ACCESS	Transmit instruction at any burst access.
OSPI_W_INSTR_MD_TX_ONLY_IN_FIRST_ACCESS	Transmit instruction only in the first access after the selection of Auto Mode.

ospi_w_wrap_md_t

enum ospi_w_wrap_md_t

OSPIF wrap mode enable bit.

Enumerator
OSPI_W_WRAP_MD_SEL_INSTR	The OSPIC_INST is the selected instruction at any read access.
OSPI_W_WRAP_MD_SEL_INSTR_WB	The OSPIC_INST_WB is the selected instruction at any read wrapping burst access.

ospi_w_wrap_wr_en_t

enum ospi_w_wrap_wr_en_t

OSPIF write wrapping burst will be implemented by using a special write instruction.

Enumerator
OSPI_W_WRAP_WR_EN_INST	Select OSPIC_WR_INST.
OSPI_W_WRAP_WR_EN_INST_WB	Select OSPIC_WR_INST_WB.

ospi_w_rd_bend_md_t

enum ospi_w_rd_bend_md_t

OSPIF behavior when a read burst is terminated early in the AMBA bus.

Enumerator
OSPI_W_RD_BEND_MD_TERMINATE_ASAP	The corresponding read burst in the memory device will be terminated as soon as possible, based on the pipeline of the controller.
OSPI_W_RD_BEND_MD_TERMINATE_WHEN_DONE	The read burst in the memory device will be terminated only after filling the last position of the current read buffer.

ospi_w_rd_rdb_en_t

enum ospi_w_rd_rdb_en_t

Set the read pipeline in burst mode while retrieving the data of the memory device.

Enumerator
OSPI_W_RD_RDB_EN_MIN_CLK_PULSES	The controller will provide the minimum required number of clock pulses in the interface during the reading of the data.
OSPI_W_RD_RDB_EN_UNTIL_DONE	Set the read pipeline in burst mode while the data are retrieved of the memory device.

ospi_w_extra_byte_t

enum ospi_w_extra_byte_t

OSPIF extra byte setting in auto access mode.

Enumerator
OSPI_W_EXTRA_BYTE_DISABLE	Disable extra byte phase.
OSPI_W_EXTRA_BYTE_ENABLE	Enable extra byte phase.

ospi_w_extra_byte_half_t

enum ospi_w_extra_byte_half_t

OSPIF extra byte half setting in auto access mode.

This setting is out of scope if the extra byte is disabled.

Enumerator
OSPI_W_EXTRA_BYTE_HALF_DISABLE	Transmit the complete extra byte.
OSPI_W_EXTRA_BYTE_HALF_ENABLE	The output switches to Hi-Z during the transmission of the low nibble of the extra byte.

ospi_w_break_t

enum ospi_w_break_t

OSPIF break enable/disable.

Enumerator
OSPI_W_BREAK_DISABLE	Disable break command.
OSPI_W_BREAK_ENABLE	Enable break command.

ospi_w_break_sec_hf_t

enum ospi_w_break_sec_hf_t

OSPIF Disable output during the transmission of the second half (OSPIC_BRK_WRD[3:0]).

Setting this bit is only useful if OSPIC_BRK_EN =1 and OSPIC_BRK_SZ= 1.

Enumerator
OSPI_W_BREAK_SEC_HF_DRIVE	The controller drives the SPI bus during the transmission of the OSPIC_BRK_WRD[3:0].
OSPI_W_BREAK_SEC_HF_HIZ	The controller leaves the SPI bus in Hi-Z during the transmission of the OSPIC_BRK_WORD[3:0].

ospi_w_t_cem_t

enum ospi_w_t_cem_t

OSPIF tCEM enable/disable.

Enumerator
OSPI_W_T_CEM_DISABLE	Disable tCEM control.
OSPI_W_T_CEM_ENABLE	Enable tCEM control.

ospi_w_memblen_burst_t

enum ospi_w_memblen_burst_t

Length of a burst operation for a OSPI RAM device.

Enumerator
OSPI_W_MEMBLEN_BURST_INCR_UNSPECIFIED	The external memory device implements incremental burst of unspecified length.
OSPI_W_MEMBLEN_BURST_WRAP_4B	The external memory device implements a wrapping burst of length 4 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_8B	The external memory device implements a wrapping burst of length 8 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_16B	The external memory device implements a wrapping burst of length 16 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_32B	The external memory device implements a wrapping burst of length 32 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_64B	The external memory device implements a wrapping burst of length 64 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_128B	The external memory device implements a wrapping burst of length 128 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_256B	The external memory device implements a wrapping burst of length 256 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_512B	The external memory device implements a wrapping burst of length 512 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_1024B	The external memory device implements a wrapping burst of length 1024 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_2048B	The external memory device implements a wrapping burst of length 2048 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_4096B	The external memory device implements a wrapping burst of length 4096 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_8192B	The external memory device implements a wrapping burst of length 8192 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_16384B	The external memory device implements a wrapping burst of length 16384 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_32768B	The external memory device implements a wrapping burst of length 32768 bytes.
OSPI_W_MEMBLEN_BURST_WRAP_65536B	The external memory device implements a wrapping burst of length 65536 bytes.

ospi_w_sampling_edge_t

enum ospi_w_sampling_edge_t

OSPI clock edge setting for the sampling of the incoming data when the read pipe is disabled.

Enumerator
OSPI_W_SAMPLING_EDGE_POS	The incoming data sampling is triggered by the positive edge of OSPI clock signal.
OSPI_W_SAMPLING_EDGE_NEG	The incoming data sampling is triggered by the negative edge of OSPI clock signal.

ospi_w_mode_t

enum ospi_w_mode_t

OSPI DDR or SDR mode.

Enumerator
OSPI_W_MODE_DDR	OSPI DDR (double data rate) mode.
OSPI_W_MODE_SDR	OSPI SDR (single data rate) mode.

ospi_w_busy_level_t

enum ospi_w_busy_level_t

OSPI device busy status setting.

Enumerator
OSPI_W_BUSY_LEVEL_LOW	The OSPI device is busy when the pin level bit is low.
OSPI_W_BUSY_LEVEL_HIGH	The OSPI device is busy when the pin level bit is high.

ospi_w_stsdly_sel_t

enum ospi_w_stsdly_sel_t

OSPIF timer which is used to count the delay that it has to wait before to read the Flash status register, after an erase or an erase resume command.

Enumerator
OSPI_W_STSDLY_SEL_RESSTS_DLY	The delay is controlled by the OSPIC_RESSTS_DLY which counts on the OSPI_SCK clock.
OSPI_W_STSDLY_SEL_RESSUS_DLY	The delay is controlled by the OSPIC_RESSUS_DLY which counts on the 222 kHz clock.

ospi_w_dummy_value_t

enum ospi_w_dummy_value_t

OSPIF value that is transferred on the SPI bus during the phase of the dummy bytes.

Enumerator
OSPI_W_RSTAT_DMY_ZERO_KEEP_UNCHANGED	The controller keeps the data in the bus unchanged, until to change the bus direction in input mode.
OSPI_W_RSTAT_DMY_ZERO_FORCE_ZERO	Forces the dummy bytes to get the zero value (only for the cycles that are not in input mode).

ospi_w_idx_bus_mode_t

enum ospi_w_idx_bus_mode_t

Enumerator
OSPI_W_IDX_INSTR_BUS_MODE	Index of instruction bus mode.
OSPI_W_IDX_NONINSTR_BUS_MODE	Index of non-instruction bus mode (address/extra/dummy/data bus modes).

Function Documentation

R_OSPI_W_DirectWrite()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_DirectWrite	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint32_t const	bytes,
		bool const	read_after_write
	)

Writes raw data directly to the OSPI_W. Unsupported by OSPI_W.

Implements spi_flash_api_t::directWrite.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[in]	p_src	Pointer to the data to write.
[in]	bytes	Number of bytes to write.
[in]	read_after_write	Whether or not to close the SPI bus cycle.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI_W.

R_OSPI_W_DirectRead()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_DirectRead	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_dest,
		uint32_t const	bytes
	)

Reads raw data directly from the OSPI_W. This API can only be called after R_OSPI_W_DirectWrite with read_after_write set to true. Unsupported by OSPI_W.

Implements spi_flash_api_t::directRead.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[out]	p_dest	Pointer to the destination buffer.
[in]	bytes	Number of bytes to read.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI_W.

R_OSPI_W_DirectTransfer()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_DirectTransfer	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_direct_transfer_t *const	p_transfer,
		spi_flash_direct_transfer_dir_t	direction
	)

Read/Write raw data directly with the OctaFlash/OctaRAM device.

Note

Use R_OSPI_W_SpiProtocolSet before a direct transfer to set the bus mode in the appropriate manual mode.

Implements spi_flash_api_t::directTransfer.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[in]	p_transfer	Pointer to spi_flash_direct_transfer_t.
[in]	direction	Direct read or write direction.

Return values

FSP_SUCCESS	Directly read raw data successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_OSPI_W_XipEnter()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_XipEnter

(

spi_flash_ctrl_t *

p_ctrl

)

Enters XiP (execute in place) mode.

Note

XiP mode refers to random access read mode, also known as Fast Read Quad I/O (EBh), 4READ: 4 x I/O READ (EBh), etc.

Implements spi_flash_api_t::xipEnter.

Parameters

[in]

p_ctrl

Pointer to the instance control structure.

Return values

FSP_SUCCESS	The flash enters XiP mode successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_W_XipExit()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_XipExit

(

spi_flash_ctrl_t *

p_ctrl

)

Exits XiP (execute in place) mode.

Implements spi_flash_api_t::xipExit.

Parameters

[in]

p_ctrl

Pointer to the instance control structure.

Return values

FSP_SUCCESS	The flash exits XiP mode successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_W_Write()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Write	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t const *const	p_src,
		uint8_t *const	p_dest,
		uint32_t	byte_count
	)

Program a page of data to the flash.

Implements spi_flash_api_t::write.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[in]	p_src	Pointer to the source data.
[out]	p_dest	Pointer to the destination.
[in]	byte_count	Number of bytes to write.

Return values

FSP_SUCCESS	The flash was programmed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl, p_dest or p_src is NULL, or byte_count crosses a page boundary.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_OSPI_W_Erase()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Erase	(	spi_flash_ctrl_t *	p_ctrl,
		uint8_t *const	p_device_address,
		uint32_t	byte_count
	)

Erase a block or sector of flash. The byte_count must exactly match one of the erase sizes defined in spi_flash_cfg_t. For chip erase, byte_count must be SPI_FLASH_ERASE_SIZE_CHIP_ERASE.

Implements spi_flash_api_t::erase.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[in]	p_device_address	Pointer to the device address.
[in]	byte_count	Number of bytes to be erased.

Return values

FSP_SUCCESS	The command to erase the flash was executed successfully.
FSP_ERR_ASSERTION	p_instance_ctrl or p_device_address is NULL, or byte_count doesn't match an erase size defined in spi_flash_cfg_t, or device is in XiP mode.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_DEVICE_BUSY	The device is busy.

R_OSPI_W_StatusGet()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_StatusGet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_status_t *const	p_status
	)

Gets the write or erase status of the flash.

Implements spi_flash_api_t::statusGet.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[out]	p_status	Pointer to the status spi_flash_status_t.

Return values

FSP_SUCCESS	The write status is in p_status.
FSP_ERR_ASSERTION	p_instance_ctrl or p_status is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.

R_OSPI_W_BankSet()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_BankSet	(	spi_flash_ctrl_t *	p_ctrl,
		uint32_t	bank
	)

Selects the bank to access.

Implements spi_flash_api_t::bankSet.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[in]	bank	The bank which need to access.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI_W.

R_OSPI_W_SpiProtocolSet()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_SpiProtocolSet	(	spi_flash_ctrl_t *	p_ctrl,
		spi_flash_protocol_t	spi_protocol
	)

Sets the SPI protocol in R_OSPI_W_DirectTransfer API.

Note

Updates OSPI_W access bus mode for R_OSPI_W_DirectTransfer API.

Implements spi_flash_api_t::spiProtocolSet.

Parameters

[in]	p_ctrl	Pointer to the instance control structure.
[in]	spi_protocol	The type of SPI Flash protocol.

Return values

FSP_SUCCESS	SPI protocol updated successfully.
FSP_ERR_ASSERTION	A required pointer is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.
FSP_ERR_UNSUPPORTED	Protocol is not supported by OSPI_W.

R_OSPI_W_AutoCalibrate()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_AutoCalibrate

(

spi_flash_ctrl_t *

p_ctrl

)

Auto-calibrate the OctaRAM device using the preamble pattern. Implements spi_flash_api_t::autoCalibrate.

Parameters

[in]

p_ctrl

Pointer to the instance control structure.

Return values

FSP_ERR_UNSUPPORTED

API not supported by OSPI_W.

R_OSPI_W_Close()

BSP_PLACE_CODE_IN_RAM fsp_err_t R_OSPI_W_Close

(

spi_flash_ctrl_t *

p_ctrl

)

Close the OSPI_W driver module.

Implements spi_flash_api_t::close.

Parameters

[in]

p_ctrl

Pointer to the instance control structure.

Return values

FSP_SUCCESS	Close module successfully.
FSP_ERR_ASSERTION	p_instance_ctrl is NULL.
FSP_ERR_NOT_OPEN	Driver is not opened.