hw_timer.h

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#ifndef HW_TIMER_H_
#define HW_TIMER_H_
 
 
#if dg_configUSE_HW_TIMER
 
#include <stdbool.h>
#include <stdint.h>
#include "sdk_defs.h"
#include "hw_gpio.h"
 
 
/* Timer Base Address */
#define TBA(id)                         ((TIMER_Type *)id)
 
#define HW_TIMER_REG_GETF(id, reg, field) \
        ((TBA(id)->reg & (TIMER_##reg##_##field##_Msk)) >> (TIMER_##reg##_##field##_Pos))
 
#define HW_TIMER_REG_SETF(id, reg, field, val) \
        TBA(id)->reg = ((TBA(id)->reg & ~(TIMER_##reg##_##field##_Msk)) | \
        ((TIMER_##reg##_##field##_Msk) & ((val) << (TIMER_##reg##_##field##_Pos))))
 
#define TIMER_MAX_PRESCALER_VAL   (TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Msk >> \
                                   TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Pos)
 
#define TIMER_MAX_RELOAD_VAL   TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Msk
 
#define TIMER_MAX_SHOTWIDTH_VAL   TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk
 
 
#define TIMER_MAX_PWM_FREQ_VAL   TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk
 
#define TIMER_MAX_PWM_DC_VAL   TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk
 
#define HW_TIMER          ((void *)TIMER_BASE)
#define HW_TIMER2         ((void *)TIMER2_BASE)
#define HW_TIMER3         ((void *)TIMER3_BASE)
#define HW_TIMER4         ((void *)TIMER4_BASE)
typedef void * HW_TIMER_ID;
 
 
typedef enum {
        HW_TIMER_MODE_TIMER = 0,          
        HW_TIMER_MODE_ONESHOT = 1,        
} HW_TIMER_MODE;
 
typedef enum {
        HW_TIMER_CLK_SRC_INT = 0,      
        HW_TIMER_CLK_SRC_EXT = 1       
} HW_TIMER_CLK_SRC;
 
typedef enum {
        HW_TIMER_DIR_UP = 0,           
        HW_TIMER_DIR_DOWN = 1          
} HW_TIMER_DIR;
 
typedef enum {
        HW_TIMER_TRIGGER_RISING = 0,   
        HW_TIMER_TRIGGER_FALLING = 1   
} HW_TIMER_TRIGGER;
 
 
typedef enum {
        HW_TIMER_ONESHOT_WAIT = 0,     
        HW_TIMER_ONESHOT_DELAY = 1,    
        HW_TIMER_ONESHOT_STARTED = 2,  
        HW_TIMER_ONESHOT_ACTIVE = 3    
} HW_TIMER_ONESHOT;
 
typedef enum {
        HW_TIMER_GPIO_GPIO_NONE = 0,      
        HW_TIMER_GPIO_PIN_P0_0  = 1,      
        HW_TIMER_GPIO_PIN_P0_1  = 2,      
        HW_TIMER_GPIO_PIN_P0_2  = 3,      
        HW_TIMER_GPIO_PIN_P0_3  = 4,      
        HW_TIMER_GPIO_PIN_P0_4  = 5,      
        HW_TIMER_GPIO_PIN_P0_5  = 6,      
        HW_TIMER_GPIO_PIN_P0_6  = 7,      
        HW_TIMER_GPIO_PIN_P0_7  = 8,      
        HW_TIMER_GPIO_PIN_P0_8  = 9,      
        HW_TIMER_GPIO_PIN_P0_9  = 10,     
        HW_TIMER_GPIO_PIN_P0_10 = 11,     
        HW_TIMER_GPIO_PIN_P0_11 = 12,     
        HW_TIMER_GPIO_PIN_P0_12 = 13,     
        HW_TIMER_GPIO_PIN_P0_13 = 14,     
        HW_TIMER_GPIO_PIN_P0_14 = 15,     
        HW_TIMER_GPIO_PIN_P0_15 = 16,     
        HW_TIMER_GPIO_PIN_P1_0  = 17,     
        HW_TIMER_GPIO_PIN_P1_1  = 18,     
        HW_TIMER_GPIO_PIN_P1_2  = 19,     
        HW_TIMER_GPIO_PIN_P1_3  = 20,     
        HW_TIMER_GPIO_PIN_P1_4  = 21,     
        HW_TIMER_GPIO_PIN_P1_5  = 22,     
        HW_TIMER_GPIO_PIN_P1_6  = 23,     
        HW_TIMER_GPIO_PIN_P1_7  = 24,     
        HW_TIMER_GPIO_PIN_P1_8  = 25,     
        HW_TIMER_GPIO_PIN_P1_9  = 26,     
        HW_TIMER_GPIO_PIN_P1_10 = 27,     
        HW_TIMER_GPIO_PIN_P1_11 = 28,     
        HW_TIMER_GPIO_PIN_P1_12 = 29,     
        HW_TIMER_GPIO_PIN_P1_13 = 30,     
        HW_TIMER_GPIO_PIN_P1_14 = 31,     
        HW_TIMER_GPIO_PIN_P1_15 = 32,     
} HW_TIMER_GPIO;
 
typedef void (*hw_timer_handler_cb)(void);
 
typedef void (*hw_timer_capture_handler_cb)(uint8_t gpio_event);
 
typedef struct {
        HW_TIMER_DIR        direction;    
        uint32_t            reload_val;   
        bool                free_run;     
        HW_TIMER_GPIO       gpio1;        
        HW_TIMER_TRIGGER    trigger1;     
        HW_TIMER_GPIO       gpio2;        
        HW_TIMER_TRIGGER    trigger2;     
        HW_TIMER_GPIO       gpio3;        
        HW_TIMER_TRIGGER    trigger3;     
        HW_TIMER_GPIO       gpio4;        
        HW_TIMER_TRIGGER    trigger4;     
} timer_config_timer_capture;
 
typedef struct {
        uint32_t            delay;              
        uint32_t            shot_width;         
        HW_TIMER_GPIO       gpio;               
        HW_TIMER_TRIGGER    trigger;            
} timer_config_oneshot;
 
typedef struct {
        HW_GPIO_PIN     pin;          
        HW_GPIO_PORT    port;         
        bool            pwm_active_in_sleep;
        uint16_t        frequency;
        uint16_t        duty_cycle;
} timer_config_pwm;
 
typedef struct {
        HW_TIMER_CLK_SRC    clk_src;                    
        uint8_t             prescaler;                  
        HW_TIMER_MODE       mode;                       
        union {
                timer_config_timer_capture    timer;    
                timer_config_oneshot          oneshot;  
        };
        timer_config_pwm   pwm;                         
} timer_config;
 
void hw_timer_init(HW_TIMER_ID id, const timer_config *cfg);
 
void hw_timer_configure(HW_TIMER_ID id, const timer_config *cfg);
 
void hw_timer_configure_timer(HW_TIMER_ID id, const timer_config_timer_capture *cfg);
 
void hw_timer_configure_oneshot(HW_TIMER_ID id, const timer_config_oneshot *cfg);
 
 
__STATIC_INLINE void hw_timer_freeze(const HW_TIMER_ID id)
{
        if (id == HW_TIMER) {
                GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk;
        } else if (id == HW_TIMER2) {
                GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk;
        } else if (id == HW_TIMER3) {
                GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk;
        } else if (id == HW_TIMER4) {
                GPREG->SET_FREEZE_REG = GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk;
        } else {
                ASSERT_WARNING(0);//Invalid argument
        }
}
 
__STATIC_INLINE void hw_timer_unfreeze(const HW_TIMER_ID id)
{
        if (id == HW_TIMER) {
                GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk;
        } else if (id == HW_TIMER2) {
                GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk;
        } else if (id == HW_TIMER3) {
                GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk;
        } else if (id == HW_TIMER4) {
                GPREG->RESET_FREEZE_REG = GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk;
        } else {
                ASSERT_WARNING(0);//Invalid argument
        }
}
 
__STATIC_INLINE bool hw_timer_frozen(const HW_TIMER_ID id)
{
        if (id == HW_TIMER) {
                return (GPREG->SET_FREEZE_REG & GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk);
        } else if (id == HW_TIMER2) {
                return (GPREG->SET_FREEZE_REG & GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk);
        } else if (id == HW_TIMER3) {
                return (GPREG->SET_FREEZE_REG & GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk);
        } else if (id == HW_TIMER4) {
                return (GPREG->SET_FREEZE_REG & GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk);
        } else {
                ASSERT_WARNING(0);//Invalid argument
        }
}
 
__STATIC_INLINE void hw_timer_set_clk(HW_TIMER_ID id, HW_TIMER_CLK_SRC clk)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_SYS_CLK_EN, clk);
}
 
__STATIC_INLINE void hw_timer_set_prescaler(HW_TIMER_ID id, uint8_t value)
{
        ASSERT_WARNING(TIMER_MAX_PRESCALER_VAL >= value);
        HW_TIMER_REG_SETF(id, TIMER_SETTINGS_REG, TIM_PRESCALER, value);
        while (HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_TIMER_BUSY));
}
 
__STATIC_FORCEINLINE void hw_timer_set_reload(HW_TIMER_ID id, uint32_t value)
{
        ASSERT_WARNING(TIMER_MAX_RELOAD_VAL >= value);
        HW_TIMER_REG_SETF(id, TIMER_SETTINGS_REG, TIM_RELOAD, value);
        while (HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_TIMER_BUSY));
}
 
__STATIC_INLINE void hw_timer_set_oneshot_delay(HW_TIMER_ID id, uint32_t delay)
{
        ASSERT_WARNING(TIMER_MAX_RELOAD_VAL >= delay);
        HW_TIMER_REG_SETF(id, TIMER_SETTINGS_REG, TIM_RELOAD, delay);
        while (HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_TIMER_BUSY));
}
 
__STATIC_INLINE void hw_timer_set_shot_width(HW_TIMER_ID id, uint32_t duration)
{
        ASSERT_WARNING(TIMER_MAX_SHOTWIDTH_VAL >= duration);
        TBA(id)->TIMER_SHOTWIDTH_REG = duration;
        while (HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_TIMER_BUSY));
}
 
__STATIC_INLINE void hw_timer_set_freerun(HW_TIMER_ID id, bool enable)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_FREE_RUN_MODE_EN, enable);
}
 
__STATIC_INLINE void hw_timer_set_event1_trigger(HW_TIMER_ID id, HW_TIMER_TRIGGER edge)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_IN1_EVENT_FALL_EN, edge);
}
 
__STATIC_INLINE void hw_timer_set_event2_trigger(HW_TIMER_ID id, HW_TIMER_TRIGGER edge)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_IN2_EVENT_FALL_EN, edge);
}
 
__STATIC_INLINE void hw_timer_set_event3_trigger(HW_TIMER_TRIGGER edge)
{
        REG_SETF(TIMER, TIMER_CTRL_REG, TIM_IN3_EVENT_FALL_EN, edge);
}
 
__STATIC_INLINE void hw_timer_set_event4_trigger(HW_TIMER_TRIGGER edge)
{
        REG_SETF(TIMER, TIMER_CTRL_REG, TIM_IN4_EVENT_FALL_EN, edge);
}
 
__STATIC_INLINE void hw_timer_set_gpio_event_int(uint8_t mask)
{
        uint32_t tmp = TIMER->TIMER_CTRL_REG;
        REG_SET_FIELD(TIMER, TIMER_CTRL_REG, TIM_CAP_GPIO1_IRQ_EN, tmp, (mask & 0x1));
        REG_SET_FIELD(TIMER, TIMER_CTRL_REG, TIM_CAP_GPIO2_IRQ_EN, tmp, ((mask & 0x2) >> 1));
        REG_SET_FIELD(TIMER, TIMER_CTRL_REG, TIM_CAP_GPIO3_IRQ_EN, tmp, ((mask & 0x4) >> 2));
        REG_SET_FIELD(TIMER, TIMER_CTRL_REG, TIM_CAP_GPIO4_IRQ_EN, tmp, ((mask & 0x8) >> 3));
        TIMER->TIMER_CTRL_REG = tmp;
}
 
__STATIC_INLINE void hw_timer_set_event1_gpio(HW_TIMER_ID id, HW_TIMER_GPIO gpio)
{
        TBA(id)->TIMER_GPIO1_CONF_REG = gpio;
}
 
__STATIC_INLINE void hw_timer_set_event2_gpio(HW_TIMER_ID id, HW_TIMER_GPIO gpio)
{
        TBA(id)->TIMER_GPIO2_CONF_REG = gpio;
}
 
__STATIC_INLINE void hw_timer_set_event3_gpio(HW_TIMER_GPIO gpio)
{
        TIMER->TIMER_GPIO3_CONF_REG = gpio;
}
 
__STATIC_INLINE void hw_timer_set_event4_gpio(HW_TIMER_GPIO gpio)
{
        TIMER->TIMER_GPIO4_CONF_REG = gpio;
}
 
__STATIC_INLINE HW_TIMER_CLK_SRC hw_timer_get_clk(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_CTRL_REG, TIM_SYS_CLK_EN);
}
 
__STATIC_INLINE uint32_t hw_timer_get_prescaler(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_SETTINGS_REG, TIM_PRESCALER);
}
 
__STATIC_INLINE uint32_t hw_timer_get_reload(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_SETTINGS_REG, TIM_RELOAD);
}
 
__STATIC_INLINE uint32_t hw_timer_get_oneshot_delay(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_SETTINGS_REG, TIM_RELOAD);
}
 
__STATIC_INLINE uint32_t hw_timer_get_shot_width(HW_TIMER_ID id)
{
        return TBA(id)->TIMER_SHOTWIDTH_REG;
}
 
__STATIC_INLINE bool hw_timer_get_freerun(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_CTRL_REG, TIM_FREE_RUN_MODE_EN);
}
 
__STATIC_INLINE HW_TIMER_TRIGGER hw_timer_get_event1_trigger(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_CTRL_REG, TIM_IN1_EVENT_FALL_EN);
}
 
__STATIC_INLINE HW_TIMER_TRIGGER hw_timer_get_event2_trigger(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_CTRL_REG, TIM_IN2_EVENT_FALL_EN);
}
 
__STATIC_INLINE HW_TIMER_TRIGGER hw_timer_get_event3_trigger(void)
{
        return REG_GETF(TIMER, TIMER_CTRL_REG, TIM_IN3_EVENT_FALL_EN);
}
 
__STATIC_INLINE HW_TIMER_TRIGGER hw_timer_get_event4_trigger(void)
{
        return REG_GETF(TIMER, TIMER_CTRL_REG, TIM_IN4_EVENT_FALL_EN);
}
 
__STATIC_INLINE HW_TIMER_GPIO hw_timer_get_event1_gpio(HW_TIMER_ID id)
{
        return TBA(id)->TIMER_GPIO1_CONF_REG;
}
 
__STATIC_INLINE HW_TIMER_GPIO hw_timer_get_event2_gpio(HW_TIMER_ID id)
{
        return TBA(id)->TIMER_GPIO2_CONF_REG;
}
 
__STATIC_INLINE HW_TIMER_GPIO hw_timer_get_event3_gpio(void)
{
        return TIMER->TIMER_GPIO3_CONF_REG;
}
 
__STATIC_INLINE HW_TIMER_GPIO hw_timer_get_event4_gpio(void)
{
        return TIMER->TIMER_GPIO4_CONF_REG;
}
 
__STATIC_INLINE uint32_t hw_timer_get_capture1(HW_TIMER_ID id)
{
        return TBA(id)->TIMER_CAPTURE_GPIO1_REG;
}
 
__STATIC_INLINE uint32_t hw_timer_get_capture2(HW_TIMER_ID id)
{
        return TBA(id)->TIMER_CAPTURE_GPIO2_REG;
}
 
__STATIC_INLINE uint32_t hw_timer_get_capture3(void)
{
        return TIMER->TIMER_CAPTURE_GPIO3_REG;
}
 
__STATIC_INLINE uint32_t hw_timer_get_capture4(void)
{
        return TIMER->TIMER_CAPTURE_GPIO4_REG;
}
 
__STATIC_INLINE void hw_timer_set_direction(HW_TIMER_ID id, HW_TIMER_DIR dir)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_COUNT_DOWN_EN, dir);
}
 
__STATIC_INLINE void hw_timer_set_mode(HW_TIMER_ID id, HW_TIMER_MODE mode)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_ONESHOT_MODE_EN, mode);
}
 
__STATIC_INLINE HW_TIMER_MODE hw_timer_get_mode(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_CTRL_REG, TIM_ONESHOT_MODE_EN);
}
 
__STATIC_FORCEINLINE uint32_t hw_timer_get_count(HW_TIMER_ID id)
{
 
        return TBA(id)->TIMER_TIMER_VAL_REG;
}
 
__STATIC_INLINE HW_TIMER_ONESHOT hw_timer_get_oneshot_phase(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_ONESHOT_PHASE);
}
 
__STATIC_INLINE bool hw_timer_get_gpio1_state(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_IN1_STATE);
}
 
__STATIC_INLINE uint8_t hw_timer_get_gpio_event_pending(void)
{
        return ((TIMER->TIMER_STATUS_REG &
                (TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk |
                 TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk |
                 TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk |
                 TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk)) >> 4);
}
 
__STATIC_INLINE bool hw_timer_get_gpio2_state(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_IN2_STATE);
}
 
 
__STATIC_INLINE uint16_t hw_timer_get_prescaler_val(HW_TIMER_ID id)
{
        return TBA(id)->TIMER_PRESCALER_VAL_REG;
}
 
__RETAINED_CODE void hw_timer_register_int(const HW_TIMER_ID id, hw_timer_handler_cb handler);
 
__RETAINED_HOT_CODE void hw_timer_unregister_int(const HW_TIMER_ID id);
 
void hw_timer_register_capture_int(hw_timer_capture_handler_cb handler, uint8_t gpio_mask);
 
void hw_timer_unregister_capture_int(void);
 
__STATIC_INLINE void hw_timer_enable(HW_TIMER_ID id)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_EN, 1);
}
 
__STATIC_INLINE void hw_timer_disable(HW_TIMER_ID id)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_EN, 0);
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_CLK_EN, 0);
 
}
 
__STATIC_INLINE void hw_timer_enable_clk(HW_TIMER_ID id)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_CLK_EN, 1);
}
 
__STATIC_INLINE void hw_timer_disable_clk(HW_TIMER_ID id)
{
        HW_TIMER_REG_SETF(id, TIMER_CTRL_REG, TIM_CLK_EN, 0);
}
 
void hw_timer_configure_pwm(HW_TIMER_ID id, const timer_config_pwm *cfg);
 
__STATIC_INLINE void hw_timer_set_pwm_freq(HW_TIMER_ID id, uint32_t value)
{
        ASSERT_WARNING(TIMER_MAX_PWM_FREQ_VAL >= value);
 
        HW_TIMER_REG_SETF(id, TIMER_PWM_CTRL_REG, TIM_PWM_FREQ, value);
        while (HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_PWM_BUSY));
}
 
__STATIC_INLINE void hw_timer_set_pwm_duty_cycle(HW_TIMER_ID id, uint32_t value)
{
        ASSERT_WARNING(TIMER_MAX_PWM_DC_VAL >= value);
        HW_TIMER_REG_SETF(id, TIMER_PWM_CTRL_REG, TIM_PWM_DC, value);
        while (HW_TIMER_REG_GETF(id, TIMER_STATUS_REG, TIM_PWM_BUSY));
}
 
__STATIC_INLINE uint32_t hw_timer_get_pwm_freq(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_PWM_CTRL_REG, TIM_PWM_FREQ);
}
 
__STATIC_INLINE uint32_t hw_timer_get_pwm_duty_cycle(HW_TIMER_ID id)
{
        return HW_TIMER_REG_GETF(id, TIMER_PWM_CTRL_REG, TIM_PWM_DC);
}
 
__STATIC_INLINE void hw_timer_clear_gpio_event(uint8_t mask)
{
        TIMER->TIMER_CLEAR_GPIO_EVENT_REG = mask;
}
 
__STATIC_INLINE void hw_timer_clear_interrupt(const HW_TIMER_ID id)
{
        if (id == HW_TIMER) {
                TIMER->TIMER_CLEAR_IRQ_REG = 0;
        } else if (id == HW_TIMER2) {
                TIMER2->TIMER2_CLEAR_IRQ_REG = 0;
        } else if (id == HW_TIMER3) {
                TIMER3->TIMER3_CLEAR_IRQ_REG = 0;
        } else if (id == HW_TIMER4) {
                TIMER4->TIMER4_CLEAR_IRQ_REG = 0;
        } else {
                ASSERT_WARNING(0);//Invalid argument
        }
}
 
 
#endif /* dg_configUSE_HW_TIMER */
 
 
#endif /* HW_TIMER_H_ */