hw_spi.h

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#ifndef HW_SPI_H_
#define HW_SPI_H_
 
 
#if dg_configUSE_HW_SPI
 
#include <stdint.h>
#include "sdk_defs.h"
#include "hw_gpio.h"
 
/* SPI Base Address */
#define SBA(id)                         ((SPI_Type *)id)
 
typedef void (*hw_spi_tx_callback)(void *user_data, uint16_t transferred);
 
#define HW_SPI1         ((void *)SPI_BASE)
#ifdef SPI2
#define HW_SPI2         ((void *)SPI2_BASE)
#endif
#ifdef SPI3
#define HW_SPI3         ((void *)SPI3_BASE)
#endif
typedef void * HW_SPI_ID;
 
/*
 * OPTIMIZATION DEFINITIONS
 **
 */
 
#define HW_SPI_DMA_SUPPORT              dg_configSPI_DMA_SUPPORT
 
#ifndef HW_SPI1_USE_FIXED_WORD_SIZE
#define HW_SPI1_USE_FIXED_WORD_SIZE     (0)
#endif
 
#ifdef HW_SPI2
 
#ifndef HW_SPI2_USE_FIXED_WORD_SIZE
#define HW_SPI2_USE_FIXED_WORD_SIZE     (0)
#endif
#endif
 
#ifdef HW_SPI3
 
#ifndef HW_SPI3_USE_FIXED_WORD_SIZE
#define HW_SPI3_USE_FIXED_WORD_SIZE     (0)
#endif
#endif
 
#if HW_SPI1_USE_FIXED_WORD_SIZE == 1
 
#ifndef HW_SPI1_FIXED_WORD_SIZE
#error "HW_SPI1_FIXED_WORD_SIZE must be defined when HW_SPI1_USE_FIXED_WORD_SIZE is set!"
#endif
#endif
 
#ifdef HW_SPI2
#if HW_SPI2_USE_FIXED_WORD_SIZE == 1
 
#ifndef HW_SPI2_FIXED_WORD_SIZE
#error "HW_SPI2_FIXED_WORD_SIZE must be defined when HW_SPI2_USE_FIXED_WORD_SIZE is set!"
#endif
#endif
#endif
 
#ifdef HW_SPI3
#if HW_SPI3_USE_FIXED_WORD_SIZE == 1
 
#ifndef HW_SPI3_FIXED_WORD_SIZE
#error "HW_SPI3_FIXED_WORD_SIZE must be defined when HW_SPI3_USE_FIXED_WORD_SIZE is set!"
#endif
#endif
#endif
 
/*
 * ENUMERATION DEFINITIONS
 **
 */
 
typedef enum {
        HW_SPI_WORD_4BIT = 3,    
        HW_SPI_WORD_5BIT,        
        HW_SPI_WORD_6BIT,        
        HW_SPI_WORD_7BIT,        
        HW_SPI_WORD_8BIT,        
        HW_SPI_WORD_9BIT,        
        HW_SPI_WORD_10BIT,       
        HW_SPI_WORD_11BIT,       
        HW_SPI_WORD_12BIT,       
        HW_SPI_WORD_13BIT,       
        HW_SPI_WORD_14BIT,       
        HW_SPI_WORD_15BIT,       
        HW_SPI_WORD_16BIT,       
        HW_SPI_WORD_17BIT,       
        HW_SPI_WORD_18BIT,       
        HW_SPI_WORD_19BIT,       
        HW_SPI_WORD_20BIT,       
        HW_SPI_WORD_21BIT,       
        HW_SPI_WORD_22BIT,       
        HW_SPI_WORD_23BIT,       
        HW_SPI_WORD_24BIT,       
        HW_SPI_WORD_25BIT,       
        HW_SPI_WORD_26BIT,       
        HW_SPI_WORD_27BIT,       
        HW_SPI_WORD_28BIT,       
        HW_SPI_WORD_29BIT,       
        HW_SPI_WORD_30BIT,       
        HW_SPI_WORD_31BIT,       
        HW_SPI_WORD_32BIT,       
} HW_SPI_WORD;
 
typedef enum {
        HW_SPI_MODE_MASTER,
        HW_SPI_MODE_SLAVE,
} HW_SPI_MODE;
 
typedef enum {
        HW_SPI_CP_MODE_0,         
        HW_SPI_CP_MODE_1,         
        HW_SPI_CP_MODE_2,         
        HW_SPI_CP_MODE_3,         
} HW_SPI_MODE_CPOL_CPHA;
 
typedef enum {
        HW_SPI_MINT_DISABLE,
        HW_SPI_MINT_ENABLE,
} HW_SPI_MINT;
 
typedef uint8_t HW_SPI_FREQ;
 
typedef enum {
        HW_SPI_MASTER_EDGE_CAPTURE_CURRENT,    
        HW_SPI_MASTER_EDGE_CAPTURE_NEXT,       
} HW_SPI_MASTER_EDGE_CAPTURE;
 
typedef enum {
        HW_SPI_CS_NONE         = 0,         
        HW_SPI_CS_0            = 1,         
        HW_SPI_CS_1            = 2,         
        HW_SPI_CS_GPIO         = 4,         
} HW_SPI_CS_MODE;
 
typedef enum {
        HW_SPI_FIFO_LEVEL0,     
        HW_SPI_FIFO_LEVEL1,     
        HW_SPI_FIFO_LEVEL2,     
        HW_SPI_FIFO_LEVEL3,     
        HW_SPI_FIFO_LEVEL4,     
} HW_SPI_FIFO_TL;
 
typedef enum {
        HW_SPI_FIFO_NONE        = 0,                                      
        HW_SPI_FIFO_RX_ONLY     = REG_MSK(SPI, SPI_CTRL_REG, SPI_RX_EN),  
        HW_SPI_FIFO_TX_ONLY     = REG_MSK(SPI, SPI_CTRL_REG, SPI_TX_EN),  
        HW_SPI_FIFO_RX_TX       = REG_MSK(SPI, SPI_CTRL_REG, SPI_RX_EN) |
                                  REG_MSK(SPI, SPI_CTRL_REG, SPI_TX_EN)   
} HW_SPI_FIFO;
 
typedef struct
{
        HW_GPIO_PORT port;
        HW_GPIO_PIN pin;
} SPI_Pad;
 
#if (HW_SPI_DMA_SUPPORT == 1)
#include "hw_dma.h"
 
typedef hw_dma_periph_prio_t hw_spi_dma_prio_t;
#endif /* HW_SPI_DMA_SUPPORT */
 
typedef struct
{
        SPI_Pad                 cs_pad;         
        HW_SPI_WORD             word_mode;      
        HW_SPI_MODE             smn_role;       
        HW_SPI_MODE_CPOL_CPHA   cpol_cpha_mode; 
        HW_SPI_FREQ             xtal_freq;      
        HW_SPI_FIFO             fifo_mode;      
        uint8_t                 disabled;       
        HW_SPI_CS_MODE          spi_cs;         
        HW_SPI_FIFO_TL          rx_tl;          
        HW_SPI_FIFO_TL          tx_tl;          
        bool                    swap_bytes;     
        bool                    select_divn;    
#if (HW_SPI_DMA_SUPPORT == 1)
        uint8_t                 use_dma;                
        HW_DMA_CHANNEL          rx_dma_channel;         
        HW_DMA_CHANNEL          tx_dma_channel;         
        hw_spi_dma_prio_t       dma_prio;               
#endif /* HW_SPI_DMA_SUPPORT */
} hw_spi_config_t;
 
//===================== Read/Write functions ===================================
 
#define HW_SPI_REG_SETF(id, reg, field, val) \
        SBA(id)->reg = ((SBA(id)->reg & ~(SPI_##reg##_##field##_Msk)) | \
        ((SPI_##reg##_##field##_Msk) & ((val) << (SPI_##reg##_##field##_Pos))))
 
#define HW_SPI_REG_GETF(id, reg, field) \
        ((SBA(id)->reg & (SPI_##reg##_##field##_Msk)) >> (SPI_##reg##_##field##_Pos))
 
#define HW_SPI_REG_SET_FIELD(reg, field, var, val) \
        REG_SET_FIELD(SPI, reg##_REG, field, var, val)
 
#define HW_SPI_ASSERT(id)                                                                       \
        do {                                                                                    \
                ASSERT_WARNING(REG_GETF(CRG_COM, CLK_COM_REG, SPI_ENABLE) == true);         \
        } while (0);
 
__STATIC_INLINE uint16_t hw_spi_fifo_read16(HW_SPI_ID id)
{
        // Read data from the SPI RX register or RX FIFO
        return (uint16_t) SBA(id)->SPI_FIFO_READ_REG;
}
 
__STATIC_INLINE void hw_spi_fifo_write16(HW_SPI_ID id, uint16_t data)
{
        SBA(id)->SPI_FIFO_WRITE_REG = data;
}
 
__STATIC_INLINE uint8_t hw_spi_fifo_read8(HW_SPI_ID id)
{
        // Read byte from the SPI RX register or RX FIFO
        return (uint8_t) SBA(id)->SPI_FIFO_READ_REG;
}
 
__STATIC_INLINE void hw_spi_fifo_write8(HW_SPI_ID id, uint8_t data)
{
        // Write byte to the SPI TX register or TX FIFO
        SBA(id)->SPI_FIFO_WRITE_REG = data;
}
 
__STATIC_INLINE uint32_t hw_spi_fifo_read32(HW_SPI_ID id)
{
        return SBA(id)->SPI_FIFO_READ_REG;
}
 
__STATIC_INLINE void hw_spi_fifo_write32(HW_SPI_ID id, uint32_t data)
{
        SBA(id)->SPI_FIFO_WRITE_REG = data;
}
 
uint16_t hw_spi_writeread(HW_SPI_ID id, uint16_t val);
 
uint32_t hw_spi_writeread32(HW_SPI_ID id, uint32_t val);
 
void hw_spi_writeread_buf(HW_SPI_ID id, const uint8_t *out_buf, uint8_t *in_buf, uint16_t len,
                                                            hw_spi_tx_callback cb, void *user_data);
 
void hw_spi_write_buf(HW_SPI_ID id, const uint8_t *out_buf, uint16_t len,
                                                            hw_spi_tx_callback cb, void *user_data);
 
void hw_spi_read_buf(HW_SPI_ID id, uint8_t *in_buf, uint16_t len,
                                                            hw_spi_tx_callback cb, void *user_data);
 
__STATIC_INLINE HW_SPI_FIFO_TL hw_spi_get_fifo_depth_in_bytes(const HW_SPI_ID id)
{
        return HW_SPI_FIFO_LEVEL4;
}
 
/*
 * Low Level Register Access Functions
 **
 */
 
/***************** SPI_CTRL_REG Functions *****************/
 
__STATIC_INLINE void hw_spi_set_ctrl_reg(HW_SPI_ID id, uint32_t val)
{
        SBA(id)->SPI_CTRL_REG = val;
}
 
__STATIC_INLINE uint32_t hw_spi_get_ctrl_reg(HW_SPI_ID id)
{
        return SBA(id)->SPI_CTRL_REG;
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_clear_enable(HW_SPI_ID id)
{
        uint32_t ctrl = hw_spi_get_ctrl_reg(id);
 
        HW_SPI_REG_SET_FIELD(SPI_CTRL, SPI_EN, ctrl, 0);
        HW_SPI_REG_SET_FIELD(SPI_CTRL, SPI_TX_EN, ctrl, 0);
        HW_SPI_REG_SET_FIELD(SPI_CTRL, SPI_RX_EN, ctrl, 0);
        HW_SPI_REG_SET_FIELD(SPI_CTRL, SPI_DMA_TX_EN, ctrl, 0);
        HW_SPI_REG_SET_FIELD(SPI_CTRL, SPI_DMA_RX_EN, ctrl, 0);
 
        hw_spi_set_ctrl_reg(id, ctrl);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_spi_en(HW_SPI_ID id, bool spi_enable)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_EN, spi_enable);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_spi_en(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_EN);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_tx_en(HW_SPI_ID id, bool spi_tx_enable)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_TX_EN, spi_tx_enable);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_tx_en(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_TX_EN);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_rx_en(HW_SPI_ID id, bool spi_rx_enable)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_RX_EN, spi_rx_enable);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_rx_en(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_RX_EN);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_dma_tx_en(HW_SPI_ID id, bool spi_dma_tx_enable)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_DMA_TX_EN, spi_dma_tx_enable);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_dma_tx_en(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_DMA_TX_EN);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_dma_rx_en(HW_SPI_ID id, bool spi_dma_rx_enable)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_DMA_RX_EN, spi_dma_rx_enable);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_dma_rx_en(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_DMA_RX_EN);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_fifo_reset(HW_SPI_ID id, bool spi_fifo_reset)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_FIFO_RESET, spi_fifo_reset);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_fifo_reset(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_FIFO_RESET);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_capture_next_edge(HW_SPI_ID id, HW_SPI_MASTER_EDGE_CAPTURE capture_next_edge)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_CAPTURE_AT_NEXT_EDGE, capture_next_edge);
}
 
__STATIC_INLINE HW_SPI_MASTER_EDGE_CAPTURE hw_spi_get_ctrl_reg_capture_next_edge(HW_SPI_ID id)
{
        return (HW_SPI_MASTER_EDGE_CAPTURE) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_CAPTURE_AT_NEXT_EDGE);
}
 
__STATIC_INLINE void hw_spi_set_ctrl_reg_swap_bytes(HW_SPI_ID id, bool swap_bytes)
{
        HW_SPI_REG_SETF(id, SPI_CTRL_REG, SPI_SWAP_BYTES, swap_bytes);
}
 
__STATIC_INLINE bool hw_spi_get_ctrl_reg_swap_bytes(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_CTRL_REG, SPI_SWAP_BYTES);
}
 
/***************** SPI_CONFIG_REG Functions *****************/
 
__STATIC_INLINE void hw_spi_set_config_reg(HW_SPI_ID id, uint32_t spi_config_reg)
{
        SBA(id)->SPI_CONFIG_REG = spi_config_reg;
}
 
__STATIC_INLINE uint32_t hw_spi_get_config_reg(HW_SPI_ID id)
{
        return SBA(id)->SPI_CONFIG_REG;
}
 
__STATIC_INLINE void hw_spi_set_config_reg_spi_mode(HW_SPI_ID id, HW_SPI_MODE_CPOL_CPHA spi_cp)
{
        HW_SPI_REG_SETF(id, SPI_CONFIG_REG, SPI_MODE, spi_cp);
}
 
__STATIC_INLINE HW_SPI_MODE_CPOL_CPHA hw_spi_get_config_reg_spi_mode(HW_SPI_ID id)
{
        return (HW_SPI_MODE_CPOL_CPHA) HW_SPI_REG_GETF(id, SPI_CONFIG_REG, SPI_MODE);
}
 
__STATIC_INLINE void hw_spi_set_config_reg_word_len(HW_SPI_ID id, HW_SPI_WORD spi_wsz)
{
        HW_SPI_REG_SETF(id, SPI_CONFIG_REG, SPI_WORD_LENGTH, spi_wsz);
}
 
__STATIC_INLINE HW_SPI_WORD hw_spi_get_config_reg_word_len(HW_SPI_ID id)
{
        return (HW_SPI_WORD) HW_SPI_REG_GETF(id, SPI_CONFIG_REG, SPI_WORD_LENGTH);
}
 
__STATIC_INLINE void hw_spi_set_config_reg_slave_en(HW_SPI_ID id, HW_SPI_MODE spi_ms)
{
        HW_SPI_REG_SETF(id, SPI_CONFIG_REG, SPI_SLAVE_EN, spi_ms);
}
 
__STATIC_INLINE HW_SPI_MODE hw_spi_get_config_reg_slave_en(HW_SPI_ID id)
{
        return (HW_SPI_MODE) HW_SPI_REG_GETF(id, SPI_CONFIG_REG, SPI_SLAVE_EN);
}
 
/***************** SPI_CLOCK_REG Functions *****************/
 
__STATIC_INLINE bool hw_spi_get_clock_en(const HW_SPI_ID id)
{
        return (bool) REG_GETF(CRG_COM, CLK_COM_REG, SPI_ENABLE);
}
 
__STATIC_INLINE void hw_spi_set_clock_reg(HW_SPI_ID id, uint8_t spi_clock_reg)
{
        SBA(id)->SPI_CLOCK_REG = spi_clock_reg;
}
 
__STATIC_INLINE uint8_t hw_spi_get_clock_reg(HW_SPI_ID id)
{
        return SBA(id)->SPI_CLOCK_REG;
}
 
__STATIC_INLINE void hw_spi_set_clock_reg_clk_div(HW_SPI_ID id, HW_SPI_FREQ spi_clk_div)
{
        ASSERT_WARNING(spi_clk_div <= SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Msk);
        HW_SPI_REG_SETF(id, SPI_CLOCK_REG, SPI_CLK_DIV, spi_clk_div);
}
 
__STATIC_INLINE HW_SPI_FREQ hw_spi_get_clock_reg_clk_div(HW_SPI_ID id)
{
        return (HW_SPI_FREQ) HW_SPI_REG_GETF(id, SPI_CLOCK_REG, SPI_CLK_DIV);
}
 
/***************** SPI_FIFO_CONFIG_REG Functions *****************/
 
__STATIC_INLINE void hw_spi_set_fifo_config_reg(HW_SPI_ID id, uint8_t val)
{
        SBA(id)->SPI_FIFO_CONFIG_REG = val;
}
 
__STATIC_INLINE uint32_t hw_spi_get_fifo_config_reg(HW_SPI_ID id)
{
        return SBA(id)->SPI_FIFO_CONFIG_REG;
}
 
__STATIC_INLINE void hw_spi_set_fifo_config_reg_tx_tl(HW_SPI_ID id, HW_SPI_FIFO_TL spi_tx_tl)
{
        ASSERT_WARNING(spi_tx_tl <= hw_spi_get_fifo_depth_in_bytes(id));
        HW_SPI_REG_SETF(id, SPI_FIFO_CONFIG_REG, SPI_TX_TL, spi_tx_tl);
}
 
__STATIC_INLINE HW_SPI_FIFO_TL hw_spi_get_fifo_config_reg_tx_tl(HW_SPI_ID id)
{
        return (HW_SPI_FIFO_TL) HW_SPI_REG_GETF(id, SPI_FIFO_CONFIG_REG, SPI_TX_TL);
}
 
__STATIC_INLINE void hw_spi_set_fifo_config_reg_rx_tl(HW_SPI_ID id, HW_SPI_FIFO_TL spi_rx_tl)
{
        ASSERT_WARNING(spi_rx_tl < hw_spi_get_fifo_depth_in_bytes(id));
        HW_SPI_REG_SETF(id, SPI_FIFO_CONFIG_REG, SPI_RX_TL, spi_rx_tl);
}
 
__STATIC_INLINE HW_SPI_FIFO_TL hw_spi_get_fifo_config_reg_rx_tl(HW_SPI_ID id)
{
        return (HW_SPI_FIFO_TL) HW_SPI_REG_GETF(id, SPI_FIFO_CONFIG_REG, SPI_RX_TL);
}
 
 
/***************** SPI_IRQ_MASK_REG Functions *****************/
__STATIC_INLINE void hw_spi_set_irq_mask_reg_tx_empty_en(HW_SPI_ID id, HW_SPI_MINT irq_tx_empty_en)
{
        HW_SPI_REG_SETF(id, SPI_IRQ_MASK_REG, SPI_IRQ_MASK_TX_EMPTY, irq_tx_empty_en);
}
 
__STATIC_INLINE HW_SPI_MINT hw_spi_get_irq_mask_reg_tx_empty_en(HW_SPI_ID id)
{
        return (HW_SPI_MINT) HW_SPI_REG_GETF(id, SPI_IRQ_MASK_REG, SPI_IRQ_MASK_TX_EMPTY);
}
 
__STATIC_INLINE void hw_spi_set_irq_mask_reg_rx_full_en(HW_SPI_ID id, HW_SPI_MINT irq_rx_full_en)
{
        HW_SPI_REG_SETF(id, SPI_IRQ_MASK_REG, SPI_IRQ_MASK_RX_FULL, irq_rx_full_en);
}
 
__STATIC_INLINE HW_SPI_MINT hw_spi_get_irq_mask_reg_rx_full_en(HW_SPI_ID id)
{
        return (HW_SPI_MINT) HW_SPI_REG_GETF(id, SPI_IRQ_MASK_REG, SPI_IRQ_MASK_RX_FULL);
}
 
 
/***************** SPI_STATUS_REG Functions *****************/
 
__STATIC_INLINE bool hw_spi_get_status_reg_tx_fifo_empty(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_STATUS_REG, SPI_STATUS_TX_EMPTY);
}
 
__STATIC_INLINE bool hw_spi_get_status_reg_rx_fifo_full(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_STATUS_REG, SPI_STATUS_RX_FULL);
}
 
 
/***************** SPI_FIFO_STATUS_REG Functions *****************/
 
__STATIC_INLINE uint16_t hw_spi_get_fifo_status_reg(HW_SPI_ID id)
{
    return  SBA(id)->SPI_FIFO_STATUS_REG;
}
 
__STATIC_INLINE bool hw_spi_get_fifo_status_reg_transaction_active(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_FIFO_STATUS_REG, SPI_TRANSACTION_ACTIVE);
}
 
__STATIC_INLINE uint8_t hw_spi_get_fifo_status_reg_tx_fifo_level(HW_SPI_ID id)
{
        return (uint8_t) HW_SPI_REG_GETF(id, SPI_FIFO_STATUS_REG, SPI_TX_FIFO_LEVEL);
}
 
__STATIC_INLINE bool hw_spi_get_fifo_status_reg_rx_empty(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_FIFO_STATUS_REG, SPI_STATUS_RX_EMPTY);
}
 
__STATIC_INLINE uint8_t hw_spi_get_fifo_status_reg_rx_fifo_level(HW_SPI_ID id)
{
        return (uint8_t) HW_SPI_REG_GETF(id, SPI_FIFO_STATUS_REG, SPI_RX_FIFO_LEVEL);
}
 
__STATIC_INLINE uint8_t hw_spi_get_fifo_status_reg_rx_fifo_overflow(HW_SPI_ID id)
{
        return (uint8_t) HW_SPI_REG_GETF(id, SPI_FIFO_STATUS_REG, SPI_RX_FIFO_OVFL);
}
 
 
/***************** SPI_FIFO_READ_REG Functions *****************/
 
__STATIC_INLINE uint32_t hw_spi_get_fifo_read_reg(HW_SPI_ID id)
{
        return SBA(id)->SPI_FIFO_READ_REG;
}
 
 
/***************** SPI_FIFO_WRITE_REG Functions *****************/
 
__STATIC_INLINE void hw_spi_set_fifo_write_reg(HW_SPI_ID id, uint32_t tx_data)
{
        SBA(id)->SPI_FIFO_WRITE_REG = tx_data;
}
 
 
/***************** SPI_CS_CONFIG_REG Functions *****************/
 
__STATIC_INLINE void hw_spi_set_cs_config_reg_mode(HW_SPI_ID id, HW_SPI_CS_MODE cs_mode)
{
        SBA(id)->SPI_CS_CONFIG_REG = cs_mode;
}
 
__STATIC_INLINE HW_SPI_CS_MODE hw_spi_get_cs_config_reg_mode(HW_SPI_ID id)
{
    return (HW_SPI_CS_MODE) SBA(id)->SPI_CS_CONFIG_REG;
}
 
 
/***************** SPI_TXBUFFER_FORCE_REG Functions *****************/
 
__STATIC_INLINE void hw_spi_set_txbuffer_force_reg(HW_SPI_ID id, uint32_t tx_data)
{
        SBA(id)->SPI_TXBUFFER_FORCE_REG = tx_data;
}
 
 
//============== Interrupt handling ============================================
__STATIC_INLINE void hw_spi_enable_interrupt(HW_SPI_ID id)
{
        uint32_t tmp = SBA(id)->SPI_IRQ_MASK_REG;
        if (hw_spi_get_ctrl_reg_tx_en(id) == true) {
                HW_SPI_REG_SET_FIELD(SPI_IRQ_MASK, SPI_IRQ_MASK_TX_EMPTY, tmp, HW_SPI_MINT_ENABLE);
        }
        if (hw_spi_get_ctrl_reg_rx_en(id) == true) {
                HW_SPI_REG_SET_FIELD(SPI_IRQ_MASK, SPI_IRQ_MASK_RX_FULL, tmp, HW_SPI_MINT_ENABLE);
        }
        SBA(id)->SPI_IRQ_MASK_REG = tmp;
}
 
__STATIC_INLINE void hw_spi_disable_interrupt(HW_SPI_ID id)
{
        uint32_t tmp = SBA(id)->SPI_IRQ_MASK_REG;
        HW_SPI_REG_SET_FIELD(SPI_IRQ_MASK, SPI_IRQ_MASK_RX_FULL, tmp, HW_SPI_MINT_DISABLE);
        HW_SPI_REG_SET_FIELD(SPI_IRQ_MASK, SPI_IRQ_MASK_TX_EMPTY, tmp, HW_SPI_MINT_DISABLE);
        SBA(id)->SPI_IRQ_MASK_REG = tmp;
}
 
__STATIC_INLINE HW_SPI_MINT hw_spi_is_interrupt_enabled(HW_SPI_ID id)
{
        return !!(hw_spi_get_irq_mask_reg_tx_empty_en(id) && hw_spi_get_irq_mask_reg_rx_full_en(id));
}
 
 
//==================== Configuration functions =================================
 
__STATIC_INLINE void hw_spi_enable(HW_SPI_ID id, uint8_t on)
{
        if (on) {
                hw_spi_set_ctrl_reg_spi_en(id, true);
        } else {
                hw_spi_set_ctrl_reg_spi_en(id, false);
        }
}
 
__STATIC_INLINE uint8_t hw_spi_is_enabled(HW_SPI_ID id)
{
        return hw_spi_get_ctrl_reg_spi_en(id);
}
 
__STATIC_INLINE void hw_spi_set_clock_freq(HW_SPI_ID id, HW_SPI_FREQ freq)
{
        hw_spi_set_clock_reg_clk_div(id, freq);
}
 
__STATIC_INLINE HW_SPI_FREQ hw_spi_get_clock_freq(HW_SPI_ID id)
{
        return hw_spi_get_clock_reg_clk_div(id);
}
 
 
__STATIC_INLINE void hw_spi_set_mode(HW_SPI_ID id, HW_SPI_MODE smn)
{
        hw_spi_set_config_reg_slave_en(id, smn);
}
 
__STATIC_INLINE HW_SPI_MODE hw_spi_is_slave(HW_SPI_ID id)
{
        return hw_spi_get_config_reg_slave_en(id);
}
 
__STATIC_INLINE void hw_spi_set_word_size(HW_SPI_ID id, HW_SPI_WORD word)
{
        hw_spi_set_config_reg_word_len(id, word);
}
 
__STATIC_INLINE HW_SPI_WORD hw_spi_get_word_size(HW_SPI_ID id)
{
#if HW_SPI1_USE_FIXED_WORD_SIZE == 1
                return (HW_SPI1_FIXED_WORD_SIZE);
#else
                // Get value of SPI master/slave mode from SPI control register
                return hw_spi_get_config_reg_word_len(id);
#endif
}
 
__STATIC_INLINE uint32_t hw_spi_get_memory_word_size(HW_SPI_ID id)
{
        // Register Value = 3..31 -> Actual Wordsize = 4..32bits
        // E.g. Register Value = 3..7bits => Actual Wordsize = 4..8bits => Mem_wsz = 1Byte
        uint32_t mem_wsz = (hw_spi_get_word_size(id)>>3) + 1;
        if (mem_wsz == 3) {
                mem_wsz++;
        }
        return mem_wsz;
}
 
 
__STATIC_INLINE bool hw_spi_is_tx_fifo_full(HW_SPI_ID id)
{
        return (bool) HW_SPI_REG_GETF(id, SPI_FIFO_STATUS_REG, SPI_STATUS_TX_FULL);
}
 
 
void hw_spi_init_clk_reg(const HW_SPI_ID id, bool select_divn);
 
void hw_spi_deinit_clk_reg(const HW_SPI_ID id);
 
void hw_spi_init(HW_SPI_ID id, const hw_spi_config_t *cfg);
 
//=========================== CS handling functions ============================
void hw_spi_set_cs_pad(HW_SPI_ID id, const SPI_Pad *pad, HW_SPI_CS_MODE cs_mode, bool validate);
 
void hw_spi_set_cs_low(HW_SPI_ID id);
 
void hw_spi_set_cs_high(HW_SPI_ID id);
 
 
//=========================== FIFO control functions ===========================
 
void hw_spi_set_fifo_mode(HW_SPI_ID id, HW_SPI_FIFO mode);
 
HW_SPI_FIFO hw_spi_get_fifo_mode(HW_SPI_ID id);
 
HW_SPI_FIFO hw_spi_change_fifo_mode(HW_SPI_ID id, HW_SPI_FIFO mode);
 
#if (HW_SPI_DMA_SUPPORT == 1)
//=========================== DMA control functions ============================
 
void hw_spi_configure_dma_channels(HW_SPI_ID id, HW_DMA_CHANNEL rx_channel, const hw_spi_dma_prio_t *prio);
 
#endif /* HW_SPI_DMA_SUPPORT */
 
//=========================== Other functions ============================
 
__STATIC_INLINE uint8_t hw_spi_is_busy(HW_SPI_ID id)
{
        // Get the value of the SPI BUSY bit from the secondary SPI control register
        return hw_spi_get_fifo_status_reg_transaction_active(id) ? 1 : 0;
}
 
__STATIC_INLINE void hw_spi_wait_while_busy(HW_SPI_ID id)
{
        while (hw_spi_is_busy(id));
}
 
void hw_spi_deinit(HW_SPI_ID id);
 
bool hw_spi_is_occupied(const HW_SPI_ID id);
 
 
#endif /* dg_configUSE_HW_SPI */
#endif /* HW_SPI_H_ */