hw_fcu.h

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#ifndef HW_FCU_H_
#define HW_FCU_H_
 
#if dg_configUSE_HW_FCU
 
#include <stdbool.h>
#include "sdk_defs.h"
#include "hw_dma.h"
 
/*
 * The following macros are defined according to FCU properties and its registers default values
 * and size in bits
 */
#define HW_FCU_FLASH_PAGE_SIZE_IN_BYTES (2048)
#define HW_FCU_FLASH_PAGE_SIZE_IN_WORDS (HW_FCU_FLASH_PAGE_SIZE_IN_BYTES / 4)
 
#define HW_FCU_ERASE_FLASH_PAGE_MIN_TIME (0x13880)
/*
 * FLASH_PTERASE_REG[PTERASE] field is 24 bits but FCU hardware only uses
 * 18 bits, so maximum erase time is 262143 us
 */
#define HW_FCU_ERASE_FLASH_PAGE_MAX_TIME (0x3FFFF)
 
#define HW_FCU_ERASE_FLASH_BLOCK_MIN_TIME (0x13880)
/*
 * FLASH_PTME_REG[PTME] field is 24 bits but FCU hardware only uses
 * 18 bits, so maximum erase time is 262143 us
 */
#define HW_FCU_ERASE_FLASH_BLOCK_MAX_TIME (0x3FFFF)
 
#define HW_FCU_ERASE_FLASH_PAGE_SEGMENT_MIN_TIME (0x3E8)
/*
 * FLASH_PTERASE_SEG_REG[PTERASE_SEG] field is 24 bits but FCU hardware only uses
 * 18 bits, so maximum erase time is 262143 us
 */
#define HW_FCU_ERASE_FLASH_PAGE_SEGMENT_MAX_TIME (0x3FFFF)
 
typedef enum {
        HW_FCU_ERROR_ERASE_IN_PROGRESS = -5,
        HW_FCU_ERROR_WRITE_IN_PROGRESS = -4,
        HW_FCU_ERROR_PROTECTED_AGAINST_ACTION = -3,
        HW_FCU_ERROR_INVALID_ADDRESS = -2,
        HW_FCU_ERROR_INVALID_FUNCTION_INPUT = -1,
        HW_FCU_ERROR_NONE = 0
} HW_FCU_ERROR;
 
typedef enum {
        HW_FCU_ERASE_SUSPEND_MODE_PREEMPTIVE,     
        HW_FCU_ERASE_SUSPEND_MODE_NONPREEMPTIVE , 
} HW_FCU_ERASE_SUSPEND_MODE;
 
typedef enum {
        HW_FCU_FLASH_ACCESS_MODE_READ,        
        HW_FCU_FLASH_ACCESS_MODE_WRITE_ERASE, 
} HW_FCU_FLASH_ACCESS_MODE;
 
typedef enum {
        HW_FCU_FLASH_PROG_MODE_READ,           
        HW_FCU_FLASH_PROG_MODE_WRITE_PAGE,     
        HW_FCU_FLASH_PROG_MODE_ERASE_PAGE,     
        HW_FCU_FLASH_PROG_MODE_ERASE_BLOCK,    
} HW_FCU_FLASH_PROG_MODE;
 
typedef enum {
        HW_FCU_WAIT_CYCLES_0,
        HW_FCU_WAIT_CYCLES_1,
        HW_FCU_WAIT_CYCLES_2,
        HW_FCU_WAIT_CYCLES_3,
        HW_FCU_WAIT_CYCLES_4,
        HW_FCU_WAIT_CYCLES_5,
        HW_FCU_WAIT_CYCLES_6,
        HW_FCU_WAIT_CYCLES_7,
        HW_FCU_WAIT_CYCLES_MAX
} HW_FCU_WAIT_CYCLES;
 
typedef enum {
        HW_FCU_VDD_LESS_THAN_1V08,      
        HW_FCU_VDD_GREATER_THAN_1V08    
} HW_FCU_VDD_LEVEL_VALUE;
 
typedef void (*hw_fcu_operation_completed_cb)(void *user_data);
 
struct hw_fcu_operation_params_t {
        hw_fcu_operation_completed_cb cb;       
        void *user_data;                        
#if dg_configUSE_HW_DMA
        HW_DMA_CHANNEL dma_channel;             
#endif
};
 
__STATIC_FORCEINLINE void hw_fcu_set_vdd_level_value(HW_FCU_VDD_LEVEL_VALUE value)
{
        REG_SETF(FCU, FLASH_CTRL_REG, VDD_LEVEL_VALUE, value);
}
 
__STATIC_FORCEINLINE HW_FCU_VDD_LEVEL_VALUE hw_fcu_get_vdd_level_value(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, VDD_LEVEL_VALUE);
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_vdd_level_overriding(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, VDD_LEVEL_FORCE);
}
 
__STATIC_FORCEINLINE void hw_fcu_disable_vdd_level_overriding(void)
{
        REG_CLR_BIT(FCU, FLASH_CTRL_REG, VDD_LEVEL_FORCE);
}
 
__STATIC_FORCEINLINE void hw_fcu_prohibit_flash_operations(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, FLASH_PROT);
}
 
__STATIC_FORCEINLINE void hw_fcu_permit_flash_operations(void)
{
        REG_CLR_BIT(FCU, FLASH_CTRL_REG, FLASH_PROT);
}
 
__STATIC_FORCEINLINE bool hw_fcu_are_flash_operations_prohibited(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, FLASH_PROT) == 1;
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_flash_erase_suspended(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_STAT) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_set_erase_suspend_mode(HW_FCU_ERASE_SUSPEND_MODE mode)
{
        REG_SETF(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_MODE, mode);
}
 
__STATIC_FORCEINLINE HW_FCU_ERASE_SUSPEND_MODE hw_fcu_get_erase_suspend_mode(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_MODE);
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_erase_suspend(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_EN);
}
 
__STATIC_FORCEINLINE void hw_fcu_disable_erase_suspend(void)
{
        REG_CLR_BIT(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_EN);
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_erase_suspend_enabled(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_EN) == 1;
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_asleep(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, SLEEP) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_dma(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, DMA_EN);
}
 
__STATIC_FORCEINLINE void hw_fcu_disable_dma(void)
{
        REG_CLR_BIT(FCU, FLASH_CTRL_REG, DMA_EN);
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_dma_enabled(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, DMA_EN) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_bus_error(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, BUS_ERROR_EN);
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_bus_error_enabled(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, BUS_ERROR_EN) == 1;
}
 
__STATIC_FORCEINLINE bool hw_fcu_get_bus_error_status(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, BUS_ERROR) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_clear_interrupt(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, IRQ_CLEAR);
}
 
__STATIC_FORCEINLINE HW_FCU_WAIT_CYCLES hw_fcu_get_wait_cycles(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, WAIT_CYCLES);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_wait_cycles(HW_FCU_WAIT_CYCLES wait_cycles)
{
        ASSERT_WARNING(wait_cycles < HW_FCU_WAIT_CYCLES_MAX);
 
        REG_SETF(FCU, FLASH_CTRL_REG, WAIT_CYCLES, wait_cycles);
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_protected_against_actions(uint32_t mask)
{
     return ((FCU->FLASH_CTRL_REG & mask) != 0);
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_flash_read_protection(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, FLASH_RPROT);
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_flash_read_protection_enabled(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, FLASH_RPROT) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_flash_write_protection(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, FLASH_WPROT);
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_flash_write_protection_enabled(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, FLASH_WPROT) == 1;
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_flash_read_mode_inhibited(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, PROG_RMIN) == 1;
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_erase_in_progress(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, PROG_ERS) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_resume_erase(void)
{
        uint32_t reg_val = FCU->FLASH_CTRL_REG;
        uint32_t mask = REG_MSK(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_EN) |
                        REG_MSK(FCU, FLASH_CTRL_REG, ERASE_SUSPEND_STAT);
 
        if (mask == (reg_val & mask)) {
                REG_SET_BIT(FCU, FLASH_CTRL_REG, ERASE_RESUME);
                while (!hw_fcu_is_erase_in_progress());
        }
}
 
__STATIC_FORCEINLINE bool hw_fcu_is_write_in_progress(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, PROG_WRS) == 1;
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_access_mode(HW_FCU_FLASH_ACCESS_MODE mode)
{
        REG_SETF(FCU, FLASH_CTRL_REG, PROG_SEL, mode);
}
 
__STATIC_FORCEINLINE HW_FCU_FLASH_ACCESS_MODE hw_fcu_get_flash_access_mode(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, PROG_SEL);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_programming_mode(HW_FCU_FLASH_PROG_MODE mode)
{
        REG_SETF(FCU, FLASH_CTRL_REG, PROG_MODE, mode);
}
 
__STATIC_FORCEINLINE HW_FCU_FLASH_PROG_MODE hw_fcu_get_flash_programming_mode(void)
{
        return REG_GETF(FCU, FLASH_CTRL_REG, PROG_MODE);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_sleep_mode(void)
{
        REG_SET_BIT(FCU, FLASH_CTRL_REG, SLEEP_MODE);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_hold_time(uint16_t hold_time)
{
        ASSERT_WARNING(hold_time >= 100);
        REG_SETF(FCU, FLASH_PTNVH1_REG, PTNVH1, hold_time);
}
 
__STATIC_FORCEINLINE uint16_t hw_fcu_get_flash_hold_time(void)
{
        return REG_GETF(FCU, FLASH_PTNVH1_REG, PTNVH1);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_program_time(uint16_t prog_time)
{
        ASSERT_WARNING(prog_time >= 8);
        REG_SETF(FCU, FLASH_PTPROG_REG, PTPROG, prog_time);
}
 
__STATIC_FORCEINLINE uint16_t hw_fcu_get_flash_program_time(void)
{
        return REG_GETF(FCU, FLASH_PTPROG_REG, PTPROG);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_page_erase_time(uint32_t erase_time)
{
        ASSERT_WARNING(erase_time >= HW_FCU_ERASE_FLASH_PAGE_MIN_TIME &&
                       erase_time < HW_FCU_ERASE_FLASH_PAGE_MAX_TIME + 1);
        REG_SETF(FCU, FLASH_PTERASE_REG, PTERASE, erase_time);
}
 
__STATIC_FORCEINLINE uint32_t hw_fcu_get_flash_page_erase_time(void)
{
        return REG_GETF(FCU, FLASH_PTERASE_REG, PTERASE);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_mass_erase_time(uint32_t erase_time)
{
        ASSERT_WARNING(erase_time >= HW_FCU_ERASE_FLASH_BLOCK_MIN_TIME &&
                       erase_time < HW_FCU_ERASE_FLASH_BLOCK_MAX_TIME + 1);
        REG_SETF(FCU, FLASH_PTME_REG, PTME, erase_time);
}
 
__STATIC_FORCEINLINE uint32_t hw_fcu_get_flash_mass_erase_time(void)
{
        return REG_GETF(FCU, FLASH_PTME_REG, PTME);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_sleep_to_standby_time(uint8_t wakeup_time)
{
        ASSERT_WARNING(wakeup_time >= 3);
        REG_SETF(FCU, FLASH_PTWK_SP_REG, PTWK_SP, wakeup_time);
}
 
__STATIC_FORCEINLINE uint8_t hw_fcu_get_flash_sleep_to_standby_time(void)
{
        return REG_GETF(FCU, FLASH_PTWK_SP_REG, PTWK_SP);
}
 
__STATIC_FORCEINLINE void hw_fcu_set_flash_page_segment_erase_time(uint32_t erase_time)
{
        ASSERT_WARNING(erase_time >= HW_FCU_ERASE_FLASH_PAGE_SEGMENT_MIN_TIME &&
                       erase_time < HW_FCU_ERASE_FLASH_PAGE_SEGMENT_MAX_TIME + 1);
        REG_SETF(FCU, FLASH_PTERASE_SEG_REG, PTERASE_SEG, erase_time);
}
 
__STATIC_FORCEINLINE uint32_t hw_fcu_get_flash_page_segment_erase_time(void)
{
        return REG_GETF(FCU, FLASH_PTERASE_SEG_REG, PTERASE_SEG);
}
 
__STATIC_FORCEINLINE uint32_t hw_fcu_get_total_erase_counter(void)
{
        return REG_GETF(FCU, FLASH_RTERASE_TOT_CNT_REG, RTERASE_TOT_CNT);
}
 
__STATIC_FORCEINLINE uint32_t hw_fcu_get_segment_erase_counter(void)
{
        return REG_GETF(FCU, FLASH_RTERASE_SEG_CNT_REG, RTERASE_SEG_CNT);
}
 
__STATIC_FORCEINLINE void hw_fcu_enable_reset_delay(void)
{
        REG_SET_BIT(CRG_TOP, RST_CTRL_REG, GATE_RST_WITH_FCU);
}
 
__STATIC_FORCEINLINE void hw_fcu_disable_reset_delay(void)
{
        REG_CLR_BIT(CRG_TOP, RST_CTRL_REG, GATE_RST_WITH_FCU);
}
 
__ALWAYS_RETAINED_CODE void hw_fcu_wakeup(void);
 
__ALWAYS_RETAINED_CODE void hw_fcu_sleep(void);
 
__ALWAYS_RETAINED_CODE void hw_fcu_enable_erase(HW_FCU_FLASH_PROG_MODE mode);
 
__ALWAYS_RETAINED_CODE HW_FCU_ERROR hw_fcu_erase_page(uint32_t address,
                                               struct hw_fcu_operation_params_t *params);
 
__ALWAYS_RETAINED_CODE HW_FCU_ERROR hw_fcu_configure_erase_page_suspend(HW_FCU_ERASE_SUSPEND_MODE mode,
                                                                 uint32_t page_erase_time,
                                                                 uint32_t segment_erase_time);
 
__ALWAYS_RETAINED_CODE HW_FCU_ERROR hw_fcu_erase_block(uint32_t address,
                                                struct hw_fcu_operation_params_t *params);
 
__ALWAYS_RETAINED_CODE void hw_fcu_enable_write(void);
 
__ALWAYS_RETAINED_CODE HW_FCU_ERROR hw_fcu_write(uint32_t *src, uint32_t address, uint32_t len,
                                          struct hw_fcu_operation_params_t *params);
 
__ALWAYS_RETAINED_CODE void hw_fcu_enable_read(void);
 
__ALWAYS_RETAINED_CODE HW_FCU_ERROR hw_fcu_read(uint32_t address, uint32_t *dst, uint32_t len,
                                         struct hw_fcu_operation_params_t *params);
 
__ALWAYS_RETAINED_CODE bool hw_fcu_is_available(void);
 
#endif /* dg_configUSE_HW_FCU */
#endif /* HW_FCU_H_ */