hw_pmu_da1459x.h

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#ifndef HW_PMU_DA1459x_H_
#define HW_PMU_DA1459x_H_
 
 
#if dg_configUSE_HW_PMU
 
 
#include "sdk_defs.h"
 
typedef enum {
        HW_PMU_ERROR_NOERROR                    = 0,        
        HW_PMU_ERROR_INVALID_ARGS               = 1,        
        HW_PMU_ERROR_NOT_ENOUGH_POWER           = 2,        
        HW_PMU_ERROR_XTAL32M_DBLR_ON            = 3,        
        HW_PMU_ERROR_XTAL32M_ON                 = 4,        
        HW_PMU_ERROR_RC32M_ON                   = 5,        
        HW_PMU_ERROR_RCX_ON                     = 6,        
        HW_PMU_ERROR_RCX_LP                     = 7,        
        HW_PMU_ERROR_XTAL32K_ON                 = 8,        
        HW_PMU_ERROR_XTAL32K_LP                 = 9,        
        HW_PMU_ERROR_FAST_WAKEUP_ON             = 10,       
        HW_PMU_ERROR_ACTION_NOT_POSSIBLE        = 11,       
        HW_PMU_ERROR_OTHER_LOADS_DEPENDENCY     = 12,       
        HW_PMU_ERROR_BOD_IS_ACTIVE              = 13,       
        HW_PMU_ERROR_BOD_THRESHOLD              = 14,       
        HW_PMU_ERROR_SLEEP_LDO                  = 15,       
        HW_PMU_ERROR_EFLASH_OPS                 = 16        
} HW_PMU_ERROR_CODE;
 
typedef enum {
        HW_PMU_SRC_TYPE_LDO_LOW_RIPPLE       = 0,   
        HW_PMU_SRC_TYPE_DCDC_HIGH_EFFICIENCY = 1,   
        HW_PMU_SRC_TYPE_VBAT                 = 2    
} HW_PMU_SRC_TYPE;
 
typedef enum {
        POWER_RAIL_DISABLED = 0,        
        POWER_RAIL_ENABLED  = 1         
} HW_PMU_POWER_RAIL_STATE;
 
typedef enum {
        HW_PMU_1V8_VOLTAGE_1V8 = 0      
} HW_PMU_1V8_VOLTAGE;
 
typedef enum {
        HW_PMU_1V8_MAX_LDO_LOAD_2       = 0,    
        HW_PMU_1V8_MAX_BYPASS_LOAD_2    = 1,    
        HW_PMU_1V8_MAX_LDO_LOAD_20      = 2,    
        HW_PMU_1V8_MAX_BYPASS_LOAD_20   = 3,    
} HW_PMU_1V8_MAX_LOAD;
 
typedef struct {
        HW_PMU_1V8_VOLTAGE voltage;
        HW_PMU_1V8_MAX_LOAD current;
        HW_PMU_SRC_TYPE src_type;
} HW_PMU_1V8_RAIL_CONFIG;
 
 
typedef enum {
        HW_PMU_VDCDC_VOLTAGE_1V10       = 0,    
        HW_PMU_VDCDC_VOLTAGE_1V15       = 1,    
        HW_PMU_VDCDC_VOLTAGE_1V20       = 2,    
        HW_PMU_VDCDC_VOLTAGE_1V25       = 3,    
        HW_PMU_VDCDC_VOLTAGE_1V30       = 4,    
        HW_PMU_VDCDC_VOLTAGE_1V35       = 5,    
        HW_PMU_VDCDC_VOLTAGE_1V40       = 6,    
        HW_PMU_VDCDC_VOLTAGE_1V45       = 7     
} HW_PMU_VDCDC_VOLTAGE;
 
typedef enum {
        HW_PMU_VDCDC_MAX_DCDC_LOAD_0_300        = 0,    
        HW_PMU_VDCDC_MAX_LDO_LOAD_1             = 1,    
        HW_PMU_VDCDC_MAX_DCDC_LOAD_40           = 2,    
        HW_PMU_VDCDC_MAX_LDO_LOAD_40            = 3     
} HW_PMU_VDCDC_MAX_LOAD;
 
typedef struct {
        HW_PMU_VDCDC_VOLTAGE voltage;
        HW_PMU_VDCDC_MAX_LOAD current;
        HW_PMU_SRC_TYPE src_type;
} HW_PMU_VDCDC_RAIL_CONFIG;
 
 
typedef enum {
        /* active state */
        HW_PMU_VDD_VOLTAGE_0V90         = 0,    
        HW_PMU_VDD_VOLTAGE_0V95         = 1,    
        HW_PMU_VDD_VOLTAGE_1V00         = 2,    
        HW_PMU_VDD_VOLTAGE_1V05         = 3,    
        HW_PMU_VDD_VOLTAGE_1V10         = 4,    
        HW_PMU_VDD_VOLTAGE_1V15         = 5,    
        HW_PMU_VDD_VOLTAGE_1V20         = 6,    
        HW_PMU_VDD_VOLTAGE_1V25         = 7,    
 
        /* sleep state
         * Only the last bit of the enumerated value is used
         * for programming the rail
         */
 
        HW_PMU_VDD_VOLTAGE_SLEEP_0V75   = 8,    
        HW_PMU_VDD_VOLTAGE_SLEEP_0V90   = 9,    
 
        HW_PMU_VDD_VOLTAGE_INVALID              
} HW_PMU_VDD_VOLTAGE;
 
typedef enum {
        HW_PMU_VDD_MAX_LOAD_20          = 0,    
        HW_PMU_VDD_MAX_LOAD_0_400       = 1     
} HW_PMU_VDD_MAX_LOAD;
 
typedef struct {
        HW_PMU_VDD_VOLTAGE voltage;
        HW_PMU_VDD_MAX_LOAD current;
        HW_PMU_SRC_TYPE src_type;
} HW_PMU_VDD_RAIL_CONFIG;
 
 
HW_PMU_ERROR_CODE hw_pmu_1v8_onwakeup_enable(HW_PMU_1V8_MAX_LOAD max_load);
 
HW_PMU_ERROR_CODE hw_pmu_1v8_onwakeup_disable(void);
 
HW_PMU_ERROR_CODE hw_pmu_1v8_onsleep_enable(HW_PMU_1V8_MAX_LOAD max_load);
 
HW_PMU_ERROR_CODE hw_pmu_1v8_onsleep_disable(void);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_1v8_active_config(HW_PMU_1V8_RAIL_CONFIG *rail_config);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_1v8_onwakeup_config(HW_PMU_1V8_RAIL_CONFIG *rail_config);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_1v8_onsleep_config(HW_PMU_1V8_RAIL_CONFIG *rail_config);
 
HW_PMU_ERROR_CODE hw_pmu_vdcdc_set_voltage(HW_PMU_VDCDC_VOLTAGE voltage);
 
HW_PMU_ERROR_CODE hw_pmu_vdcdc_onwakeup_enable(HW_PMU_VDCDC_MAX_LOAD max_load);
 
HW_PMU_ERROR_CODE hw_pmu_vdcdc_onwakeup_disable(void);
 
HW_PMU_ERROR_CODE hw_pmu_vdcdc_onsleep_enable(HW_PMU_VDCDC_MAX_LOAD max_load);
 
HW_PMU_ERROR_CODE hw_pmu_vdcdc_onsleep_disable(void);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_vdcdc_active_config(HW_PMU_VDCDC_RAIL_CONFIG *rail_config);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_vdcdc_onwakeup_config(HW_PMU_VDCDC_RAIL_CONFIG *rail_config);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_vdcdc_onsleep_config(HW_PMU_VDCDC_RAIL_CONFIG *rail_config);
 
HW_PMU_ERROR_CODE hw_pmu_vdd_set_voltage(HW_PMU_VDD_VOLTAGE voltage);
 
HW_PMU_ERROR_CODE hw_pmu_vdd_onwakeup_enable(HW_PMU_VDD_MAX_LOAD max_load);
 
HW_PMU_ERROR_CODE hw_pmu_vdd_onwakeup_disable(void);
 
HW_PMU_ERROR_CODE hw_pmu_vdd_onsleep_enable(HW_PMU_VDD_MAX_LOAD max_load);
 
HW_PMU_ERROR_CODE hw_pmu_vdd_onsleep_disable(void);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_vdd_active_config(HW_PMU_VDD_RAIL_CONFIG *rail_config);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_vdd_onwakeup_config(HW_PMU_VDD_RAIL_CONFIG *rail_config);
 
HW_PMU_POWER_RAIL_STATE hw_pmu_get_vdd_onsleep_config(HW_PMU_VDD_RAIL_CONFIG *rail_config);
 
 
#endif /* dg_configUSE_HW_PMU */
 
 
#endif /* HW_PMU_DA1459x_H_ */