Serial Peripheral Interface (SPI) Controller. More...

Files
file	hw_spi.h
	Serial Peripheral Interface (SPI) Low Level Driver (LLD) API definition.

Data Structures
struct	SPI_Pad
	SPI chip-select pin definition. More...

struct	hw_spi_config_t
	SPI configuration. More...

Macros
#define	HW_SPI1 ((void *)SPI_BASE)
	SPI controller number. More...

#define	HW_SPI_DMA_SUPPORT dg_configSPI_DMA_SUPPORT
	DMA support for SPI.

#define	HW_SPI1_USE_FIXED_WORD_SIZE (0)
	Use predefined (fixed) word size to optimize performance. More...

#define	HW_SPI_REG_SETF(id, reg, field, val)
	Write a value to an SPI register field. More...

#define	HW_SPI_REG_GETF(id, reg, field) ((SBA(id)->reg & (SPI_##reg##_##field##_Msk)) >> (SPI_##reg##_##field##_Pos))
	Get the value of an SPI register field. More...

#define	HW_SPI_REG_SET_FIELD(reg, field, var, val) REG_SET_FIELD(SPI, reg##_REG, field, var, val)
	Sets a field value of an SPI register. Aimed to be used with local variables. More...

#define	HW_SPI_ASSERT(id)
	Assertion for SPI control fields. More...

Typedefs
typedef uint8_t	HW_SPI_FREQ
	Source clock's divider for the selected SPI clock frequency. More...

Enumerations
enum	HW_SPI_WORD { HW_SPI_WORD_4BIT = 3, HW_SPI_WORD_5BIT, HW_SPI_WORD_6BIT, HW_SPI_WORD_7BIT, HW_SPI_WORD_8BIT, HW_SPI_WORD_9BIT, HW_SPI_WORD_10BIT, HW_SPI_WORD_11BIT, HW_SPI_WORD_12BIT, HW_SPI_WORD_13BIT, HW_SPI_WORD_14BIT, HW_SPI_WORD_15BIT, HW_SPI_WORD_16BIT, HW_SPI_WORD_17BIT, HW_SPI_WORD_18BIT, HW_SPI_WORD_19BIT, HW_SPI_WORD_20BIT, HW_SPI_WORD_21BIT, HW_SPI_WORD_22BIT, HW_SPI_WORD_23BIT, HW_SPI_WORD_24BIT, HW_SPI_WORD_25BIT, HW_SPI_WORD_26BIT, HW_SPI_WORD_27BIT, HW_SPI_WORD_28BIT, HW_SPI_WORD_29BIT, HW_SPI_WORD_30BIT, HW_SPI_WORD_31BIT, HW_SPI_WORD_32BIT }
	Word length. More...

enum	HW_SPI_MODE
	Master/slave mode. More...

enum	HW_SPI_MODE_CPOL_CPHA { HW_SPI_CP_MODE_0, HW_SPI_CP_MODE_1, HW_SPI_CP_MODE_2, HW_SPI_CP_MODE_3 }
	Defines the SPI mode Clock Polarity and Clock Phase (CPOL, CPHA) More...

enum	HW_SPI_MINT
	Disable/enable interrupts to the CPU. More...

enum	HW_SPI_MASTER_EDGE_CAPTURE { HW_SPI_MASTER_EDGE_CAPTURE_CURRENT, HW_SPI_MASTER_EDGE_CAPTURE_NEXT }
	Define the SPI master edge capture type. More...

enum	HW_SPI_CS_MODE { HW_SPI_CS_NONE = 0, HW_SPI_CS_0 = 1, HW_SPI_CS_1 = 2, HW_SPI_CS_GPIO = 4 }
	Control the CS output in master mode. More...

enum	HW_SPI_FIFO_TL { HW_SPI_FIFO_LEVEL0, HW_SPI_FIFO_LEVEL1, HW_SPI_FIFO_LEVEL2, HW_SPI_FIFO_LEVEL3, HW_SPI_FIFO_LEVEL4 }
	Define the SPI RX/TX FIFO threshold level in bytes. More...

enum	HW_SPI_FIFO { HW_SPI_FIFO_NONE = 0, HW_SPI_FIFO_RX_ONLY = REG_MSK(SPI, SPI_CTRL_REG, SPI_RX_EN), HW_SPI_FIFO_TX_ONLY = REG_MSK(SPI, SPI_CTRL_REG, SPI_TX_EN), HW_SPI_FIFO_RX_TX }
	FIFO mode. More...

Functions
__STATIC_INLINE uint16_t	hw_spi_fifo_read16 (HW_SPI_ID id)
	Read 4 to 16-bits from RX FIFO. More...

__STATIC_INLINE void	hw_spi_fifo_write16 (HW_SPI_ID id, uint16_t data)
	Write 4 to 16-bits to TX FIFO. More...

__STATIC_INLINE uint8_t	hw_spi_fifo_read8 (HW_SPI_ID id)
	Read 4 to 8-bits from RX FIFO. More...

__STATIC_INLINE void	hw_spi_fifo_write8 (HW_SPI_ID id, uint8_t data)
	Write 4 to 8-bits to TX FIFO. More...

__STATIC_INLINE uint32_t	hw_spi_fifo_read32 (HW_SPI_ID id)
	Read 4 to 32-bits from RX FIFO. More...

__STATIC_INLINE void	hw_spi_fifo_write32 (HW_SPI_ID id, uint32_t data)
	Write 4 to 32-bits to TX FIFO. More...

uint16_t	hw_spi_writeread (HW_SPI_ID id, uint16_t val)
	Writes/reads 4 to 16 bits to the SPI. More...

uint32_t	hw_spi_writeread32 (HW_SPI_ID id, uint32_t val)
	Writes/reads 4 to 32 bits to the SPI. More...

void	hw_spi_writeread_buf (HW_SPI_ID id, const uint8_t out_buf, uint8_t in_buf, uint16_t len, hw_spi_tx_callback cb, void *user_data)
	Write and reads array of bytes through SPI. More...

void	hw_spi_write_buf (HW_SPI_ID id, const uint8_t out_buf, uint16_t len, hw_spi_tx_callback cb, void user_data)
	Write array of bytes to SPI. More...

void	hw_spi_read_buf (HW_SPI_ID id, uint8_t in_buf, uint16_t len, hw_spi_tx_callback cb, void user_data)
	Reads array of bytes through SPI. More...

__STATIC_INLINE HW_SPI_FIFO_TL	hw_spi_get_fifo_depth_in_bytes (const HW_SPI_ID id)
	Get SPI fifo depth in bytes. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg (HW_SPI_ID id, uint32_t val)
	Set SPI Control Register Value. More...

__STATIC_INLINE uint32_t	hw_spi_get_ctrl_reg (HW_SPI_ID id)
	Get SPI Control Register Value. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_clear_enable (HW_SPI_ID id)
	Set SPI Control Register Value to clear SPI enable. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_spi_en (HW_SPI_ID id, bool spi_enable)
	Set SPI_EN in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_spi_en (HW_SPI_ID id)
	Get SPI_EN from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_tx_en (HW_SPI_ID id, bool spi_tx_enable)
	Set SPI_TX_EN in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_tx_en (HW_SPI_ID id)
	Get SPI_TX_EN from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_rx_en (HW_SPI_ID id, bool spi_rx_enable)
	Set SPI_RX_EN in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_rx_en (HW_SPI_ID id)
	Get SPI_RX_EN from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_dma_tx_en (HW_SPI_ID id, bool spi_dma_tx_enable)
	Set SPI_DMA_TX_EN in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_dma_tx_en (HW_SPI_ID id)
	Get SPI_DMA_TX_EN from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_dma_rx_en (HW_SPI_ID id, bool spi_dma_rx_enable)
	Set SPI_DMA_RX_EN in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_dma_rx_en (HW_SPI_ID id)
	Get SPI_DMA_RX_EN from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_fifo_reset (HW_SPI_ID id, bool spi_fifo_reset)
	Set SPI_FIFO_RESET in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_fifo_reset (HW_SPI_ID id)
	Get SPI_FIFO_RESET from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_capture_next_edge (HW_SPI_ID id, HW_SPI_MASTER_EDGE_CAPTURE capture_next_edge)
	Set SPI_CAPTURE_AT_NEXT_EDGE in Control Register. More...

__STATIC_INLINE HW_SPI_MASTER_EDGE_CAPTURE	hw_spi_get_ctrl_reg_capture_next_edge (HW_SPI_ID id)
	Get SPI_CAPTURE_AT_NEXT_EDGE from Control Register. More...

__STATIC_INLINE void	hw_spi_set_ctrl_reg_swap_bytes (HW_SPI_ID id, bool swap_bytes)
	Set SPI_SWAP_BYTES in Control Register. More...

__STATIC_INLINE bool	hw_spi_get_ctrl_reg_swap_bytes (HW_SPI_ID id)
	Get SPI_SWAP_BYTES from Control Register. More...

__STATIC_INLINE void	hw_spi_set_config_reg (HW_SPI_ID id, uint32_t spi_config_reg)
	Set SPI Configuration Register Value. More...

__STATIC_INLINE uint32_t	hw_spi_get_config_reg (HW_SPI_ID id)
	Get SPI Configuration Register Value. More...

__STATIC_INLINE void	hw_spi_set_config_reg_spi_mode (HW_SPI_ID id, HW_SPI_MODE_CPOL_CPHA spi_cp)
	Set SPI_MODE in Configuration Register. More...

__STATIC_INLINE HW_SPI_MODE_CPOL_CPHA	hw_spi_get_config_reg_spi_mode (HW_SPI_ID id)
	Get SPI_MODE from Configuration Register. More...

__STATIC_INLINE void	hw_spi_set_config_reg_word_len (HW_SPI_ID id, HW_SPI_WORD spi_wsz)
	Set SPI_WORD_LENGTH in Configuration Register. More...

__STATIC_INLINE HW_SPI_WORD	hw_spi_get_config_reg_word_len (HW_SPI_ID id)
	Get SPI_WORD_LENGTH from Configuration Register. More...

__STATIC_INLINE void	hw_spi_set_config_reg_slave_en (HW_SPI_ID id, HW_SPI_MODE spi_ms)
	Set SPI_SLAVE_EN in Configuration Register. More...

__STATIC_INLINE HW_SPI_MODE	hw_spi_get_config_reg_slave_en (HW_SPI_ID id)
	Get SPI Master/Slave mode from Configuration Register. More...

__STATIC_INLINE bool	hw_spi_get_clock_en (const HW_SPI_ID id)
	Check if the SPI clock is enabled. More...

__STATIC_INLINE void	hw_spi_set_clock_reg (HW_SPI_ID id, uint8_t spi_clock_reg)
	Set SPI Clock Register Value. More...

__STATIC_INLINE uint8_t	hw_spi_get_clock_reg (HW_SPI_ID id)
	Get SPI Clock Register Value. More...

__STATIC_INLINE void	hw_spi_set_clock_reg_clk_div (HW_SPI_ID id, HW_SPI_FREQ spi_clk_div)
	Set SPI_CLK_DIV in Clock Register Applicable only in master mode. Defines the spi clock frequency in master only mode. More...

__STATIC_INLINE HW_SPI_FREQ	hw_spi_get_clock_reg_clk_div (HW_SPI_ID id)
	Get SPI_CLK_DIV from Configuration Register. More...

__STATIC_INLINE void	hw_spi_set_fifo_config_reg (HW_SPI_ID id, uint8_t val)
	Set SPI FIFO Configuration Register Value. More...

__STATIC_INLINE uint32_t	hw_spi_get_fifo_config_reg (HW_SPI_ID id)
	Get SPI FIFO Configuration Register Value. More...

__STATIC_INLINE void	hw_spi_set_fifo_config_reg_tx_tl (HW_SPI_ID id, HW_SPI_FIFO_TL spi_tx_tl)
	Set SPI_TX_TL in FIFO Configuration Register. More...

__STATIC_INLINE HW_SPI_FIFO_TL	hw_spi_get_fifo_config_reg_tx_tl (HW_SPI_ID id)
	Get SPI_TX_TL from FIFO Configuration Register. More...

__STATIC_INLINE void	hw_spi_set_fifo_config_reg_rx_tl (HW_SPI_ID id, HW_SPI_FIFO_TL spi_rx_tl)
	Set SPI_RX_TL in FIFO Configuration Register. More...

__STATIC_INLINE HW_SPI_FIFO_TL	hw_spi_get_fifo_config_reg_rx_tl (HW_SPI_ID id)
	Get SPI_RX_TL from FIFO Configuration Register. More...

__STATIC_INLINE void	hw_spi_set_irq_mask_reg_tx_empty_en (HW_SPI_ID id, HW_SPI_MINT irq_tx_empty_en)
	Set SPI_IRQ_MASK_TX_EMPTY in IRQ Mask Register. More...

__STATIC_INLINE HW_SPI_MINT	hw_spi_get_irq_mask_reg_tx_empty_en (HW_SPI_ID id)
	Get SPI_IRQ_MASK_TX_EMPTY from IRQ Mask Register. More...

__STATIC_INLINE void	hw_spi_set_irq_mask_reg_rx_full_en (HW_SPI_ID id, HW_SPI_MINT irq_rx_full_en)
	Set SPI_IRQ_MASK_RX_FULL in IRQ Mask Register. More...

__STATIC_INLINE HW_SPI_MINT	hw_spi_get_irq_mask_reg_rx_full_en (HW_SPI_ID id)
	Get SPI_IRQ_MASK_RX_FULL from IRQ Mask Register. More...

__STATIC_INLINE bool	hw_spi_get_status_reg_tx_fifo_empty (HW_SPI_ID id)
	Get SPI TX FIFO Empty status from Status Register. More...

__STATIC_INLINE bool	hw_spi_get_status_reg_rx_fifo_full (HW_SPI_ID id)
	Get SPI RX FIFO Full status from Status Register. More...

__STATIC_INLINE uint16_t	hw_spi_get_fifo_status_reg (HW_SPI_ID id)
	Get SPI FIFO status. More...

__STATIC_INLINE bool	hw_spi_get_fifo_status_reg_transaction_active (HW_SPI_ID id)
	Get SPI transaction status from Status Register. More...

__STATIC_INLINE uint8_t	hw_spi_get_fifo_status_reg_tx_fifo_level (HW_SPI_ID id)
	Get SPI TX FIFO level from FIFO Status Register. More...

__STATIC_INLINE bool	hw_spi_get_fifo_status_reg_rx_empty (HW_SPI_ID id)
	Get SPI RX FIFO Empty status from FIFO Status Register. More...

__STATIC_INLINE uint8_t	hw_spi_get_fifo_status_reg_rx_fifo_level (HW_SPI_ID id)
	Get SPI RX FIFO level from FIFO Status Register. More...

__STATIC_INLINE uint8_t	hw_spi_get_fifo_status_reg_rx_fifo_overflow (HW_SPI_ID id)
	Get SPI RX FIFO overflow status from FIFO Status Register. More...

__STATIC_INLINE uint32_t	hw_spi_get_fifo_read_reg (HW_SPI_ID id)
	Read RX FIFO. Read access is permitted only if SPI_RX_FIFO_EMPTY = 0. More...

__STATIC_INLINE void	hw_spi_set_fifo_write_reg (HW_SPI_ID id, uint32_t tx_data)
	Write to TX FIFO. Write access is permitted only if SPI_TX_FIFO_FULL is 0. More...

__STATIC_INLINE void	hw_spi_set_cs_config_reg_mode (HW_SPI_ID id, HW_SPI_CS_MODE cs_mode)
	Set CS output in master mode. More...

__STATIC_INLINE HW_SPI_CS_MODE	hw_spi_get_cs_config_reg_mode (HW_SPI_ID id)
	Get CS output in master mode. More...

__STATIC_INLINE void	hw_spi_set_txbuffer_force_reg (HW_SPI_ID id, uint32_t tx_data)
	Write SPI_TXBUFFER_FORCE_REG Register. More...

__STATIC_INLINE void	hw_spi_enable_interrupt (HW_SPI_ID id)
	Enables the SPI maskable interrupt (MINT) to the CPU. More...

__STATIC_INLINE void	hw_spi_disable_interrupt (HW_SPI_ID id)
	Disables the SPI maskable interrupt (MINT) to the CPU. More...

__STATIC_INLINE HW_SPI_MINT	hw_spi_is_interrupt_enabled (HW_SPI_ID id)
	Get the status of the SPI maskable interrupt (MINT) to the CPU. More...

__STATIC_INLINE void	hw_spi_enable (HW_SPI_ID id, uint8_t on)
	Switch the SPI module on and off. More...

__STATIC_INLINE uint8_t	hw_spi_is_enabled (HW_SPI_ID id)
	Get the on/off status of the SPI module. More...

__STATIC_INLINE void	hw_spi_set_clock_freq (HW_SPI_ID id, HW_SPI_FREQ freq)
	Set SPI source clock's divider for the selected SPI clock frequency. More...

__STATIC_INLINE HW_SPI_FREQ	hw_spi_get_clock_freq (HW_SPI_ID id)
	Get SPI source clock's divider for the selected SPI clock frequency. More...

__STATIC_INLINE void	hw_spi_set_mode (HW_SPI_ID id, HW_SPI_MODE smn)
	Set SPI master/slave mode. More...

__STATIC_INLINE HW_SPI_MODE	hw_spi_is_slave (HW_SPI_ID id)
	Get the SPI master/slave mode. More...

__STATIC_INLINE void	hw_spi_set_word_size (HW_SPI_ID id, HW_SPI_WORD word)
	Set SPI word mode. More...

__STATIC_INLINE HW_SPI_WORD	hw_spi_get_word_size (HW_SPI_ID id)
	Get the SPI word mode. More...

__STATIC_INLINE uint32_t	hw_spi_get_memory_word_size (HW_SPI_ID id)
	Get the SPI word size. More...

__STATIC_INLINE bool	hw_spi_is_tx_fifo_full (HW_SPI_ID id)
	Get the value of the SPI TX FIFO full bit. More...

void	hw_spi_init_clk_reg (const HW_SPI_ID id, bool select_divn)
	Initialize peripheral divider register - select clock source and enable SPI clock. More...

void	hw_spi_deinit_clk_reg (const HW_SPI_ID id)
	De-initialize peripheral divider register - disable SPI clock. More...

void	hw_spi_init (HW_SPI_ID id, const hw_spi_config_t *cfg)
	Initialize the SPI module. More...

void	hw_spi_set_cs_pad (HW_SPI_ID id, const SPI_Pad *pad, HW_SPI_CS_MODE cs_mode, bool validate)
	Set SPI GPIO Chip Select (CS) Pad. More...

void	hw_spi_set_cs_low (HW_SPI_ID id)
	Set SPI CS low. More...

void	hw_spi_set_cs_high (HW_SPI_ID id)
	Set SPI CS high. More...

void	hw_spi_set_fifo_mode (HW_SPI_ID id, HW_SPI_FIFO mode)
	Set SPI FIFO mode. More...

HW_SPI_FIFO	hw_spi_get_fifo_mode (HW_SPI_ID id)
	Get SPI FIFO mode. More...

HW_SPI_FIFO	hw_spi_change_fifo_mode (HW_SPI_ID id, HW_SPI_FIFO mode)
	Change SPI FIFO mode. More...

__STATIC_INLINE uint8_t	hw_spi_is_busy (HW_SPI_ID id)
	Get SPI busy status in master mode. More...

__STATIC_INLINE void	hw_spi_wait_while_busy (HW_SPI_ID id)
	Wait till SPI is not busy. More...

void	hw_spi_deinit (HW_SPI_ID id)
	Disables SPI controller. More...

bool	hw_spi_is_occupied (const HW_SPI_ID id)
	get SPI transaction status More...

Detailed Description

Serial Peripheral Interface (SPI) Controller.

Macro Definition Documentation

◆ HW_SPI1

#define HW_SPI1 ((void *)SPI_BASE)

SPI controller number.

◆ HW_SPI1_USE_FIXED_WORD_SIZE

#define HW_SPI1_USE_FIXED_WORD_SIZE (0)

Use predefined (fixed) word size to optimize performance.

The SPI controller supports multiple word sizes (see HW_SPI_WORD). However, if an application uses devices with the same word size connected to the controller, a predefined word size can be used by defining the HW_SPI1_FIXED_WORD_SIZE macro. This improves LLD performance.

◆ HW_SPI_ASSERT

#define HW_SPI_ASSERT ( id )

Value:

do {                                                                                    \
                ASSERT_WARNING(REG_GETF(CRG_COM, CLK_COM_REG, SPI_ENABLE) == true);         \
        } while (0);

Assertion for SPI control fields.

Certain SPI control fields can be changed only when: CLK_COM_REG[SPI_ENABLE] = 1

Parameters

[in] id SPI controller instance

See also: HW_SPI_ASSERT

◆ HW_SPI_REG_GETF

#define HW_SPI_REG_GETF	(	id,
		reg,
		field
	)	((SBA(id)->reg & (SPI_##reg##_##field##_Msk)) >> (SPI_##reg##_##field##_Pos))

Get the value of an SPI register field.

Parameters

[in]	id	SPI controller instance
[in]	reg	the SPI register
[in]	field	the SPI register field

See also: HW_SPI_REG_SETF

◆ HW_SPI_REG_SET_FIELD

#define HW_SPI_REG_SET_FIELD	(	reg,
		field,
		var,
		val
	)	REG_SET_FIELD(SPI, reg##_REG, field, var, val)

Sets a field value of an SPI register. Aimed to be used with local variables.

Parameters

[in]	reg	the SPI register
[in]	field	the SPI register field
[out]	var	the local variable
[in]	val	the field value

◆ HW_SPI_REG_SETF

#define HW_SPI_REG_SETF	(	id,
		reg,
		field,
		val
	)

Value:

SBA(id)->reg = ((SBA(id)->reg & ~(SPI_##reg##_##field##_Msk)) | \

((SPI_##reg##_##field##_Msk) & ((val) << (SPI_##reg##_##field##_Pos))))

Write a value to an SPI register field.

Parameters

[in]	id	SPI controller instance
[in]	reg	the SPI register
[in]	field	the SPI register field
[in]	val	value to be written

See also: HW_SPI_REG_GETF

Typedef Documentation

◆ HW_SPI_FREQ

typedef uint8_t HW_SPI_FREQ

Source clock's divider for the selected SPI clock frequency.

SPI_CLK = module_clk / 2*(SPI_CLK_DIV+1) when SPI_CLK_DIV not 0x7F If SPI_CLK_DIV=0x7F then SPI_CLK=module_clk

Enumeration Type Documentation

◆ HW_SPI_CS_MODE

enum HW_SPI_CS_MODE

Control the CS output in master mode.

Enumerator
HW_SPI_CS_NONE	None slave device selected
HW_SPI_CS_0	Selected slave device connected to GPIO with FUNC_MODE = SPI_EN
HW_SPI_CS_1	Selected slave device connected to GPIO with FUNC_MODE = SPI_EN2
HW_SPI_CS_GPIO	Selected slave device connected to GPIO with FUNC_MODE = GPIO

◆ HW_SPI_FIFO

enum HW_SPI_FIFO

FIFO mode.

Enumerator
HW_SPI_FIFO_NONE	Backwards compatible mode.
HW_SPI_FIFO_RX_ONLY	Read only mode.
HW_SPI_FIFO_TX_ONLY	Write only mode.
HW_SPI_FIFO_RX_TX	Bidirectional mode.

◆ HW_SPI_FIFO_TL

enum HW_SPI_FIFO_TL

Define the SPI RX/TX FIFO threshold level in bytes.

Valid values are 0 to 4 bytes

Enumerator
HW_SPI_FIFO_LEVEL0	SPI RX/TX FIFO threshold level is 0 bytes
HW_SPI_FIFO_LEVEL1	SPI RX/TX FIFO threshold level is 1 bytes
HW_SPI_FIFO_LEVEL2	SPI RX/TX FIFO threshold level is 2 bytes
HW_SPI_FIFO_LEVEL3	SPI RX/TX FIFO threshold level is 3 bytes
HW_SPI_FIFO_LEVEL4	SPI RX/TX FIFO threshold level is 4 bytes

◆ HW_SPI_MASTER_EDGE_CAPTURE

enum HW_SPI_MASTER_EDGE_CAPTURE

Define the SPI master edge capture type.

Enumerator
HW_SPI_MASTER_EDGE_CAPTURE_CURRENT	SPI master captures data at current clock edge
HW_SPI_MASTER_EDGE_CAPTURE_NEXT	SPI master captures data at next clock edge. (only for high clock configurations)

◆ HW_SPI_MINT

enum HW_SPI_MINT

Disable/enable interrupts to the CPU.

◆ HW_SPI_MODE

enum HW_SPI_MODE

Master/slave mode.

Used to set/get SPI_CONFIG_REG[SPI_SLAVE_EN], where: 0 = SPI module master mode 1 = SPI module slave mode

◆ HW_SPI_MODE_CPOL_CPHA

enum HW_SPI_MODE_CPOL_CPHA

Defines the SPI mode Clock Polarity and Clock Phase (CPOL, CPHA)

Used to set/get SPI_CONFIG_REG[SPI_MODE]

Enumerator
HW_SPI_CP_MODE_0	CPOL=0, CPHA=0: New data on falling, capture on rising, Clk low in idle state
HW_SPI_CP_MODE_1	CPOL=0, CPHA=1: New data on rising, capture on falling, Clk low in idle state
HW_SPI_CP_MODE_2	CPOL=1, CPHA=0: New data on rising, capture on falling, Clk high in idle state
HW_SPI_CP_MODE_3	CPOL=1, CPHA=1: New data on falling, capture on rising, Clk high in idle state

◆ HW_SPI_WORD

enum HW_SPI_WORD

Word length.

Used to set/get SPI_CONFIG_REG[SPI_WORD_LENGTH], 5-bits Define the spi word length = 1 + SPI_WORD_LENGTH (range 4 to 32) Values 3..31 => 4..32-bits

Enumerator
HW_SPI_WORD_4BIT	4 bits mode
HW_SPI_WORD_5BIT	5 bits mode
HW_SPI_WORD_6BIT	6 bits mode
HW_SPI_WORD_7BIT	7 bits mode
HW_SPI_WORD_8BIT	8 bits mode
HW_SPI_WORD_9BIT	9 bits mode
HW_SPI_WORD_10BIT	10 bits mode
HW_SPI_WORD_11BIT	11 bits mode
HW_SPI_WORD_12BIT	12 bits mode
HW_SPI_WORD_13BIT	13 bits mode
HW_SPI_WORD_14BIT	14 bits mode
HW_SPI_WORD_15BIT	15 bits mode
HW_SPI_WORD_16BIT	16 bits mode
HW_SPI_WORD_17BIT	17 bits mode
HW_SPI_WORD_18BIT	18 bits mode
HW_SPI_WORD_19BIT	19 bits mode
HW_SPI_WORD_20BIT	20 bits mode
HW_SPI_WORD_21BIT	21 bits mode
HW_SPI_WORD_22BIT	22 bits mode
HW_SPI_WORD_23BIT	23 bits mode
HW_SPI_WORD_24BIT	24 bits mode
HW_SPI_WORD_25BIT	25 bits mode
HW_SPI_WORD_26BIT	26 bits mode
HW_SPI_WORD_27BIT	27 bits mode
HW_SPI_WORD_28BIT	28 bits mode
HW_SPI_WORD_29BIT	29 bits mode
HW_SPI_WORD_30BIT	30 bits mode
HW_SPI_WORD_31BIT	31 bits mode
HW_SPI_WORD_32BIT	32 bits mode

Function Documentation

◆ hw_spi_change_fifo_mode()

HW_SPI_FIFO hw_spi_change_fifo_mode	(	HW_SPI_ID	id,
		HW_SPI_FIFO	mode
	)

Change SPI FIFO mode.

Unlike hw_spi_set_fifo_mode() it checks current FIFO mode and if mode is going to change waits till all data were sent before changing mode. If mode is same, registers are not touched and no waiting is performed.

Parameters

[in]	id	SPI controller instance
[in]	mode	SPI FIFO mode

Returns: previously selected SPI FIFO mode

See also: hw_spi_set_fifo_mode

◆ hw_spi_deinit()

void hw_spi_deinit ( HW_SPI_ID id )

Disables SPI controller.

Parameters

[in] id SPI controller instance

Returns: status of ongoing async transaction

◆ hw_spi_deinit_clk_reg()

void hw_spi_deinit_clk_reg ( const HW_SPI_ID id )

De-initialize peripheral divider register - disable SPI clock.

Note: Function is executed at hw_spi_deinit. No need to run it when use hw_spi_deinit interface.

Parameters

[in] id SPI controller instance

◆ hw_spi_disable_interrupt()

__STATIC_INLINE void hw_spi_disable_interrupt ( HW_SPI_ID id )

Disables the SPI maskable interrupt (MINT) to the CPU.

Parameters

[in] id SPI controller instance

◆ hw_spi_enable()

__STATIC_INLINE void hw_spi_enable	(	HW_SPI_ID	id,
		uint8_t	on
	)

Switch the SPI module on and off.

Parameters

[in]	id	SPI controller instance
[in]	on	the SPI module switch: 0 = SPI module switch off (power saving). Everything is reset except control registers. 1 = SPI module is in operational mode

◆ hw_spi_enable_interrupt()

__STATIC_INLINE void hw_spi_enable_interrupt ( HW_SPI_ID id )

Enables the SPI maskable interrupt (MINT) to the CPU.

Parameters

[in] id SPI controller instance

◆ hw_spi_fifo_read16()

__STATIC_INLINE uint16_t hw_spi_fifo_read16 ( HW_SPI_ID id )

Read 4 to 16-bits from RX FIFO.

Word size must be setup before to 4 to 16-bits. This function should be called only when FIFO is not empty. Call hw_spi_get_fifo_status_reg_rx_empty() before using this. MSBits are zero if word length is smaller than 16-bits.

Parameters

[in] id SPI controller instance

Returns: read data

See also: hw_spi_get_fifo_status_reg_rx_empty

◆ hw_spi_fifo_read32()

__STATIC_INLINE uint32_t hw_spi_fifo_read32 ( HW_SPI_ID id )

Read 4 to 32-bits from RX FIFO.

Word size must be setup before to 4 to 32-bits. This function should be called only when FIFO is not empty. Call hw_spi_get_fifo_status_reg_rx_empty() before using this. MSBits are zero if word length is smaller than 32-bits.

Parameters

[in] id SPI controller instance

Returns: read data

See also: hw_spi_get_fifo_status_reg_rx_empty

◆ hw_spi_fifo_read8()

__STATIC_INLINE uint8_t hw_spi_fifo_read8 ( HW_SPI_ID id )

Read 4 to 8-bits from RX FIFO.

Word size must be setup before to 4 to 8-bits. This function should be called only when FIFO is not empty. Call hw_spi_get_fifo_status_reg_rx_empty() before using this. MSBits are zero if word length is smaller than 8-bits.

Parameters

[in] id SPI controller instance

Returns: read data

See also: hw_spi_get_fifo_status_reg_rx_empty

◆ hw_spi_fifo_write16()

__STATIC_INLINE void hw_spi_fifo_write16	(	HW_SPI_ID	id,
		uint16_t	data
	)

Write 4 to 16-bits to TX FIFO.

Word size must be setup before to 4 to 16-bits. This function should be called only when FIFO is not full. Call hw_spi_is_tx_fifo_full() before using this. MSBits are ignored if word length is smaller than 16-bits.

Parameters

[in]	id	SPI controller instance
[in]	data	data to be written

See also: hw_spi_is_tx_fifo_full

◆ hw_spi_fifo_write32()

__STATIC_INLINE void hw_spi_fifo_write32	(	HW_SPI_ID	id,
		uint32_t	data
	)

Write 4 to 32-bits to TX FIFO.

Word size must be setup before to 4 to 32-bits. This function should be called only when FIFO is not full. Call hw_spi_is_tx_fifo_full() before using this. MSBits are ignored if word length is smaller than 32-bits.

Parameters

[in]	id	SPI controller instance
[in]	data	data to be written

See also: hw_spi_is_tx_fifo_full

◆ hw_spi_fifo_write8()

__STATIC_INLINE void hw_spi_fifo_write8	(	HW_SPI_ID	id,
		uint8_t	data
	)

Write 4 to 8-bits to TX FIFO.

Word size must be setup before to 4 to 8-bits. This function should be called only when FIFO is not full. Call hw_spi_is_tx_fifo_full() before using this. MSBits are ignored if word length is smaller than 8-bits.

Parameters

[in]	id	SPI controller instance
[in]	data	data to be written

See also: hw_spi_is_tx_fifo_full

◆ hw_spi_get_clock_en()

__STATIC_INLINE bool hw_spi_get_clock_en ( const HW_SPI_ID id )

Check if the SPI clock is enabled.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_clock_freq()

__STATIC_INLINE HW_SPI_FREQ hw_spi_get_clock_freq ( HW_SPI_ID id )

Get SPI source clock's divider for the selected SPI clock frequency.

Note: See hw_spi_get_clock_reg_clk_div

Parameters

[in] id SPI controller instance

Returns: SPI source clock's divider in master mode

◆ hw_spi_get_clock_reg()

__STATIC_INLINE uint8_t hw_spi_get_clock_reg ( HW_SPI_ID id )

Get SPI Clock Register Value.

Parameters

[in] id SPI controller instance

Returns: uint8_t SPI Clock Register Value

◆ hw_spi_get_clock_reg_clk_div()

__STATIC_INLINE HW_SPI_FREQ hw_spi_get_clock_reg_clk_div ( HW_SPI_ID id )

Get SPI_CLK_DIV from Configuration Register.

Parameters

[in] id SPI controller instance

Returns: spi_clk_div

◆ hw_spi_get_config_reg()

__STATIC_INLINE uint32_t hw_spi_get_config_reg ( HW_SPI_ID id )

Get SPI Configuration Register Value.

Parameters

[in] id SPI controller instance

Returns: uint8_t SPI Configuration Register Value

◆ hw_spi_get_config_reg_slave_en()

__STATIC_INLINE HW_SPI_MODE hw_spi_get_config_reg_slave_en ( HW_SPI_ID id )

Get SPI Master/Slave mode from Configuration Register.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_MODE

◆ hw_spi_get_config_reg_spi_mode()

__STATIC_INLINE HW_SPI_MODE_CPOL_CPHA hw_spi_get_config_reg_spi_mode ( HW_SPI_ID id )

Get SPI_MODE from Configuration Register.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_MODE_CPOL_CPHA

◆ hw_spi_get_config_reg_word_len()

__STATIC_INLINE HW_SPI_WORD hw_spi_get_config_reg_word_len ( HW_SPI_ID id )

Get SPI_WORD_LENGTH from Configuration Register.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_WORD SPI Word size - 1 in bits

◆ hw_spi_get_cs_config_reg_mode()

__STATIC_INLINE HW_SPI_CS_MODE hw_spi_get_cs_config_reg_mode ( HW_SPI_ID id )

Get CS output in master mode.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_CS_MODE.

◆ hw_spi_get_ctrl_reg()

__STATIC_INLINE uint32_t hw_spi_get_ctrl_reg ( HW_SPI_ID id )

Get SPI Control Register Value.

Parameters

[in] id SPI controller instance

Returns: SPI Control Register Value

◆ hw_spi_get_ctrl_reg_capture_next_edge()

__STATIC_INLINE HW_SPI_MASTER_EDGE_CAPTURE hw_spi_get_ctrl_reg_capture_next_edge ( HW_SPI_ID id )

Get SPI_CAPTURE_AT_NEXT_EDGE from Control Register.

Parameters

[in] id SPI controller instance

Returns: SPI_MASTER_EDGE_CAPTURE_CFG

◆ hw_spi_get_ctrl_reg_dma_rx_en()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_dma_rx_en ( HW_SPI_ID id )

Get SPI_DMA_RX_EN from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_ctrl_reg_dma_tx_en()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_dma_tx_en ( HW_SPI_ID id )

Get SPI_DMA_TX_EN from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_ctrl_reg_fifo_reset()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_fifo_reset ( HW_SPI_ID id )

Get SPI_FIFO_RESET from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_ctrl_reg_rx_en()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_rx_en ( HW_SPI_ID id )

Get SPI_RX_EN from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_ctrl_reg_spi_en()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_spi_en ( HW_SPI_ID id )

Get SPI_EN from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_ctrl_reg_swap_bytes()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_swap_bytes ( HW_SPI_ID id )

Get SPI_SWAP_BYTES from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_ctrl_reg_tx_en()

__STATIC_INLINE bool hw_spi_get_ctrl_reg_tx_en ( HW_SPI_ID id )

Get SPI_TX_EN from Control Register.

Parameters

[in] id SPI controller instance

Returns: false: Disabled, true: Enabled

◆ hw_spi_get_fifo_config_reg()

__STATIC_INLINE uint32_t hw_spi_get_fifo_config_reg ( HW_SPI_ID id )

Get SPI FIFO Configuration Register Value.

Parameters

[in] id SPI controller instance

Returns: SPI FIFO Config Register Value

◆ hw_spi_get_fifo_config_reg_rx_tl()

__STATIC_INLINE HW_SPI_FIFO_TL hw_spi_get_fifo_config_reg_rx_tl ( HW_SPI_ID id )

Get SPI_RX_TL from FIFO Configuration Register.

Parameters

[in] id SPI controller instance

Returns: spi_rx_tl

◆ hw_spi_get_fifo_config_reg_tx_tl()

__STATIC_INLINE HW_SPI_FIFO_TL hw_spi_get_fifo_config_reg_tx_tl ( HW_SPI_ID id )

Get SPI_TX_TL from FIFO Configuration Register.

Parameters

[in] id SPI controller instance

Returns: spi_tx_tl

◆ hw_spi_get_fifo_depth_in_bytes()

__STATIC_INLINE HW_SPI_FIFO_TL hw_spi_get_fifo_depth_in_bytes ( const HW_SPI_ID id )

Get SPI fifo depth in bytes.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_FIFO_TL

◆ hw_spi_get_fifo_mode()

HW_SPI_FIFO hw_spi_get_fifo_mode ( HW_SPI_ID id )

Get SPI FIFO mode.

Parameters

[in] id SPI controller instance

Returns: currently selected SPI FIFO mode

◆ hw_spi_get_fifo_read_reg()

__STATIC_INLINE uint32_t hw_spi_get_fifo_read_reg ( HW_SPI_ID id )

Read RX FIFO. Read access is permitted only if SPI_RX_FIFO_EMPTY = 0.

Parameters

[in] id SPI controller instance

Returns: 16 LSbits of RX FIFO.

◆ hw_spi_get_fifo_status_reg()

__STATIC_INLINE uint16_t hw_spi_get_fifo_status_reg ( HW_SPI_ID id )

Get SPI FIFO status.

Parameters

[in] id SPI controller instance

Returns: SPI FIFO STATUS.

◆ hw_spi_get_fifo_status_reg_rx_empty()

__STATIC_INLINE bool hw_spi_get_fifo_status_reg_rx_empty ( HW_SPI_ID id )

Get SPI RX FIFO Empty status from FIFO Status Register.

Parameters

[in] id SPI controller instance

Returns: SPI RX FIFO empty bit: 0 = RX FIFO is not empty, data can be read, 1 = RX FIFO is empty, data cannot be read

◆ hw_spi_get_fifo_status_reg_rx_fifo_level()

__STATIC_INLINE uint8_t hw_spi_get_fifo_status_reg_rx_fifo_level ( HW_SPI_ID id )

Get SPI RX FIFO level from FIFO Status Register.

Parameters

[in] id SPI controller instance

Returns: Number of bytes in RX FIFO.

◆ hw_spi_get_fifo_status_reg_rx_fifo_overflow()

__STATIC_INLINE uint8_t hw_spi_get_fifo_status_reg_rx_fifo_overflow ( HW_SPI_ID id )

Get SPI RX FIFO overflow status from FIFO Status Register.

Parameters

[in] id SPI controller instance

Returns: 0 = no overflow. 1 = receive data is not written to FIFO because FIFO was full. It clears with SPI_CTRL_REG.SPI_FIFO_RESET.

◆ hw_spi_get_fifo_status_reg_transaction_active()

__STATIC_INLINE bool hw_spi_get_fifo_status_reg_transaction_active ( HW_SPI_ID id )

Get SPI transaction status from Status Register.

Parameters

[in] id SPI controller instance

Returns: bool.

◆ hw_spi_get_fifo_status_reg_tx_fifo_level()

__STATIC_INLINE uint8_t hw_spi_get_fifo_status_reg_tx_fifo_level ( HW_SPI_ID id )

Get SPI TX FIFO level from FIFO Status Register.

Parameters

[in] id SPI controller instance

Returns: Number of bytes in TX FIFO.

◆ hw_spi_get_irq_mask_reg_rx_full_en()

__STATIC_INLINE HW_SPI_MINT hw_spi_get_irq_mask_reg_rx_full_en ( HW_SPI_ID id )

Get SPI_IRQ_MASK_RX_FULL from IRQ Mask Register.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_MINT.

◆ hw_spi_get_irq_mask_reg_tx_empty_en()

__STATIC_INLINE HW_SPI_MINT hw_spi_get_irq_mask_reg_tx_empty_en ( HW_SPI_ID id )

Get SPI_IRQ_MASK_TX_EMPTY from IRQ Mask Register.

Parameters

[in] id SPI controller instance

Returns: HW_SPI_MINT.

◆ hw_spi_get_memory_word_size()

__STATIC_INLINE uint32_t hw_spi_get_memory_word_size ( HW_SPI_ID id )

Get the SPI word size.

Returns number of bytes that will be read/written to/from memory.

Parameters

[in] id SPI controller instance

Returns: SPI word mode

◆ hw_spi_get_status_reg_rx_fifo_full()

__STATIC_INLINE bool hw_spi_get_status_reg_rx_fifo_full ( HW_SPI_ID id )

Get SPI RX FIFO Full status from Status Register.

Parameters

[in] id SPI controller instance

Returns: bool.

◆ hw_spi_get_status_reg_tx_fifo_empty()

__STATIC_INLINE bool hw_spi_get_status_reg_tx_fifo_empty ( HW_SPI_ID id )

Get SPI TX FIFO Empty status from Status Register.

Parameters

[in] id SPI controller instance

Returns: bool.

◆ hw_spi_get_word_size()

__STATIC_INLINE HW_SPI_WORD hw_spi_get_word_size ( HW_SPI_ID id )

Get the SPI word mode.

Parameters

[in] id SPI controller instance

Returns: SPI word mode

◆ hw_spi_init()

void hw_spi_init	(	HW_SPI_ID	id,
		const hw_spi_config_t *	cfg
	)

Initialize the SPI module.

Note: The SPI clock source is set to DIVN (16MHz, regardless of PLL or XTAL16M being used).

Parameters

[in]	id	SPI controller instance
[in]	cfg	pointer to SPI configuration struct

◆ hw_spi_init_clk_reg()

void hw_spi_init_clk_reg	(	const HW_SPI_ID	id,
		bool	select_divn
	)

Initialize peripheral divider register - select clock source and enable SPI clock.

Note: Function is executed at hw_spi_init. No need to run it when use hw_spi_init interface.

Parameters

[in]	id	SPI controller instance
[in]	select_divn	True = Select DIVN clock source False = Select DIV1 clock source

◆ hw_spi_is_busy()

__STATIC_INLINE uint8_t hw_spi_is_busy ( HW_SPI_ID id )

Get SPI busy status in master mode.

Parameters

[in] id SPI controller instance

Returns: status of SPI_TRANSACTION_ACTIVE bit: 0 = SPI transaction inactive 1 = SPI transaction active

◆ hw_spi_is_enabled()

__STATIC_INLINE uint8_t hw_spi_is_enabled ( HW_SPI_ID id )

Get the on/off status of the SPI module.

Parameters

[in] id SPI controller instance

Returns: the status of the SPI ON bit: 0 = SPI module switched off, 1 = SPI module switched on

◆ hw_spi_is_interrupt_enabled()

__STATIC_INLINE HW_SPI_MINT hw_spi_is_interrupt_enabled ( HW_SPI_ID id )

Get the status of the SPI maskable interrupt (MINT) to the CPU.

Parameters

[in] id SPI controller instance

Returns: SPI maskable interrupt (MINT) status

◆ hw_spi_is_occupied()

bool hw_spi_is_occupied ( const HW_SPI_ID id )

get SPI transaction status

Parameters

[in] id SPI controller instance

Returns: status of ongoing async transaction

◆ hw_spi_is_slave()

__STATIC_INLINE HW_SPI_MODE hw_spi_is_slave ( HW_SPI_ID id )

Get the SPI master/slave mode.

Parameters

[in] id SPI controller instance

Returns: SPI master/slave mode

◆ hw_spi_is_tx_fifo_full()

__STATIC_INLINE bool hw_spi_is_tx_fifo_full ( HW_SPI_ID id )

Get the value of the SPI TX FIFO full bit.

Parameters

[in] id SPI controller instance

Returns: SPI TX FIFO full bit: false = TX FIFO is not full, data can be written, true = TX FIFO is full, data cannot be written

◆ hw_spi_read_buf()

void hw_spi_read_buf	(	HW_SPI_ID	id,
		uint8_t *	in_buf,
		uint16_t	len,
		hw_spi_tx_callback	cb,
		void *	user_data
	)

Reads array of bytes through SPI.

Initiates SPI read transfer. If no callback is provided this function wait for transfer to finish. If callback is provided function sets up transfer in interrupt or dma mode and ends immediately. In this case data pointed by in_buf and out_buf should not be touched till callback is called.

Note: In master mode, the TX path is enabled as well as the RX path. The master has to write dummy data, thus giving a clock to slave and read data from slave.; In master interrupt mode, the SPI_STATUS_TX_EMPTY event triggers the SPI handler for the first time only, and the TX FIFO is written (dummy writes) until it is full. The SPI_STATUS_TX_EMPTY event is disabled and thus the TX_TL is used for the first time only. The SPI_STATUS_RX_FULL event triggers the handler from now on according to RX_TL, where the master starts reading the RX_FIFO until it is empty and writing TX_FIFO until full. This is repeated until len bytes are read into in_buf.; In slave interrupt mode, the SPI_STATUS_RX_FULL event triggers the SPI handler, according to the RX_TL, where the slave starts reading the RX_FIFO until it is empty. This is repeated until len bytes are read into in_buf.

Parameters

[in]	id	SPI controller instance
[out]	in_buf	buffer for incoming data
[in]	len	data length in bytes
[in]	cb	callback to call after transfer is finished
[in]	user_data	parameter for callback

Note: Supplied buffer address and length must be SPI-word-aligned.

◆ hw_spi_set_clock_freq()

__STATIC_INLINE void hw_spi_set_clock_freq	(	HW_SPI_ID	id,
		HW_SPI_FREQ	freq
	)

Set SPI source clock's divider for the selected SPI clock frequency.

Note: See hw_spi_set_clock_reg_clk_div

Parameters

[in]	id	SPI controller instance
[in]	freq	selected SPI source clock's divider in master mode

◆ hw_spi_set_clock_reg()

__STATIC_INLINE void hw_spi_set_clock_reg	(	HW_SPI_ID	id,
		uint8_t	spi_clock_reg
	)

Set SPI Clock Register Value.

Parameters

[in]	id	SPI controller instance
[in]	spi_clock_reg	SPI Clock Register Value

◆ hw_spi_set_clock_reg_clk_div()

__STATIC_INLINE void hw_spi_set_clock_reg_clk_div	(	HW_SPI_ID	id,
		HW_SPI_FREQ	spi_clk_div
	)

Set SPI_CLK_DIV in Clock Register Applicable only in master mode. Defines the spi clock frequency in master only mode.

Parameters

[in]	id	SPI controller instance
[in]	spi_clk_div	SPI_CLK = module_clk / 2 * (SPI_CLK_DIV + 1) when SPI_CLK_DIV is not 0x7F. If SPI_CLK_DIV = 0x7F then SPI_CLK = module_clk

◆ hw_spi_set_config_reg()

__STATIC_INLINE void hw_spi_set_config_reg	(	HW_SPI_ID	id,
		uint32_t	spi_config_reg
	)

Set SPI Configuration Register Value.

Parameters

[in]	id	SPI controller instance
[in]	spi_config_reg	SPI Configuration Register Value

◆ hw_spi_set_config_reg_slave_en()

__STATIC_INLINE void hw_spi_set_config_reg_slave_en	(	HW_SPI_ID	id,
		HW_SPI_MODE	spi_ms
	)

Set SPI_SLAVE_EN in Configuration Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_ms

◆ hw_spi_set_config_reg_spi_mode()

__STATIC_INLINE void hw_spi_set_config_reg_spi_mode	(	HW_SPI_ID	id,
		HW_SPI_MODE_CPOL_CPHA	spi_cp
	)

Set SPI_MODE in Configuration Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_cp	HW_SPI_MODE_CPOL_CPHA

◆ hw_spi_set_config_reg_word_len()

__STATIC_INLINE void hw_spi_set_config_reg_word_len	(	HW_SPI_ID	id,
		HW_SPI_WORD	spi_wsz
	)

Set SPI_WORD_LENGTH in Configuration Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_wsz	SPI Word size - 1 in bits

◆ hw_spi_set_cs_config_reg_mode()

__STATIC_INLINE void hw_spi_set_cs_config_reg_mode	(	HW_SPI_ID	id,
		HW_SPI_CS_MODE	cs_mode
	)

Set CS output in master mode.

Parameters

[in]	id	SPI controller instance
[in]	cs_mode	CS output in master mode.

◆ hw_spi_set_cs_high()

void hw_spi_set_cs_high ( HW_SPI_ID id )

Set SPI CS high.

Parameters

[in] id SPI controller instance

See also: hw_spi_set_cs_pad, hw_spi_set_cs_config_reg_mode

◆ hw_spi_set_cs_low()

void hw_spi_set_cs_low ( HW_SPI_ID id )

Set SPI CS low.

Parameters

[in] id SPI controller instance

See also: hw_spi_set_cs_pad, hw_spi_set_cs_config_reg_mode

◆ hw_spi_set_cs_pad()

void hw_spi_set_cs_pad	(	HW_SPI_ID	id,
		const SPI_Pad *	pad,
		HW_SPI_CS_MODE	cs_mode,
		bool	validate
	)

Set SPI GPIO Chip Select (CS) Pad.

Parameters

[in]	id	SPI controller instance
[in]	pad	struct SPI_Pad with CS port and pin selection
[in]	cs_mode	CS mode
[in]	validate	CS consistency checks applicable if true

◆ hw_spi_set_ctrl_reg()

__STATIC_INLINE void hw_spi_set_ctrl_reg	(	HW_SPI_ID	id,
		uint32_t	val
	)

Set SPI Control Register Value.

Parameters

[in]	id	SPI controller instance
[in]	val	SPI Control Register Value

◆ hw_spi_set_ctrl_reg_capture_next_edge()

__STATIC_INLINE void hw_spi_set_ctrl_reg_capture_next_edge	(	HW_SPI_ID	id,
		HW_SPI_MASTER_EDGE_CAPTURE	capture_next_edge
	)

Set SPI_CAPTURE_AT_NEXT_EDGE in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	capture_next_edge

◆ hw_spi_set_ctrl_reg_clear_enable()

__STATIC_INLINE void hw_spi_set_ctrl_reg_clear_enable ( HW_SPI_ID id )

Set SPI Control Register Value to clear SPI enable.

Parameters

[in] id SPI controller instance

◆ hw_spi_set_ctrl_reg_dma_rx_en()

__STATIC_INLINE void hw_spi_set_ctrl_reg_dma_rx_en	(	HW_SPI_ID	id,
		bool	spi_dma_rx_enable
	)

Set SPI_DMA_RX_EN in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_dma_rx_enable	false: Disable, true: Enable

◆ hw_spi_set_ctrl_reg_dma_tx_en()

__STATIC_INLINE void hw_spi_set_ctrl_reg_dma_tx_en	(	HW_SPI_ID	id,
		bool	spi_dma_tx_enable
	)

Set SPI_DMA_TX_EN in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_dma_tx_enable	false: Disable, true: Enable

◆ hw_spi_set_ctrl_reg_fifo_reset()

__STATIC_INLINE void hw_spi_set_ctrl_reg_fifo_reset	(	HW_SPI_ID	id,
		bool	spi_fifo_reset
	)

Set SPI_FIFO_RESET in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_fifo_reset	false: Disable, true: Enable

◆ hw_spi_set_ctrl_reg_rx_en()

__STATIC_INLINE void hw_spi_set_ctrl_reg_rx_en	(	HW_SPI_ID	id,
		bool	spi_rx_enable
	)

Set SPI_RX_EN in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_rx_enable	false: Disable, true: Enable

◆ hw_spi_set_ctrl_reg_spi_en()

__STATIC_INLINE void hw_spi_set_ctrl_reg_spi_en	(	HW_SPI_ID	id,
		bool	spi_enable
	)

Set SPI_EN in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_enable	false: Disable, true: Enable

◆ hw_spi_set_ctrl_reg_swap_bytes()

__STATIC_INLINE void hw_spi_set_ctrl_reg_swap_bytes	(	HW_SPI_ID	id,
		bool	swap_bytes
	)

Set SPI_SWAP_BYTES in Control Register.

In case of 8bit interface, SPI can be configured to change word endianness to off load the bus. It applies to 16-bit or 32-bit words. No use in case of 8-bit words.

Note: The name "SPI_SWAP_BYTES" comes from the former implementation of the SPI block which supported 16-bit words only.

Parameters

[in]	id	SPI controller instance
[in]	swap_bytes	false: normal operation true: change endianness in APB interface

◆ hw_spi_set_ctrl_reg_tx_en()

__STATIC_INLINE void hw_spi_set_ctrl_reg_tx_en	(	HW_SPI_ID	id,
		bool	spi_tx_enable
	)

Set SPI_TX_EN in Control Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_tx_enable	false: Disable, true: Enable

◆ hw_spi_set_fifo_config_reg()

__STATIC_INLINE void hw_spi_set_fifo_config_reg	(	HW_SPI_ID	id,
		uint8_t	val
	)

Set SPI FIFO Configuration Register Value.

Parameters

[in]	id	SPI controller instance
[in]	val	SPI FIFO Config Register Value

◆ hw_spi_set_fifo_config_reg_rx_tl()

__STATIC_INLINE void hw_spi_set_fifo_config_reg_rx_tl	(	HW_SPI_ID	id,
		HW_SPI_FIFO_TL	spi_rx_tl
	)

Set SPI_RX_TL in FIFO Configuration Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_rx_tl	Receive FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the RX_FULL interrupt. IRQ is occurred when fifo level is less or equal to spi_rx_tl + 1.

◆ hw_spi_set_fifo_config_reg_tx_tl()

__STATIC_INLINE void hw_spi_set_fifo_config_reg_tx_tl	(	HW_SPI_ID	id,
		HW_SPI_FIFO_TL	spi_tx_tl
	)

Set SPI_TX_TL in FIFO Configuration Register.

Parameters

[in]	id	SPI controller instance
[in]	spi_tx_tl	Transmit FIFO threshold level in bytes. Control the level of bytes in fifo that triggers the TX_EMPTY interrupt. IRQ is occurred when fifo level is less or equal to spi_tx_tl.

◆ hw_spi_set_fifo_mode()

void hw_spi_set_fifo_mode	(	HW_SPI_ID	id,
		HW_SPI_FIFO	mode
	)

Set SPI FIFO mode.

Parameters

[in]	id	SPI controller instance
[in]	mode	SPI FIFO mode

◆ hw_spi_set_fifo_write_reg()

__STATIC_INLINE void hw_spi_set_fifo_write_reg	(	HW_SPI_ID	id,
		uint32_t	tx_data
	)

Write to TX FIFO. Write access is permitted only if SPI_TX_FIFO_FULL is 0.

Parameters

[in]	id	SPI controller instance
[in]	tx_data	32 bits.

◆ hw_spi_set_irq_mask_reg_rx_full_en()

__STATIC_INLINE void hw_spi_set_irq_mask_reg_rx_full_en	(	HW_SPI_ID	id,
		HW_SPI_MINT	irq_rx_full_en
	)

Set SPI_IRQ_MASK_RX_FULL in IRQ Mask Register.

Parameters

[in]	id	SPI controller instance
[in]	irq_rx_full_en	HW_SPI_MINT.

◆ hw_spi_set_irq_mask_reg_tx_empty_en()

__STATIC_INLINE void hw_spi_set_irq_mask_reg_tx_empty_en	(	HW_SPI_ID	id,
		HW_SPI_MINT	irq_tx_empty_en
	)

Set SPI_IRQ_MASK_TX_EMPTY in IRQ Mask Register.

Parameters

[in]	id	SPI controller instance
[in]	irq_tx_empty_en	HW_SPI_MINT.

◆ hw_spi_set_mode()

__STATIC_INLINE void hw_spi_set_mode	(	HW_SPI_ID	id,
		HW_SPI_MODE	smn
	)

Set SPI master/slave mode.

Note: Configure SPI_CONFIG_REG[SPI_SLAVE_EN] field before SPI enable (SPI_CTRL_REG[SPI_EN] = 1)

Parameters

[in]	id	SPI controller instance
[in]	smn	SPI mode - master/slave

◆ hw_spi_set_txbuffer_force_reg()

__STATIC_INLINE void hw_spi_set_txbuffer_force_reg	(	HW_SPI_ID	id,
		uint32_t	tx_data
	)

Write SPI_TXBUFFER_FORCE_REG Register.

Parameters

[in]	id	SPI controller instance
[in]	tx_data	Write directly the tx buffer. It must be used only in slave mode.

Note: First write SPI_TXBUFFER_FORCE_REG and then enable chip select (low). This is mandatory at spi modes 0 and 2.

◆ hw_spi_set_word_size()

__STATIC_INLINE void hw_spi_set_word_size	(	HW_SPI_ID	id,
		HW_SPI_WORD	word
	)

Set SPI word mode.

Parameters

[in]	id	SPI controller instance
[in]	word	word length

◆ hw_spi_wait_while_busy()

__STATIC_INLINE void hw_spi_wait_while_busy ( HW_SPI_ID id )

Wait till SPI is not busy.

Parameters

[in] id SPI controller instance

Note: This function should be called only by SPI master.

◆ hw_spi_write_buf()

void hw_spi_write_buf	(	HW_SPI_ID	id,
		const uint8_t *	out_buf,
		uint16_t	len,
		hw_spi_tx_callback	cb,
		void *	user_data
	)

Write array of bytes to SPI.

Initiates SPI transmission, no data is received (Write only mode) If no callback is provided this function wait for transfer to finish. If callback is provided function sets up transfer and ends immediately. In this case data pointed by out_buf should not be touched till callback is called.

Parameters

[in]	id	SPI controller instance
[in]	out_buf	data to send
[in]	len	data length in bytes
[in]	cb	callback to call after transfer is finished
[in]	user_data	parameter for callback

Note: In slave mode, the first word to be transmitted should be written to the TX buffer and the remaining words are written to the TX FIFO.

The mechanism that fetches data into the TX fifo and from TX fifo to TX buffer is as follows:

DMA mode: When data is to be transmitted in Slave mode using DMA, the first word is written to SPI_TXBUFFER_FORCE_REG and the DMA is programmed to send the remaining words. When the number of bytes in the TX fifo is less or equal to the TX threshold level set by the user (SPI_TX_TL), an SPI_STATUS_TX_EMPTY event triggers the DMA to fetch new data into the TX FIFO. When the last byte is added in the TX fifo, the dma has finished, the TX dma callback is called and ad_spi_write() returns. This means that for the TX Path, there is no signal notifying about the actual transmission of the last byte on the bus.

Interrupt mode: When the number of bytes in the TX fifo is less or equal to the TX threshold level set by the user (SPI_TX_TL), an SPI_STATUS_TX_EMPTY event triggers the spi interrupt handler, which adds new data in the TX fifo. The user callback is called when the last byte is added in the TX fifo.

In the special case where only one word needs to be sent, DMA cannot not be enabled to send zero words, although DMA may have been requested by the user during driver initialization. Instead, interrupt mode will be enabled for receiving an asynchronous notification and eventually call the user callback as required by the driver API.

In the special case where two words needs to be sent, DMA will be enabled. The first word is written to SPI_TXBUFFER_FORCE_REG and the DMA is programmed to send the remaining word. The first time, the TX fifo is always empty i.e. it always has less or equal bytes to the TX threshold level set by the user (SPI_TX_TL). Therefore, an SPI_STATUS_TX_EMPTY event triggers the DMA to fetch a new word into the TX FIFO. When the last and only one word is added in the TX fifo, the dma has finished and the TX dma callback is called.

Note: Supplied buffer address and length must be non-zero and SPI-word-aligned.

◆ hw_spi_writeread()

uint16_t hw_spi_writeread	(	HW_SPI_ID	id,
		uint16_t	val
	)

Writes/reads 4 to 16 bits to the SPI.

Function sends word to SPI and reads back data on same clock. Word size must be setup before to 4 to 16-bits. Data is sent in big-endian mode, MSB goes first. MSBits are ignored if word length is smaller than 16-bits.

Note: Use hw_spi_set_txbuffer_force_reg first, when device is slave

Parameters

[in]	id	SPI controller interface
[in]	val	value to send

Returns: value read from MISO line

See also: hw_spi_writeread32, hw_spi_set_txbuffer_force_reg

◆ hw_spi_writeread32()

uint32_t hw_spi_writeread32	(	HW_SPI_ID	id,
		uint32_t	val
	)

Writes/reads 4 to 32 bits to the SPI.

Function sends word to SPI and reads back data on same clock. Word size must be setup before to 4 to 32-bits. Data is sent in big-endian mode, MSB goes first. MSBits are ignored if word length is smaller than 32-bits.

Note: Use hw_spi_set_txbuffer_force_reg first, when device is slave

Parameters

[in]	id	SPI controller interface
[in]	val	value to send

Returns: value read from MISO line

See also: hw_spi_writeread, hw_spi_set_txbuffer_force_reg

◆ hw_spi_writeread_buf()

void hw_spi_writeread_buf	(	HW_SPI_ID	id,
		const uint8_t *	out_buf,
		uint8_t *	in_buf,
		uint16_t	len,
		hw_spi_tx_callback	cb,
		void *	user_data
	)

Write and reads array of bytes through SPI.

Initiates SPI transmission, data is sent and received at the same time. If no callback is provided this function wait for transfer to finish. If callback is provided function sets up transfer in interrupt or dma mode and ends immediately. In this case data pointed by in_buf and out_buf should not be touched till callback is called.

Note: In interrupt mode, the SPI_STATUS_TX_EMPTY event triggers the SPI handler for the first time only, and the TX FIFO is written until it is full. The SPI_STATUS_TX_EMPTY event is disabled and thus the TX_TL is used for the first time only. The SPI_STATUS_RX_FULL event triggers the handler from now on according to RX_TL, where the master/slave starts reading the RX_FIFO until it is empty and writing TX_FIFO until full. This is repeated until len bytes are read into in_buf.

Parameters

[in]	id	SPI controller instance
[in]	out_buf	data to send
[out]	in_buf	buffer for incoming data
[in]	len	data length in bytes
[in]	cb	callback to call after transfer is finished
[in]	user_data	parameter for callback

Note: Supplied buffer addresses and lengths must be SPI-word-aligned.

Files

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ HW_SPI1

◆ HW_SPI1_USE_FIXED_WORD_SIZE

◆ HW_SPI_ASSERT

◆ HW_SPI_REG_GETF

◆ HW_SPI_REG_SET_FIELD

◆ HW_SPI_REG_SETF

Typedef Documentation

◆ HW_SPI_FREQ

Enumeration Type Documentation

◆ HW_SPI_CS_MODE

◆ HW_SPI_FIFO

◆ HW_SPI_FIFO_TL

◆ HW_SPI_MASTER_EDGE_CAPTURE

◆ HW_SPI_MINT

◆ HW_SPI_MODE

◆ HW_SPI_MODE_CPOL_CPHA

◆ HW_SPI_WORD

Function Documentation

◆ hw_spi_change_fifo_mode()

◆ hw_spi_deinit()

◆ hw_spi_deinit_clk_reg()

◆ hw_spi_disable_interrupt()

◆ hw_spi_enable()

◆ hw_spi_enable_interrupt()

◆ hw_spi_fifo_read16()

◆ hw_spi_fifo_read32()

◆ hw_spi_fifo_read8()

◆ hw_spi_fifo_write16()

◆ hw_spi_fifo_write32()

◆ hw_spi_fifo_write8()

◆ hw_spi_get_clock_en()

◆ hw_spi_get_clock_freq()

◆ hw_spi_get_clock_reg()

◆ hw_spi_get_clock_reg_clk_div()

◆ hw_spi_get_config_reg()

◆ hw_spi_get_config_reg_slave_en()

◆ hw_spi_get_config_reg_spi_mode()

◆ hw_spi_get_config_reg_word_len()

◆ hw_spi_get_cs_config_reg_mode()

◆ hw_spi_get_ctrl_reg()

◆ hw_spi_get_ctrl_reg_capture_next_edge()

◆ hw_spi_get_ctrl_reg_dma_rx_en()

◆ hw_spi_get_ctrl_reg_dma_tx_en()

◆ hw_spi_get_ctrl_reg_fifo_reset()

◆ hw_spi_get_ctrl_reg_rx_en()

◆ hw_spi_get_ctrl_reg_spi_en()

◆ hw_spi_get_ctrl_reg_swap_bytes()

◆ hw_spi_get_ctrl_reg_tx_en()

◆ hw_spi_get_fifo_config_reg()

◆ hw_spi_get_fifo_config_reg_rx_tl()

◆ hw_spi_get_fifo_config_reg_tx_tl()

◆ hw_spi_get_fifo_depth_in_bytes()

◆ hw_spi_get_fifo_mode()

◆ hw_spi_get_fifo_read_reg()

◆ hw_spi_get_fifo_status_reg()

◆ hw_spi_get_fifo_status_reg_rx_empty()

◆ hw_spi_get_fifo_status_reg_rx_fifo_level()

◆ hw_spi_get_fifo_status_reg_rx_fifo_overflow()

◆ hw_spi_get_fifo_status_reg_transaction_active()

◆ hw_spi_get_fifo_status_reg_tx_fifo_level()

◆ hw_spi_get_irq_mask_reg_rx_full_en()

◆ hw_spi_get_irq_mask_reg_tx_empty_en()

◆ hw_spi_get_memory_word_size()

◆ hw_spi_get_status_reg_rx_fifo_full()

◆ hw_spi_get_status_reg_tx_fifo_empty()

◆ hw_spi_get_word_size()

◆ hw_spi_init()

◆ hw_spi_init_clk_reg()

◆ hw_spi_is_busy()

◆ hw_spi_is_enabled()

◆ hw_spi_is_interrupt_enabled()

◆ hw_spi_is_occupied()