hw_pcm.h

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#ifndef HW_PCM_H_
#define HW_PCM_H_
 
#if dg_configUSE_HW_PCM
 
#include "sdk_defs.h"
 
#define HW_PCM_CRG_REG_GETF(reg, field)         REG_GETF(CRG_AUD, PCM_##reg##_REG, field)
 
#define HW_PCM_CRG_REG_SETF(reg, field, val)    REG_SETF(CRG_AUD, PCM_##reg##_REG, field, val)
 
#define HW_PCM_CRG_REG_SET_BIT(reg, field)      REG_SET_BIT(CRG_AUD, PCM_##reg##_REG, field)
 
#define HW_PCM_CRG_REG_CLR_BIT(reg, field)      REG_CLR_BIT(CRG_AUD, PCM_##reg##_REG, field)
 
#define HW_PCM_SRC_REG_GETF(reg, field)         REG_GETF(PCM1, PCM1_##reg##_REG, field)
 
#define HW_PCM_SRC_REG_SETF(reg, field, val)    REG_SETF(PCM1, PCM1_##reg##_REG, field, val)
 
#define HW_PCM_SRC_REG_SET_BIT(reg, field)      REG_SET_BIT(PCM1, PCM1_##reg##_REG, field)
 
#define HW_PCM_SRC_REG_CLR_BIT(reg, field)      REG_CLR_BIT(PCM1, PCM1_##reg##_REG, field)
 
typedef enum {
        HW_PCM_ERROR_NO_ERROR,               
        HW_PCM_ERROR_INVALID_SAMPLE_RATE,    
        HW_PCM_ERROR_INVALID_BIT_DEPTH,      
        HW_PCM_ERROR_INVALID_CHANNELS,       
        HW_PCM_ERROR_INVALID_CHANNEL_DELAYS, 
        HW_PCM_ERROR_INVALID_SLOTS,          
        HW_PCM_ERROR_INVALID_FSC_DIV,        
        HW_PCM_ERROR_NA_DIV,                 
}HW_PCM_ERROR_CODE;
 
typedef enum {
        HW_PCM_MODE_SLAVE,                   
        HW_PCM_MODE_MASTER,                  
} HW_PCM_MODE;
 
typedef enum {
        HW_PCM_CLK_DIVN,                      
        HW_PCM_CLK_DIV1,                      
} HW_PCM_CLOCK;
 
typedef enum {
        HW_PCM_CLK_GEN_FRACTIONAL = 0,   
        HW_PCM_CLK_GEN_INTEGER_ONLY,     
} HW_PCM_CLK_GENERATION;
 
typedef enum {
        HW_PCM_ONE_CYCLE_PER_BIT = 0,   
        HW_PCM_TWO_CYCLE_PER_BIT,       
} HW_PCM_CYCLE_PER_BIT;
 
typedef enum {
        HW_PCM_DO_OUTPUT_PUSH_PULL = 0,    
        HW_PCM_DO_OUTPUT_OPEN_DRAIN,       
} HW_PCM_DO_OUTPUT_MODE;
 
typedef enum {
        HW_PCM_FSC_EDGE_RISING = 0,             
        HW_PCM_FSC_EDGE_RISING_AND_FALLING,     
} HW_PCM_FSC_EDGE;
 
typedef enum {
        HW_PCM_FSC_STARTS_1_CYCLE_BEFORE_MSB_BIT = 0,   
        HW_PCM_FSC_STARTS_SYNCH_TO_MSB_BIT,             
} HW_PCM_FSC_DELAY;
 
typedef enum {
        HW_PCM_INPUT_REG_1,    
        HW_PCM_INPUT_REG_2,    
} HW_PCM_INPUT;
 
typedef enum {
        HW_PCM_OUTPUT_REG_1,  
        HW_PCM_OUTPUT_REG_2,  
} HW_PCM_OUTPUT;
 
typedef enum {
        HW_PCM_INPUT_MUX_OFF,                                     
        HW_PCM_INPUT_MUX_SRC1_OUT,                                
        HW_PCM_INPUT_MUX_SRC_OUT = HW_PCM_INPUT_MUX_SRC1_OUT,     
        HW_PCM_INPUT_MUX_PCM_OUT_REG,                             
        HW_PCM_INPUT_MUX_SRC2_OUT,                               
        HW_PCM_INPUT_MUX_SIZE
} HW_PCM_INPUT_MUX;
 
typedef enum {
        HW_PCM_CLK_POLARITY_NORMAL = 0,    
        HW_PCM_CLK_POLARITY_INVERTED,      
} HW_PCM_CLK_POLARITY;
 
typedef enum {
        HW_PCM_FSC_POLARITY_NORMAL = 0,    
        HW_PCM_FSC_POLARITY_INVERTED,      
} HW_PCM_FSC_POLARITY;
 
typedef struct {
        HW_PCM_CYCLE_PER_BIT cycle_per_bit;   
        uint8_t channel_delay;                
        HW_PCM_CLK_POLARITY clock_polarity;   
        HW_PCM_FSC_POLARITY fsc_polarity;     
        uint16_t fsc_div;                     
        HW_PCM_FSC_DELAY fsc_delay;           
        uint8_t fsc_length;                   
} hw_pcm_config_generic_pcm_t;
 
typedef struct {
        HW_PCM_CYCLE_PER_BIT cycle_per_bit;   
        uint8_t fsc_length;                   
        uint16_t fsc_div;                     
        HW_PCM_FSC_POLARITY fsc_polarity;     
} hw_pcm_config_i2s_mode_t;
 
typedef struct {
        HW_PCM_CYCLE_PER_BIT cycle_per_bit;   
        HW_PCM_CLK_POLARITY clock_polarity;   
        uint8_t channel_delay;                
        uint16_t fsc_div;                     
        HW_PCM_FSC_POLARITY fsc_polarity;     
        uint8_t fsc_length;                   
} hw_pcm_config_tdm_mode_t;
 
typedef struct {
        HW_PCM_CLK_POLARITY clock_polarity;   
        HW_PCM_FSC_POLARITY fsc_polarity;     
        uint16_t fsc_div;                     
} hw_pcm_config_iom_mode_t;
 
typedef enum {
        /* Generic PCM interface format configuration */
        HW_PCM_CONFIG_GENERIC_PCM_MODE,
        /* PCM-I2S configuration */
        HW_PCM_CONFIG_I2S_MODE,
        /* PCM-TDM configuration */
        HW_PCM_CONFIG_TDM_MODE,
        /* PCM-IOM configuration */
        HW_PCM_CONFIG_IOM_MODE
} HW_PCM_CONFIG_MODE;
 
typedef struct {
        /* PCM mode configuration is placed in mode specific structures */
        HW_PCM_CONFIG_MODE config_mode;         
        HW_PCM_MODE pcm_mode;                   
        HW_PCM_DO_OUTPUT_MODE gpio_output_mode; 
        union {
                hw_pcm_config_generic_pcm_t pcm_param;
                hw_pcm_config_i2s_mode_t    i2s_param;
                hw_pcm_config_tdm_mode_t    tdm_param;
                hw_pcm_config_iom_mode_t    iom_param;
        };
} hw_pcm_config_t;
 
typedef struct {
        HW_PCM_CLOCK clock;                     
        uint8_t sample_rate;                    
        uint16_t bit_depth;                     
        uint8_t chs;                            
        uint16_t ch_delay;                      
        HW_PCM_CYCLE_PER_BIT cycle_per_bit;     
        uint8_t slot;                           
        uint16_t fsc_div;                      
        HW_PCM_CLK_GENERATION div;              
} hw_pcm_clk_cfg_t;
 
__STATIC_INLINE void hw_pcm_clk_enable(void)
{
        // Enable PCM interface clock source
        HW_PCM_CRG_REG_SET_BIT(DIV, CLK_PCM_EN);
}
 
__STATIC_INLINE void hw_pcm_clk_disable(void)
{
        // Disable PCM interface clock source
        HW_PCM_CRG_REG_CLR_BIT(DIV, CLK_PCM_EN);
}
 
__STATIC_INLINE bool hw_pcm_clk_is_enabled(void)
{
        return (HW_PCM_CRG_REG_GETF(DIV, CLK_PCM_EN));
}
 
__STATIC_INLINE void hw_pcm_enable(void)
{
        // Enable PCM interface
        HW_PCM_SRC_REG_SET_BIT(CTRL, PCM_EN);
}
 
__STATIC_INLINE void hw_pcm_disable(void)
{
        // Disable PCM interface
        HW_PCM_SRC_REG_CLR_BIT(CTRL, PCM_EN);
}
 
__STATIC_INLINE bool hw_pcm_is_enabled(void)
{
        return (HW_PCM_SRC_REG_GETF(CTRL, PCM_EN));
}
 
__STATIC_INLINE uint8_t hw_pcm_get_channel_delay()
{
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_CH_DEL));
}
 
__STATIC_INLINE bool hw_pcm_get_fsc_edge(void)
{
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_FSC_EDGE));
}
 
__STATIC_INLINE uint8_t hw_pcm_get_fsc_length(void)
{
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_FSCLEN));
}
 
__STATIC_INLINE uint16_t hw_pcm_get_fsc_div(void)
{
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_FSC_DIV));
}
 
__STATIC_INLINE bool hw_pcm_get_fsc_delay(void)
{
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_FSCDEL));
}
 
__STATIC_INLINE bool hw_pcm_get_clk_polarity(void)
{
 
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_CLKINV));
}
 
__STATIC_INLINE bool hw_pcm_get_fsc_polarity(void)
{
 
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_FSCINV));
}
 
__STATIC_INLINE bool hw_pcm_get_clk_per_bit(void)
{
       return (HW_PCM_SRC_REG_GETF(CTRL, PCM_CLK_BIT));
}
 
__STATIC_INLINE HW_PCM_INPUT_MUX hw_pcm_get_pcm_input_mux(void)
{
        // Set PCM1_MUX_IN field in SRC1 MUX register
        return(REG_GETF(SRC1, SRC1_MUX_REG, PCM1_MUX_IN));
}
 
__STATIC_INLINE HW_PCM_DO_OUTPUT_MODE hw_pcm_get_output_mode(void)
{
        // Set PCM_PPOD field in PCM control register
        return(HW_PCM_SRC_REG_GETF(CTRL, PCM_PPOD));
}
 
__STATIC_INLINE HW_PCM_MODE hw_pcm_get_mode(void)
{
        return(HW_PCM_SRC_REG_GETF(CTRL, PCM_MASTER));
}
 
__STATIC_INLINE void hw_pcm_set_mode(HW_PCM_MODE mode)
{
        HW_PCM_SRC_REG_SETF(CTRL, PCM_MASTER, mode); // set/reset PCM_MASTER bit
}
 
 
HW_PCM_ERROR_CODE hw_pcm_init_clk(hw_pcm_clk_cfg_t *pcm_clk);
 
void hw_pcm_init(hw_pcm_config_t *config);
 
__STATIC_INLINE void hw_pcm_set_channel_delay(uint8_t delay)
{
        // Delay has a maximum value of 31
        ASSERT_WARNING(delay <= 3);
        // Set PCM_CH_DEL field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_CH_DEL, delay);
}
 
__STATIC_INLINE void hw_pcm_set_fsc_edge(HW_PCM_FSC_EDGE edge)
{
        // Set PCM_FSC_EDGE field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_FSC_EDGE, edge);
}
 
__STATIC_INLINE void hw_pcm_set_fsc_length(uint8_t length)
{
        ASSERT_WARNING(length <= 8);
 
        // Set PCM_FSCLEN field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_FSCLEN, length);
}
 
__STATIC_INLINE void hw_pcm_set_fsc_div(uint16_t div)
{
        uint32_t pcm1_ctrl_reg = PCM1->PCM1_CTRL_REG;
 
        ASSERT_WARNING(div >= 8 && div <= 0x1000);
 
        if (pcm1_ctrl_reg & REG_MSK(PCM1, PCM1_CTRL_REG, PCM_CLK_BIT)) {
                ASSERT_ERROR((div % 2 == 0));
        }
 
        // Set PCM_FSC_DIV field in PCM control register
        REG_SET_FIELD(PCM1, PCM1_CTRL_REG, PCM_FSC_DIV, pcm1_ctrl_reg, div - 1);
 
        PCM1->PCM1_CTRL_REG = pcm1_ctrl_reg;
}
 
__STATIC_INLINE void hw_pcm_set_fsc_delay(HW_PCM_FSC_DELAY delay)
{
        // Set PCM_FSCDEL field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_FSCDEL, delay);
}
 
__STATIC_INLINE void hw_pcm_set_clk_polarity(HW_PCM_CLK_POLARITY pol)
{
        // Set PCM_CLKINV field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_CLKINV, pol);
}
 
__STATIC_INLINE void hw_pcm_set_pcm_input_mux(HW_PCM_INPUT_MUX input)
{
        // Set PCM1_MUX_IN field in APU MUX register
        REG_SETF(SRC1, SRC1_MUX_REG, PCM1_MUX_IN, input);
}
 
__STATIC_INLINE void hw_pcm_set_fsc_polarity(HW_PCM_FSC_POLARITY pol)
{
        // Set PCM_FSCINV field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_FSCINV, pol);
}
 
__STATIC_INLINE void hw_pcm_set_clk_per_bit(HW_PCM_CYCLE_PER_BIT cycles)
{
        // Set PCM_CLK_BIT field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_CLK_BIT, cycles);
}
 
__STATIC_INLINE void hw_pcm_set_output_mode(HW_PCM_DO_OUTPUT_MODE mode)
{
        // Set PCM_PPOD field in PCM control register
        HW_PCM_SRC_REG_SETF(CTRL, PCM_PPOD, mode);
}
 
__STATIC_INLINE uint32_t hw_pcm_input_read(HW_PCM_INPUT input)
{
        switch (input) {
        case HW_PCM_INPUT_REG_1:
                return PCM1->PCM1_IN1_REG;
        case HW_PCM_INPUT_REG_2:
                return PCM1->PCM1_IN2_REG;
        default:
                ASSERT_WARNING(0);
        }
        return 0;
}
 
__STATIC_INLINE void hw_pcm_output_write(HW_PCM_OUTPUT output, const uint32_t data)
{
        switch (output) {
        case HW_PCM_OUTPUT_REG_1:
                PCM1->PCM1_OUT1_REG = data;
                break;
        case HW_PCM_OUTPUT_REG_2:
                PCM1->PCM1_OUT2_REG = data;
                break;
        default:
                ASSERT_WARNING(0);
        }
}
typedef void (*hw_pcm_interrupt_cb_t)(void);
 
void hw_pcm_register_interrupt(hw_pcm_interrupt_cb_t cb);
 
void hw_pcm_unregister_interrupt(void);
 
#endif /* dg_configUSE_HW_PCM */
#endif /* HW_PCM_H_ */