SmartSnippets DA1459x SDK
SEGGER_RTT_Conf.h
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48 ---------------------------END-OF-HEADER------------------------------
49 File : SEGGER_RTT_Conf.h
50 Purpose : Implementation of SEGGER real-time transfer (RTT) which
51  allows real-time communication on targets which support
52  debugger memory accesses while the CPU is running.
53 Revision: $Rev: 21386 $
54 
55 */
56 
57 #ifndef SEGGER_RTT_CONF_H
58 #define SEGGER_RTT_CONF_H
59 
60 #if defined (CONFIG_RTT) || dg_configSYSTEMVIEW
61 
62 #ifdef __IAR_SYSTEMS_ICC__
63  #include <intrinsics.h>
64 #endif
65 
66 /*********************************************************************
67 *
68 * Defines, configurable
69 *
70 **********************************************************************
71 */
72 
73 //
74 // Take in and set to correct values for Cortex-A systems with CPU cache
75 //
76 //#define SEGGER_RTT_CPU_CACHE_LINE_SIZE (32) // Largest cache line size (in bytes) in the current system
77 //#define SEGGER_RTT_UNCACHED_OFF (0xFB000000) // Address alias where RTT CB and buffers can be accessed uncached
78 //
79 // Most common case:
80 // Up-channel 0: RTT
81 // Up-channel 1: SystemView
82 //
83 #ifndef SEGGER_RTT_MAX_NUM_UP_BUFFERS
84  #define SEGGER_RTT_MAX_NUM_UP_BUFFERS (3) // Max. number of up-buffers (T->H) available on this target (Default: 3)
85 #endif
86 //
87 // Most common case:
88 // Down-channel 0: RTT
89 // Down-channel 1: SystemView
90 //
91 #ifndef SEGGER_RTT_MAX_NUM_DOWN_BUFFERS
92  #define SEGGER_RTT_MAX_NUM_DOWN_BUFFERS (3) // Max. number of down-buffers (H->T) available on this target (Default: 3)
93 #endif
94 
95 #ifndef BUFFER_SIZE_UP
96  #define BUFFER_SIZE_UP (4096) // Size of the buffer for terminal output of target, up to host (Default: 1k)
97 #endif
98 
99 #ifndef BUFFER_SIZE_DOWN
100 #define BUFFER_SIZE_DOWN (16) // Size of the buffer for terminal input to target from host (Usually keyboard input) (Default: 16)
101 #endif
102 
103 #ifndef SEGGER_RTT_PRINTF_BUFFER_SIZE
104  #define SEGGER_RTT_PRINTF_BUFFER_SIZE (64u) // Size of buffer for RTT printf to bulk-send chars via RTT (Default: 64)
105 #endif
106 
107 #ifndef SEGGER_RTT_MODE_DEFAULT
108  #define SEGGER_RTT_MODE_DEFAULT SEGGER_RTT_MODE_NO_BLOCK_SKIP // Mode for pre-initialized terminal channel (buffer 0)
109 #endif
110 
111 /*********************************************************************
112 *
113 * RTT memcpy configuration
114 *
115 * memcpy() is good for large amounts of data,
116 * but the overhead is big for small amounts, which are usually stored via RTT.
117 * With SEGGER_RTT_MEMCPY_USE_BYTELOOP a simple byte loop can be used instead.
118 *
119 * SEGGER_RTT_MEMCPY() can be used to replace standard memcpy() in RTT functions.
120 * This is may be required with memory access restrictions,
121 * such as on Cortex-A devices with MMU.
122 */
123 #ifndef SEGGER_RTT_MEMCPY_USE_BYTELOOP
124  #define SEGGER_RTT_MEMCPY_USE_BYTELOOP 0 // 0: Use memcpy/SEGGER_RTT_MEMCPY, 1: Use a simple byte-loop
125 #endif
126 //
127 // Example definition of SEGGER_RTT_MEMCPY to external memcpy with GCC toolchains and Cortex-A targets
128 //
129 //#if ((defined __SES_ARM) || (defined __CROSSWORKS_ARM) || (defined __GNUC__)) && (defined (__ARM_ARCH_7A__))
130 // #define SEGGER_RTT_MEMCPY(pDest, pSrc, NumBytes) SEGGER_memcpy((pDest), (pSrc), (NumBytes))
131 //#endif
132 
133 //
134 // Target is not allowed to perform other RTT operations while string still has not been stored completely.
135 // Otherwise we would probably end up with a mixed string in the buffer.
136 // If using RTT from within interrupts, multiple tasks or multi processors, define the SEGGER_RTT_LOCK() and SEGGER_RTT_UNLOCK() function here.
137 //
138 // SEGGER_RTT_MAX_INTERRUPT_PRIORITY can be used in the sample lock routines on Cortex-M3/4.
139 // Make sure to mask all interrupts which can send RTT data, i.e. generate SystemView events, or cause task switches.
140 // When high-priority interrupts must not be masked while sending RTT data, SEGGER_RTT_MAX_INTERRUPT_PRIORITY needs to be adjusted accordingly.
141 // (Higher priority = lower priority number)
142 // Default value for embOS: 128u
143 // Default configuration in FreeRTOS: configMAX_SYSCALL_INTERRUPT_PRIORITY: ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
144 // In case of doubt mask all interrupts: 1 << (8 - BASEPRI_PRIO_BITS) i.e. 1 << 5 when 3 bits are implemented in NVIC
145 // or define SEGGER_RTT_LOCK() to completely disable interrupts.
146 //
147 #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
148  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20) // Interrupt priority to lock on SEGGER_RTT_LOCK on Cortex-M3/4 (Default: 0x20)
149 #endif
150 
151 /*********************************************************************
152 *
153 * RTT lock configuration for SEGGER Embedded Studio,
154 * Rowley CrossStudio and GCC
155 */
156 #if ((defined(__SES_ARM) || defined(__SES_RISCV) || defined(__CROSSWORKS_ARM) || defined(__GNUC__) || defined(__clang__)) && !defined (__CC_ARM) && !defined(WIN32))
157  #if (defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_8M_BASE__))
158  #define SEGGER_RTT_LOCK() { \
159  unsigned int _SEGGER_RTT__LockState; \
160  __asm volatile ("mrs %0, primask \n\t" \
161  "movs r1, #1 \n\t" \
162  "msr primask, r1 \n\t" \
163  : "=r" (_SEGGER_RTT__LockState) \
164  : \
165  : "r1", "cc" \
166  );
167 
168  #define SEGGER_RTT_UNLOCK() __asm volatile ("msr primask, %0 \n\t" \
169  : \
170  : "r" (_SEGGER_RTT__LockState) \
171  : \
172  ); \
173  }
174  #elif (defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__))
175  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
176  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
177  #endif
178  #define SEGGER_RTT_LOCK() { \
179  unsigned int _SEGGER_RTT__LockState; \
180  __asm volatile ("mrs %0, basepri \n\t" \
181  "mov r1, %1 \n\t" \
182  "msr basepri, r1 \n\t" \
183  : "=r" (_SEGGER_RTT__LockState) \
184  : "i"(SEGGER_RTT_MAX_INTERRUPT_PRIORITY) \
185  : "r1", "cc" \
186  );
187 
188  #define SEGGER_RTT_UNLOCK() __asm volatile ("msr basepri, %0 \n\t" \
189  : \
190  : "r" (_SEGGER_RTT__LockState) \
191  : \
192  ); \
193  }
194 
195  #elif defined(__ARM_ARCH_7A__)
196  #define SEGGER_RTT_LOCK() { \
197  unsigned int _SEGGER_RTT__LockState; \
198  __asm volatile ("mrs r1, CPSR \n\t" \
199  "mov %0, r1 \n\t" \
200  "orr r1, r1, #0xC0 \n\t" \
201  "msr CPSR_c, r1 \n\t" \
202  : "=r" (_SEGGER_RTT__LockState) \
203  : \
204  : "r1", "cc" \
205  );
206 
207  #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
208  "mrs r1, CPSR \n\t" \
209  "bic r1, r1, #0xC0 \n\t" \
210  "and r0, r0, #0xC0 \n\t" \
211  "orr r1, r1, r0 \n\t" \
212  "msr CPSR_c, r1 \n\t" \
213  : \
214  : "r" (_SEGGER_RTT__LockState) \
215  : "r0", "r1", "cc" \
216  ); \
217  }
218  #elif defined(__riscv) || defined(__riscv_xlen)
219  #define SEGGER_RTT_LOCK() { \
220  unsigned int _SEGGER_RTT__LockState; \
221  __asm volatile ("csrr %0, mstatus \n\t" \
222  "csrci mstatus, 8 \n\t" \
223  "andi %0, %0, 8 \n\t" \
224  : "=r" (_SEGGER_RTT__LockState) \
225  : \
226  : \
227  );
228 
229  #define SEGGER_RTT_UNLOCK() __asm volatile ("csrr a1, mstatus \n\t" \
230  "or %0, %0, a1 \n\t" \
231  "csrs mstatus, %0 \n\t" \
232  : \
233  : "r" (_SEGGER_RTT__LockState) \
234  : "a1" \
235  ); \
236  }
237  #else
238  #define SEGGER_RTT_LOCK()
239  #define SEGGER_RTT_UNLOCK()
240  #endif
241 #endif
242 
243 /*********************************************************************
244 *
245 * RTT lock configuration for IAR EWARM
246 */
247 #ifdef __ICCARM__
248  #if (defined (__ARM6M__) && (__CORE__ == __ARM6M__)) || \
249  (defined (__ARM8M_BASELINE__) && (__CORE__ == __ARM8M_BASELINE__))
250  #define SEGGER_RTT_LOCK() { \
251  unsigned int _SEGGER_RTT__LockState; \
252  _SEGGER_RTT__LockState = __get_PRIMASK(); \
253  __set_PRIMASK(1);
254 
255  #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
256  }
257  #elif (defined (__ARM7EM__) && (__CORE__ == __ARM7EM__)) || \
258  (defined (__ARM7M__) && (__CORE__ == __ARM7M__)) || \
259  (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__)) || \
260  (defined (__ARM8M_MAINLINE__) && (__CORE__ == __ARM8M_MAINLINE__))
261  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
262  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
263  #endif
264  #define SEGGER_RTT_LOCK() { \
265  unsigned int _SEGGER_RTT__LockState; \
266  _SEGGER_RTT__LockState = __get_BASEPRI(); \
267  __set_BASEPRI(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
268 
269  #define SEGGER_RTT_UNLOCK() __set_BASEPRI(_SEGGER_RTT__LockState); \
270  }
271  #elif (defined (__ARM7A__) && (__CORE__ == __ARM7A__)) || \
272  (defined (__ARM7R__) && (__CORE__ == __ARM7R__))
273  #define SEGGER_RTT_LOCK() { \
274  unsigned int _SEGGER_RTT__LockState; \
275  __asm volatile ("mrs r1, CPSR \n\t" \
276  "mov %0, r1 \n\t" \
277  "orr r1, r1, #0xC0 \n\t" \
278  "msr CPSR_c, r1 \n\t" \
279  : "=r" (_SEGGER_RTT__LockState) \
280  : \
281  : "r1", "cc" \
282  );
283 
284  #define SEGGER_RTT_UNLOCK() __asm volatile ("mov r0, %0 \n\t" \
285  "mrs r1, CPSR \n\t" \
286  "bic r1, r1, #0xC0 \n\t" \
287  "and r0, r0, #0xC0 \n\t" \
288  "orr r1, r1, r0 \n\t" \
289  "msr CPSR_c, r1 \n\t" \
290  : \
291  : "r" (_SEGGER_RTT__LockState) \
292  : "r0", "r1", "cc" \
293  ); \
294  }
295  #endif
296 #endif
297 
298 /*********************************************************************
299 *
300 * RTT lock configuration for IAR RX
301 */
302 #ifdef __ICCRX__
303  #define SEGGER_RTT_LOCK() { \
304  unsigned long _SEGGER_RTT__LockState; \
305  _SEGGER_RTT__LockState = __get_interrupt_state(); \
306  __disable_interrupt();
307 
308  #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
309  }
310 #endif
311 
312 /*********************************************************************
313 *
314 * RTT lock configuration for IAR RL78
315 */
316 #ifdef __ICCRL78__
317  #define SEGGER_RTT_LOCK() { \
318  __istate_t _SEGGER_RTT__LockState; \
319  _SEGGER_RTT__LockState = __get_interrupt_state(); \
320  __disable_interrupt();
321 
322  #define SEGGER_RTT_UNLOCK() __set_interrupt_state(_SEGGER_RTT__LockState); \
323  }
324 #endif
325 
326 /*********************************************************************
327 *
328 * RTT lock configuration for KEIL ARM
329 */
330 #ifdef __CC_ARM
331  #if (defined __TARGET_ARCH_6S_M)
332  #define SEGGER_RTT_LOCK() { \
333  unsigned int _SEGGER_RTT__LockState; \
334  register unsigned char _SEGGER_RTT__PRIMASK __asm( "primask"); \
335  _SEGGER_RTT__LockState = _SEGGER_RTT__PRIMASK; \
336  _SEGGER_RTT__PRIMASK = 1u; \
337  __schedule_barrier();
338 
339  #define SEGGER_RTT_UNLOCK() _SEGGER_RTT__PRIMASK = _SEGGER_RTT__LockState; \
340  __schedule_barrier(); \
341  }
342  #elif (defined(__TARGET_ARCH_7_M) || defined(__TARGET_ARCH_7E_M))
343  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
344  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
345  #endif
346  #define SEGGER_RTT_LOCK() { \
347  unsigned int _SEGGER_RTT__LockState; \
348  register unsigned char BASEPRI __asm( "basepri"); \
349  SEGGER_RTT__LockState = BASEPRI; \
350  BASEPRI = SEGGER_RTT_MAX_INTERRUPT_PRIORITY; \
351  __schedule_barrier();
352 
353  #define SEGGER_RTT_UNLOCK() BASEPRI = _SEGGER_RTT__LockState; \
354  __schedule_barrier(); \
355  }
356  #endif
357 #endif
358 
359 /*********************************************************************
360 *
361 * RTT lock configuration for TI ARM
362 */
363 #ifdef __TI_ARM__
364  #if defined (__TI_ARM_V6M0__)
365  #define SEGGER_RTT_LOCK() { \
366  unsigned int _SEGGER_RTT__LockState; \
367  _SEGGER_RTT__LockState = __get_PRIMASK(); \
368  __set_PRIMASK(1);
369 
370  #define SEGGER_RTT_UNLOCK() __set_PRIMASK(_SEGGER_RTT__LockState); \
371  }
372  #elif (defined (__TI_ARM_V7M3__) || defined (__TI_ARM_V7M4__))
373  #ifndef SEGGER_RTT_MAX_INTERRUPT_PRIORITY
374  #define SEGGER_RTT_MAX_INTERRUPT_PRIORITY (0x20)
375  #endif
376  #define SEGGER_RTT_LOCK() { \
377  unsigned int _SEGGER_RTT__LockState; \
378  _SEGGER_RTT__LockState = _set_interrupt_priority(SEGGER_RTT_MAX_INTERRUPT_PRIORITY);
379 
380  #define SEGGER_RTT_UNLOCK() _set_interrupt_priority(_SEGGER_RTT__LockState); \
381  }
382  #endif
383 #endif
384 
385 /*********************************************************************
386 *
387 * RTT lock configuration for CCRX
388 */
389 #ifdef __RX
390  #include <machine.h>
391  #define SEGGER_RTT_LOCK() { \
392  unsigned long _SEGGER_RTT__LockState; \
393  _SEGGER_RTT__LockState = get_psw() & 0x010000; \
394  clrpsw_i();
395 
396  #define SEGGER_RTT_UNLOCK() set_psw(get_psw() | _SEGGER_RTT__LockState); \
397  }
398 #endif
399 
400 /*********************************************************************
401 *
402 * RTT lock configuration for embOS Simulation on Windows
403 * (Can also be used for generic RTT locking with embOS)
404 */
405 #if defined(WIN32) || defined(SEGGER_RTT_LOCK_EMBOS)
406 
407 void OS_SIM_EnterCriticalSection(void);
408 void OS_SIM_LeaveCriticalSection(void);
409 
410 #define SEGGER_RTT_LOCK() { \
411  OS_SIM_EnterCriticalSection();
412 
413 #define SEGGER_RTT_UNLOCK() OS_SIM_LeaveCriticalSection(); \
414  }
415 #endif
416 
417 /*********************************************************************
418 *
419 * RTT lock configuration fallback
420 */
421 #ifndef SEGGER_RTT_LOCK
422  #define SEGGER_RTT_LOCK() // Lock RTT (nestable) (i.e. disable interrupts)
423 #endif
424 
425 #ifndef SEGGER_RTT_UNLOCK
426  #define SEGGER_RTT_UNLOCK() // Unlock RTT (nestable) (i.e. enable previous interrupt lock state)
427 #endif
428 
429 #endif /* defined (CONFIG_RTT) || dg_configSYSTEMVIEW */
430 
431 #endif
432 /*************************** End of file ****************************/
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