41 #ifndef PLATFORM_NVPARAM_H_
42 #define PLATFORM_NVPARAM_H_
51 #define NVPARAM_BLE_PLATFORM_BD_ADDRESS 0x01 // 6 bytes array
52 #define NVPARAM_BLE_PLATFORM_LPCLK_DRIFT 0x07 // 16bit value
53 #define NVPARAM_BLE_PLATFORM_SLEEP_ENABLE 0x11 // byte
54 #define NVPARAM_BLE_PLATFORM_BLE_CA_TIMER_DUR 0x40 // 16bit value
55 #define NVPARAM_BLE_PLATFORM_BLE_CRA_TIMER_DUR 0x41 // byte
56 #define NVPARAM_BLE_PLATFORM_BLE_CA_MIN_RSSI 0x42 // byte
57 #define NVPARAM_BLE_PLATFORM_BLE_CA_NB_PKT 0x43 // 16bit value
58 #define NVPARAM_BLE_PLATFORM_BLE_CA_NB_BAD_PKT 0x44 // 16bit value
59 #define NVPARAM_BLE_PLATFORM_IRK 0x80 // 16 bytes array
64 #define NVPARAM_OFFSET_BLE_PLATFORM_BD_ADDRESS 0x0000
65 #define NVPARAM_OFFSET_BLE_PLATFORM_LPCLK_DRIFT 0x0007
66 #define NVPARAM_OFFSET_BLE_PLATFORM_SLEEP_ENABLE 0x0013
67 #define NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_TIMER_DUR 0x0017
68 #define NVPARAM_OFFSET_BLE_PLATFORM_BLE_CRA_TIMER_DUR 0x001A
69 #define NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_MIN_RSSI 0x001C
70 #define NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_NB_PKT 0x001E
71 #define NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_NB_BAD_PKT 0x0021
72 #define NVPARAM_OFFSET_BLE_PLATFORM_IRK 0x0024
79 NVPARAM_AREA(ble_platform, NVMS_PARAM_PART, 0x0000)
81 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_LPCLK_DRIFT, NVPARAM_OFFSET_BLE_PLATFORM_LPCLK_DRIFT, 3)
82 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_SLEEP_ENABLE, NVPARAM_OFFSET_BLE_PLATFORM_SLEEP_ENABLE, 2)
83 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_BLE_CA_TIMER_DUR, NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_TIMER_DUR, 3)
84 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_BLE_CRA_TIMER_DUR, NVPARAM_OFFSET_BLE_PLATFORM_BLE_CRA_TIMER_DUR, 2)
85 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_BLE_CA_MIN_RSSI, NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_MIN_RSSI, 2)
86 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_BLE_CA_NB_PKT, NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_NB_PKT, 3)
87 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_BLE_CA_NB_BAD_PKT, NVPARAM_OFFSET_BLE_PLATFORM_BLE_CA_NB_BAD_PKT, 3)
88 NVPARAM_PARAM(NVPARAM_BLE_PLATFORM_IRK, NVPARAM_OFFSET_BLE_PLATFORM_IRK, 17)