Type definitions for the Trace Port Interface (TPI) More...

Data Structures
struct	TPI_Type
	Structure type to access the Trace Port Interface Register (TPI). More...

Macros
#define	TPI_ACPR_PRESCALER_Pos 0U

#define	TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/)

#define	TPI_SPPR_TXMODE_Pos 0U

#define	TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/)

#define	TPI_FFSR_FtNonStop_Pos 3U

#define	TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

#define	TPI_FFSR_TCPresent_Pos 2U

#define	TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

#define	TPI_FFSR_FtStopped_Pos 1U

#define	TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

#define	TPI_FFSR_FlInProg_Pos 0U

#define	TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/)

#define	TPI_FFCR_TrigIn_Pos 8U

#define	TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

#define	TPI_FFCR_FOnMan_Pos 6U

#define	TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

#define	TPI_FFCR_EnFCont_Pos 1U

#define	TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

#define	TPI_TRIGGER_TRIGGER_Pos 0U

#define	TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/)

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

#define	TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

#define	TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

#define	TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

#define	TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /<< TPI_ITFTTD0_ATB_IF1_data0_Pos/)

#define	TPI_ITATBCTR2_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

#define	TPI_ITATBCTR2_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

#define	TPI_ITATBCTR2_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY2S_Pos/)

#define	TPI_ITATBCTR2_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY1S_Pos/)

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

#define	TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

#define	TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

#define	TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

#define	TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

#define	TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

#define	TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

#define	TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

#define	TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /<< TPI_ITFTTD1_ATB_IF2_data0_Pos/)

#define	TPI_ITATBCTR0_AFVALID2S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

#define	TPI_ITATBCTR0_AFVALID1S_Pos 1U

#define	TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

#define	TPI_ITATBCTR0_ATREADY2S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY2S_Pos/)

#define	TPI_ITATBCTR0_ATREADY1S_Pos 0U

#define	TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY1S_Pos/)

#define	TPI_ITCTRL_Mode_Pos 0U

#define	TPI_ITCTRL_Mode_Msk (0x3UL /<< TPI_ITCTRL_Mode_Pos/)

#define	TPI_DEVID_NRZVALID_Pos 11U

#define	TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

#define	TPI_DEVID_MANCVALID_Pos 10U

#define	TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

#define	TPI_DEVID_PTINVALID_Pos 9U

#define	TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

#define	TPI_DEVID_FIFOSZ_Pos 6U

#define	TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

#define	TPI_DEVID_NrTraceInput_Pos 0U

#define	TPI_DEVID_NrTraceInput_Msk (0x3FUL /<< TPI_DEVID_NrTraceInput_Pos/)

#define	TPI_DEVTYPE_SubType_Pos 4U

#define	TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/)

#define	TPI_DEVTYPE_MajorType_Pos 0U

#define	TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

Detailed Description

Type definitions for the Trace Port Interface (TPI)

Macro Definition Documentation

◆ TPI_ACPR_PRESCALER_Msk

#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/)

TPI ACPR: PRESCALER Mask

◆ TPI_ACPR_PRESCALER_Pos

#define TPI_ACPR_PRESCALER_Pos 0U

TPI ACPR: PRESCALER Position

◆ TPI_DEVID_FIFOSZ_Msk

#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos)

TPI DEVID: FIFOSZ Mask

◆ TPI_DEVID_FIFOSZ_Pos

#define TPI_DEVID_FIFOSZ_Pos 6U

TPI DEVID: FIFOSZ Position

◆ TPI_DEVID_MANCVALID_Msk

#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos)

TPI DEVID: MANCVALID Mask

◆ TPI_DEVID_MANCVALID_Pos

#define TPI_DEVID_MANCVALID_Pos 10U

TPI DEVID: MANCVALID Position

◆ TPI_DEVID_NrTraceInput_Msk

#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/)

TPI DEVID: NrTraceInput Mask

◆ TPI_DEVID_NrTraceInput_Pos

#define TPI_DEVID_NrTraceInput_Pos 0U

TPI DEVID: NrTraceInput Position

◆ TPI_DEVID_NRZVALID_Msk

#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos)

TPI DEVID: NRZVALID Mask

◆ TPI_DEVID_NRZVALID_Pos

#define TPI_DEVID_NRZVALID_Pos 11U

TPI DEVID: NRZVALID Position

◆ TPI_DEVID_PTINVALID_Msk

#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos)

TPI DEVID: PTINVALID Mask

◆ TPI_DEVID_PTINVALID_Pos

#define TPI_DEVID_PTINVALID_Pos 9U

TPI DEVID: PTINVALID Position

◆ TPI_DEVTYPE_MajorType_Msk

#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos)

TPI DEVTYPE: MajorType Mask

◆ TPI_DEVTYPE_MajorType_Pos

#define TPI_DEVTYPE_MajorType_Pos 0U

TPI DEVTYPE: MajorType Position

◆ TPI_DEVTYPE_SubType_Msk

#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/)

TPI DEVTYPE: SubType Mask

◆ TPI_DEVTYPE_SubType_Pos

#define TPI_DEVTYPE_SubType_Pos 4U

TPI DEVTYPE: SubType Position

◆ TPI_FFCR_EnFCont_Msk

#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos)

TPI FFCR: EnFCont Mask

◆ TPI_FFCR_EnFCont_Pos

#define TPI_FFCR_EnFCont_Pos 1U

TPI FFCR: EnFCont Position

◆ TPI_FFCR_FOnMan_Msk

#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos)

TPI FFCR: FOnMan Mask

◆ TPI_FFCR_FOnMan_Pos

#define TPI_FFCR_FOnMan_Pos 6U

TPI FFCR: FOnMan Position

◆ TPI_FFCR_TrigIn_Msk

#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos)

TPI FFCR: TrigIn Mask

◆ TPI_FFCR_TrigIn_Pos

#define TPI_FFCR_TrigIn_Pos 8U

TPI FFCR: TrigIn Position

◆ TPI_FFSR_FlInProg_Msk

#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/)

TPI FFSR: FlInProg Mask

◆ TPI_FFSR_FlInProg_Pos

#define TPI_FFSR_FlInProg_Pos 0U

TPI FFSR: FlInProg Position

◆ TPI_FFSR_FtNonStop_Msk

#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos)

TPI FFSR: FtNonStop Mask

◆ TPI_FFSR_FtNonStop_Pos

#define TPI_FFSR_FtNonStop_Pos 3U

TPI FFSR: FtNonStop Position

◆ TPI_FFSR_FtStopped_Msk

#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos)

TPI FFSR: FtStopped Mask

◆ TPI_FFSR_FtStopped_Pos

#define TPI_FFSR_FtStopped_Pos 1U

TPI FFSR: FtStopped Position

◆ TPI_FFSR_TCPresent_Msk

#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos)

TPI FFSR: TCPresent Mask

◆ TPI_FFSR_TCPresent_Pos

#define TPI_FFSR_TCPresent_Pos 2U

TPI FFSR: TCPresent Position

◆ TPI_ITATBCTR0_AFVALID1S_Msk

#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos)

TPI ITATBCTR0: AFVALID1SS Mask

◆ TPI_ITATBCTR0_AFVALID1S_Pos

#define TPI_ITATBCTR0_AFVALID1S_Pos 1U

TPI ITATBCTR0: AFVALID1S Position

◆ TPI_ITATBCTR0_AFVALID2S_Msk

#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos)

TPI ITATBCTR0: AFVALID2SS Mask

◆ TPI_ITATBCTR0_AFVALID2S_Pos

#define TPI_ITATBCTR0_AFVALID2S_Pos 1U

TPI ITATBCTR0: AFVALID2S Position

◆ TPI_ITATBCTR0_ATREADY1S_Msk

#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/)

TPI ITATBCTR0: ATREADY1S Mask

◆ TPI_ITATBCTR0_ATREADY1S_Pos

#define TPI_ITATBCTR0_ATREADY1S_Pos 0U

TPI ITATBCTR0: ATREADY1S Position

◆ TPI_ITATBCTR0_ATREADY2S_Msk

#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/)

TPI ITATBCTR0: ATREADY2S Mask

◆ TPI_ITATBCTR0_ATREADY2S_Pos

#define TPI_ITATBCTR0_ATREADY2S_Pos 0U

TPI ITATBCTR0: ATREADY2S Position

◆ TPI_ITATBCTR2_AFVALID1S_Msk

#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos)

TPI ITATBCTR2: AFVALID1SS Mask

◆ TPI_ITATBCTR2_AFVALID1S_Pos

#define TPI_ITATBCTR2_AFVALID1S_Pos 1U

TPI ITATBCTR2: AFVALID1S Position

◆ TPI_ITATBCTR2_AFVALID2S_Msk

#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos)

TPI ITATBCTR2: AFVALID2SS Mask

◆ TPI_ITATBCTR2_AFVALID2S_Pos

#define TPI_ITATBCTR2_AFVALID2S_Pos 1U

TPI ITATBCTR2: AFVALID2S Position

◆ TPI_ITATBCTR2_ATREADY1S_Msk

#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/)

TPI ITATBCTR2: ATREADY1S Mask

◆ TPI_ITATBCTR2_ATREADY1S_Pos

#define TPI_ITATBCTR2_ATREADY1S_Pos 0U

TPI ITATBCTR2: ATREADY1S Position

◆ TPI_ITATBCTR2_ATREADY2S_Msk

#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/)

TPI ITATBCTR2: ATREADY2S Mask

◆ TPI_ITATBCTR2_ATREADY2S_Pos

#define TPI_ITATBCTR2_ATREADY2S_Pos 0U

TPI ITATBCTR2: ATREADY2S Position

◆ TPI_ITCTRL_Mode_Msk

#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/)

TPI ITCTRL: Mode Mask

◆ TPI_ITCTRL_Mode_Pos

#define TPI_ITCTRL_Mode_Pos 0U

TPI ITCTRL: Mode Position

◆ TPI_ITFTTD0_ATB_IF1_ATVALID_Msk

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 1 ATVALID Mask

◆ TPI_ITFTTD0_ATB_IF1_ATVALID_Pos

#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U

TPI ITFTTD0: ATB Interface 1 ATVALID Position

◆ TPI_ITFTTD0_ATB_IF1_bytecount_Msk

#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos)

TPI ITFTTD0: ATB Interface 1 byte countt Mask

◆ TPI_ITFTTD0_ATB_IF1_bytecount_Pos

#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U

TPI ITFTTD0: ATB Interface 1 byte count Position

◆ TPI_ITFTTD0_ATB_IF1_data0_Msk

#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/)

TPI ITFTTD0: ATB Interface 1 data0 Mask

◆ TPI_ITFTTD0_ATB_IF1_data0_Pos

#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U

TPI ITFTTD0: ATB Interface 1 data0 Position

◆ TPI_ITFTTD0_ATB_IF1_data1_Msk

#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data1 Mask

◆ TPI_ITFTTD0_ATB_IF1_data1_Pos

#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U

TPI ITFTTD0: ATB Interface 1 data1 Position

◆ TPI_ITFTTD0_ATB_IF1_data2_Msk

#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos)

TPI ITFTTD0: ATB Interface 1 data2 Mask

◆ TPI_ITFTTD0_ATB_IF1_data2_Pos

#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U

TPI ITFTTD0: ATB Interface 1 data2 Position

◆ TPI_ITFTTD0_ATB_IF2_ATVALID_Msk

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos)

TPI ITFTTD0: ATB Interface 2 ATVALID Mask

◆ TPI_ITFTTD0_ATB_IF2_ATVALID_Pos

#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U

TPI ITFTTD0: ATB Interface 2 ATVALIDPosition

◆ TPI_ITFTTD0_ATB_IF2_bytecount_Msk

#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos)

TPI ITFTTD0: ATB Interface 2 byte count Mask

◆ TPI_ITFTTD0_ATB_IF2_bytecount_Pos

#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U

TPI ITFTTD0: ATB Interface 2 byte count Position

◆ TPI_ITFTTD1_ATB_IF1_ATVALID_Msk

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 1 ATVALID Mask

◆ TPI_ITFTTD1_ATB_IF1_ATVALID_Pos

#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U

TPI ITFTTD1: ATB Interface 1 ATVALID Position

◆ TPI_ITFTTD1_ATB_IF1_bytecount_Msk

#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos)

TPI ITFTTD1: ATB Interface 1 byte countt Mask

◆ TPI_ITFTTD1_ATB_IF1_bytecount_Pos

#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U

TPI ITFTTD1: ATB Interface 1 byte count Position

◆ TPI_ITFTTD1_ATB_IF2_ATVALID_Msk

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos)

TPI ITFTTD1: ATB Interface 2 ATVALID Mask

◆ TPI_ITFTTD1_ATB_IF2_ATVALID_Pos

#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U

TPI ITFTTD1: ATB Interface 2 ATVALID Position

◆ TPI_ITFTTD1_ATB_IF2_bytecount_Msk

#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos)

TPI ITFTTD1: ATB Interface 2 byte count Mask

◆ TPI_ITFTTD1_ATB_IF2_bytecount_Pos

#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U

TPI ITFTTD1: ATB Interface 2 byte count Position

◆ TPI_ITFTTD1_ATB_IF2_data0_Msk

#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/)

TPI ITFTTD1: ATB Interface 2 data0 Mask

◆ TPI_ITFTTD1_ATB_IF2_data0_Pos

#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U

TPI ITFTTD1: ATB Interface 2 data0 Position

◆ TPI_ITFTTD1_ATB_IF2_data1_Msk

#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data1 Mask

◆ TPI_ITFTTD1_ATB_IF2_data1_Pos

#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U

TPI ITFTTD1: ATB Interface 2 data1 Position

◆ TPI_ITFTTD1_ATB_IF2_data2_Msk

#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos)

TPI ITFTTD1: ATB Interface 2 data2 Mask

◆ TPI_ITFTTD1_ATB_IF2_data2_Pos

#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U

TPI ITFTTD1: ATB Interface 2 data2 Position

◆ TPI_SPPR_TXMODE_Msk

#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/)

TPI SPPR: TXMODE Mask

◆ TPI_SPPR_TXMODE_Pos

#define TPI_SPPR_TXMODE_Pos 0U

TPI SPPR: TXMODE Position

◆ TPI_TRIGGER_TRIGGER_Msk

#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/)

TPI TRIGGER: TRIGGER Mask

◆ TPI_TRIGGER_TRIGGER_Pos

#define TPI_TRIGGER_TRIGGER_Pos 0U

TPI TRIGGER: TRIGGER Position

Data Structures

Macros