hw_qspi_v2.h

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#ifndef HW_QSPI_V2_H_
#define HW_QSPI_V2_H_
 
 
#if dg_configUSE_HW_QSPI
 
#include <stdbool.h>
#include <stdint.h>
#include <sdk_defs.h>
 
/*
 * ENUMERATION DEFINITIONS
 *****************************************************************************************
 */
 
typedef enum {
        HW_QSPI_ACCESS_MODE_MANUAL = 0,        
        HW_QSPI_ACCESS_MODE_AUTO = 1           
} HW_QSPI_ACCESS_MODE;
 
typedef enum {
        HW_QSPI_ADDR_SIZE_24 = 0,      
        HW_QSPI_ADDR_SIZE_32 = 1       
} HW_QSPI_ADDR_SIZE;
 
typedef enum {
        HW_QSPI_BUS_MODE_SINGLE = 0,   
        HW_QSPI_BUS_MODE_DUAL = 1,     
        HW_QSPI_BUS_MODE_QUAD = 2,     
} HW_QSPI_BUS_MODE;
 
typedef enum {
        HW_QSPI_BUS_STATUS_IDLE = 0,           
        HW_QSPI_BUS_STATUS_ACTIVE = 1,         
} HW_QSPI_BUS_STATUS;
 
typedef enum {
        HW_QSPI_BUSY_LEVEL_LOW = 0,   
        HW_QSPI_BUSY_LEVEL_HIGH = 1   
} HW_QSPI_BUSY_LEVEL;
 
typedef enum {
        HW_QSPI_CLK_DIV_1 = 0,      
        HW_QSPI_CLK_DIV_2 = 1,      
        HW_QSPI_CLK_DIV_4 = 2,      
        HW_QSPI_CLK_DIV_8 = 3       
} HW_QSPI_CLK_DIV;
 
typedef enum {
        HW_QSPI_CLK_MODE_LOW = 0,       
        HW_QSPI_CLK_MODE_HIGH = 1       
} HW_QSPI_CLK_MODE;
 
typedef enum {
        HW_QSPI_CONTINUOUS_MODE_DISABLE = 0,   
        HW_QSPI_CONTINUOUS_MODE_ENABLE = 1     
} HW_QSPI_CONTINUOUS_MODE;
 
typedef enum {
        HW_QSPI_DRIVE_CURRENT_4 = 0,       
        HW_QSPI_DRIVE_CURRENT_8 = 1,       
        HW_QSPI_DRIVE_CURRENT_12 = 2,      
        HW_QSPI_DRIVE_CURRENT_16 = 3,      
} HW_QSPI_DRIVE_CURRENT;
 
typedef enum {
        HW_QSPI_EXTRA_BYTE_DISABLE = 0,        
        HW_QSPI_EXTRA_BYTE_ENABLE = 1,         
} HW_QSPI_EXTRA_BYTE;
 
typedef enum {
        HW_QSPI_EXTRA_BYTE_HALF_DISABLE = 0,   
        HW_QSPI_EXTRA_BYTE_HALF_ENABLE = 1,    
} HW_QSPI_EXTRA_BYTE_HALF;
 
typedef enum {
        HW_QSPI_HREADY_MODE_WAIT = 0,          
        HW_QSPI_HREADY_MODE_NO_WAIT = 1        
} HW_QSPI_HREADY_MODE;
 
typedef enum {
        HW_QSPI_IO_DIR_AUTO_SEL = 0,   
        HW_QSPI_IO_DIR_OUTPUT = 1      
} HW_QSPI_IO_DIR;
 
typedef enum {
        HW_QSPI_IO_VALUE_LOW = 0,      
        HW_QSPI_IO_VALUE_HIGH = 1,     
} HW_QSPI_IO_VALUE;
 
typedef enum {
        HW_QSPI_READ_PIPE_DISABLE = 0,         
        HW_QSPI_READ_PIPE_ENABLE = 1,          
} HW_QSPI_READ_PIPE;
 
typedef enum {
        HW_QSPI_READ_PIPE_DELAY_0 = 0,         
        HW_QSPI_READ_PIPE_DELAY_1 = 1,         
        HW_QSPI_READ_PIPE_DELAY_2 = 2,         
        HW_QSPI_READ_PIPE_DELAY_3 = 3,         
        HW_QSPI_READ_PIPE_DELAY_4 = 4,         
        HW_QSPI_READ_PIPE_DELAY_5 = 5,         
        HW_QSPI_READ_PIPE_DELAY_6 = 6,         
        HW_QSPI_READ_PIPE_DELAY_7 = 7,         
} HW_QSPI_READ_PIPE_DELAY;
 
typedef enum {
        HW_QSPI_SAMPLING_EDGE_POS = 0,    
        HW_QSPI_SAMPLING_EDGE_NEG = 1     
} HW_QSPI_SAMPLING_EDGE;
 
typedef enum {
        HW_QSPI_SLEW_RATE_0 = 0,       
        HW_QSPI_SLEW_RATE_1 = 1,       
        HW_QSPI_SLEW_RATE_2 = 2,       
        HW_QSPI_SLEW_RATE_3 = 3        
} HW_QSPI_SLEW_RATE;
 
typedef enum {
        HW_QSPI_ERASE_STATUS_NO = 0,             
        HW_QSPI_ERASE_STATUS_PENDING = 1,        
        HW_QSPI_ERASE_STATUS_RUNNING = 2,        
        HW_QSPI_ERASE_STATUS_SUSPENDED = 3,      
        HW_QSPI_ERASE_STATUS_FINISHING = 4       
} HW_QSPI_ERASE_STATUS;
/*
 * MACROS DEFINITIONS
 *****************************************************************************************
 */
#define IS_HW_QSPI_ACCESS_MODE(x)              (((x) == HW_QSPI_ACCESS_MODE_MANUAL) || \
                                                ((x) == HW_QSPI_ACCESS_MODE_AUTO))
 
#define IS_HW_QSPI_ADDR_SIZE(x)                (((x) == HW_QSPI_ADDR_SIZE_24)   || \
                                                ((x) == HW_QSPI_ADDR_SIZE_32))
 
#define IS_HW_QSPI_BUSY_LEVEL(x)               (((x) == HW_QSPI_BUSY_LEVEL_LOW)   || \
                                                ((x) == HW_QSPI_BUSY_LEVEL_HIGH))
 
#define IS_HW_QSPI_BUS_MODE(x)                 (((x) >= HW_QSPI_BUS_MODE_SINGLE) && \
                                                ((x) <= HW_QSPI_BUS_MODE_QUAD))
 
#define IS_HW_QSPI_CLK_DIV(x)                  (((x) >= HW_QSPI_CLK_DIV_1) && \
                                                ((x) <= HW_QSPI_CLK_DIV_8))
 
#define IS_HW_QSPI_CLK_MODE(x)                 (((x) == HW_QSPI_CLK_MODE_LOW) || \
                                                ((x) == HW_QSPI_CLK_MODE_HIGH))
 
#define IS_HW_QSPI_CONTINUOUS_MODE(x)          (((x) == HW_QSPI_CONTINUOUS_MODE_DISABLE) || \
                                                ((x) == HW_QSPI_CONTINUOUS_MODE_ENABLE))
 
#define IS_HW_QSPI_DRIVE_CURRENT(x)            (((x) >= HW_QSPI_DRIVE_CURRENT_4)  && \
                                                ((x) <= HW_QSPI_DRIVE_CURRENT_16))
 
#define IS_HW_QSPI_EXTRA_BYTE(x)               (((x) == HW_QSPI_EXTRA_BYTE_DISABLE) || \
                                                ((x) == HW_QSPI_EXTRA_BYTE_ENABLE))
 
#define IS_HW_QSPI_EXTRA_BYTE_HALF(x)          (((x) == HW_QSPI_EXTRA_BYTE_HALF_DISABLE) || \
                                                ((x) == HW_QSPI_EXTRA_BYTE_HALF_ENABLE))
 
#define IS_HW_QSPI_HREADY_MODE(x)              (((x) == HW_QSPI_HREADY_MODE_WAIT) || \
                                                ((x) == HW_QSPI_HREADY_MODE_NO_WAIT))
 
#define IS_HW_QSPI_IO_DIR(x)                   (((x) == HW_QSPI_IO_DIR_AUTO_SEL) || \
                                                ((x) == HW_QSPI_IO_DIR_OUTPUT))
 
#define IS_HW_QSPI_IO_VALUE(x)                 (((x) == HW_QSPI_IO_VALUE_LOW) || \
                                                ((x) == HW_QSPI_IO_VALUE_HIGH))
 
#define IS_HW_QSPI_READ_PIPE(x)                (((x) == HW_QSPI_READ_PIPE_DISABLE)   || \
                                                ((x) == HW_QSPI_READ_PIPE_ENABLE))
 
#define IS_HW_QSPI_READ_PIPE_DELAY(x)          (((x) >= HW_QSPI_READ_PIPE_DELAY_0)  && \
                                                ((x) <= HW_QSPI_READ_PIPE_DELAY_7))
 
#define IS_HW_QSPI_SAMPLING_EDGE(x)            (((x) == HW_QSPI_SAMPLING_EDGE_POS) || \
                                                ((x) == HW_QSPI_SAMPLING_EDGE_NEG))
 
#define IS_HW_QSPI_SLEW_RATE(x)                (((x) >= HW_QSPI_SLEW_RATE_0)  && \
                                                ((x) <= HW_QSPI_SLEW_RATE_3))
 
#define SUSPEND_RESUME_COUNTER_FREQ_HZ          (288000)
/*
 * STRUCTURE DEFINITIONS
 *****************************************************************************************
 */
typedef union {
        __IO uint32_t  data32;
        __IO uint16_t  data16;
        __IO uint8_t   data8;
} hw_qspi_data_t;
 
typedef struct {
        HW_QSPI_ADDR_SIZE               address_size : 1;       
        HW_QSPI_CLK_DIV                 clk_div : 2;            
        HW_QSPI_CLK_MODE                clock_mode : 1;         
        HW_QSPI_DRIVE_CURRENT           drive_current : 2;      
        HW_QSPI_READ_PIPE               read_pipe : 1;          
        HW_QSPI_READ_PIPE_DELAY         read_pipe_delay : 3;    
        HW_QSPI_SAMPLING_EDGE           sampling_edge :1;       
        HW_QSPI_SLEW_RATE               slew_rate : 2;          
        HW_QSPI_HREADY_MODE             hready_mode : 1;        
} hw_qspi_config_t;
 
typedef struct {
        HW_QSPI_BUS_MODE                opcode_bus_mode : 2;    
        HW_QSPI_BUS_MODE                addr_bus_mode : 2;      
        HW_QSPI_BUS_MODE                extra_byte_bus_mode : 2;
        HW_QSPI_BUS_MODE                dummy_bus_mode : 2;     
        HW_QSPI_BUS_MODE                data_bus_mode : 2;      
        HW_QSPI_CONTINUOUS_MODE         continuous_mode : 1;    
        HW_QSPI_EXTRA_BYTE              extra_byte_cfg : 1;     
        HW_QSPI_EXTRA_BYTE_HALF         extra_byte_half_cfg : 1;
        uint8_t                         opcode;                 
        uint8_t                         extra_byte_value;       
        uint16_t                        cs_idle_delay_nsec;     
} hw_qspi_read_instr_config_t;
 
typedef struct {
        HW_QSPI_BUS_MODE        opcode_bus_mode : 2;    
        HW_QSPI_BUS_MODE        addr_bus_mode : 2;      
        uint32_t                hclk_cycles : 4;        
        uint8_t                 opcode;                 
        uint16_t                cs_idle_delay_nsec;     
} hw_qspi_erase_instr_config_t;
 
typedef struct {
        HW_QSPI_BUS_MODE                opcode_bus_mode : 2;    
        HW_QSPI_BUS_MODE                receive_bus_mode : 2;   
        HW_QSPI_BUSY_LEVEL              busy_level : 1;         
        uint32_t                        busy_pos : 3;           
        uint8_t                         opcode;                 
        uint16_t                        delay_nsec;             
} hw_qspi_read_status_instr_config_t;
 
typedef struct {
        HW_QSPI_BUS_MODE        opcode_bus_mode: 2;     
        uint8_t                 opcode;                 
} hw_qspi_write_enable_instr_config_t;
 
typedef struct {
        HW_QSPI_BUS_MODE        opcode_bus_mode : 2;    
        HW_QSPI_BUS_MODE        addr_bus_mode : 2;      
        HW_QSPI_BUS_MODE        data_bus_mode : 2;      
        uint8_t                 opcode;                 
} hw_qspi_page_program_instr_config_t;
 
typedef struct {
        HW_QSPI_BUS_MODE                suspend_bus_mode : 2;   
        HW_QSPI_BUS_MODE                resume_bus_mode : 2;    
        uint8_t                         suspend_opcode;         
        uint8_t                         resume_opcode;          
        uint8_t                         suspend_latency_usec;   
        uint8_t                         resume_latency_usec;    
        uint16_t                        res_sus_latency_usec;   
} hw_qspi_suspend_resume_instr_config_t;
 
typedef void * HW_QSPIC_ID;
#define HW_QSPIC        ((HW_QSPIC_ID) QSPIC_BASE)
 
/* QSPI Base Address */
#define QSPIBA(id)    ((QSPIC_Type *) id)
 
#define HW_QSPIC_REG_GETF(id, reg, field) \
        ((QSPIBA(id)->QSPIC_##reg##_REG & QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) >> \
         QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)
 
#define HW_QSPIC_REG_SETF(id, reg, field, new_val) \
        QSPIBA(id)->QSPIC_##reg##_REG = ((QSPIBA(id)->QSPIC_##reg##_REG & \
                                         ~QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) | \
                                        (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk & \
                                         ((new_val) << QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)))
 
#define HW_QSPIC_REG_SET_BIT(id, reg, field) \
        QSPIBA(id)->QSPIC_##reg##_REG |= (1 << QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)
 
#define HW_QSPIC_REG_CLR_BIT(id, reg, field) \
        QSPIBA(id)->QSPIC_##reg##_REG &= ~QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk
 
__STATIC_FORCEINLINE void hw_qspi_clock_enable(HW_QSPIC_ID id)
{
        GLOBAL_INT_DISABLE();
        REG_SET_BIT(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_qspi_clock_disable(HW_QSPIC_ID id)
{
        GLOBAL_INT_DISABLE();
        REG_CLR_BIT(CRG_TOP, CLK_AMBA_REG, QSPI_ENABLE);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_qspi_cs_enable(HW_QSPIC_ID id)
{
        QSPIBA(id)->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_EN_CS);
}
 
__STATIC_FORCEINLINE void hw_qspi_cs_disable(HW_QSPIC_ID id)
{
        QSPIBA(id)->QSPIC_CTRLBUS_REG = REG_MSK(QSPIC, QSPIC_CTRLBUS_REG, QSPIC_DIS_CS);
}
 
__STATIC_FORCEINLINE HW_QSPI_BUS_STATUS hw_qspi_get_bus_status(HW_QSPIC_ID id)
{
        return (HW_QSPI_BUS_STATUS) HW_QSPIC_REG_GETF(id, STATUS, BUSY);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_div(HW_QSPIC_ID id, HW_QSPI_CLK_DIV div)
{
        ASSERT_WARNING(IS_HW_QSPI_CLK_DIV(div));
 
        GLOBAL_INT_DISABLE();
        REG_SETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV, div);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE HW_QSPI_CLK_DIV hw_qspi_get_div(HW_QSPIC_ID id)
{
        return (HW_QSPI_CLK_DIV) REG_GETF(CRG_TOP, CLK_AMBA_REG, QSPI_DIV);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_manual_access_bus_mode(HW_QSPIC_ID id, HW_QSPI_BUS_MODE bus_mode)
{
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(bus_mode));
 
        QSPIBA(id)->QSPIC_CTRLBUS_REG = 1 << bus_mode;
}
 
__STATIC_FORCEINLINE void hw_qspi_set_access_mode(HW_QSPIC_ID id, HW_QSPI_ACCESS_MODE access_mode)
{
        ASSERT_WARNING(IS_HW_QSPI_ACCESS_MODE(access_mode));
        // During erasing where QSPIC_ERASE_EN = 1, QSPIC_AUTO_MD switches in read only mode
        ASSERT_WARNING(HW_QSPIC_REG_GETF(id, ERASECTRL, ERASE_EN) == 0);
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, AUTO_MD, access_mode);
}
 
__STATIC_FORCEINLINE HW_QSPI_ACCESS_MODE hw_qspi_get_access_mode(HW_QSPIC_ID id)
{
        return (HW_QSPI_ACCESS_MODE) HW_QSPIC_REG_GETF(id, CTRLMODE, AUTO_MD);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_clock_mode(HW_QSPIC_ID id, HW_QSPI_CLK_MODE clk_mode)
{
        ASSERT_WARNING(IS_HW_QSPI_CLK_MODE(clk_mode));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, CLK_MD, clk_mode);
}
 
__STATIC_FORCEINLINE HW_QSPI_CLK_MODE hw_qspi_get_clock_mode(HW_QSPIC_ID id)
{
        return (HW_QSPI_CLK_MODE) HW_QSPIC_REG_GETF(id, CTRLMODE, CLK_MD);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_io2_direction(HW_QSPIC_ID id, HW_QSPI_IO_DIR dir)
{
        ASSERT_WARNING(IS_HW_QSPI_IO_DIR(dir));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, IO2_OEN, dir);
}
 
__STATIC_FORCEINLINE HW_QSPI_IO_DIR hw_qspi_get_io2_direction(HW_QSPIC_ID id)
{
        return (HW_QSPI_IO_DIR) HW_QSPIC_REG_GETF(id, CTRLMODE, IO2_OEN);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_io3_direction(HW_QSPIC_ID id, HW_QSPI_IO_DIR dir)
{
        ASSERT_WARNING(IS_HW_QSPI_IO_DIR(dir));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, IO3_OEN, dir);
}
 
__STATIC_FORCEINLINE HW_QSPI_IO_DIR hw_qspi_get_io3_direction(HW_QSPIC_ID id)
{
        return (HW_QSPI_IO_DIR) HW_QSPIC_REG_GETF(id, CTRLMODE, IO3_OEN);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_io2_value(HW_QSPIC_ID id, HW_QSPI_IO_VALUE value)
{
        ASSERT_WARNING(IS_HW_QSPI_IO_VALUE(value));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, IO2_DAT, (uint32_t) value);
}
 
__STATIC_FORCEINLINE HW_QSPI_IO_VALUE hw_qspi_get_io2_value(HW_QSPIC_ID id)
{
        return (HW_QSPI_IO_VALUE) HW_QSPIC_REG_GETF(id, CTRLMODE, IO2_DAT);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_io3_value(HW_QSPIC_ID id, HW_QSPI_IO_VALUE value)
{
        ASSERT_WARNING(IS_HW_QSPI_IO_VALUE(value));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, IO3_DAT, (uint32_t) value);
}
 
__STATIC_FORCEINLINE HW_QSPI_IO_VALUE hw_qspi_get_io3_value(HW_QSPIC_ID id)
{
        return (HW_QSPI_IO_VALUE) HW_QSPIC_REG_GETF(id, CTRLMODE, IO3_DAT);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_io(HW_QSPIC_ID id, HW_QSPI_BUS_MODE bus_mode)
{
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(bus_mode));
 
        uint32_t ctrlmode_reg = QSPIBA(id)->QSPIC_CTRLMODE_REG;
 
        if (bus_mode == HW_QSPI_BUS_MODE_SINGLE) {
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, ctrlmode_reg, 1);
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, ctrlmode_reg, 1);
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, ctrlmode_reg, 1);
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, ctrlmode_reg, 1);
        } else {
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_OEN, ctrlmode_reg, 0);
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO2_DAT, ctrlmode_reg, 0);
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_OEN, ctrlmode_reg, 0);
                REG_SET_FIELD(QSPIC, QSPIC_CTRLMODE_REG, QSPIC_IO3_DAT, ctrlmode_reg, 0);
        }
 
        QSPIBA(id)->QSPIC_CTRLMODE_REG = ctrlmode_reg;
}
 
__STATIC_FORCEINLINE void hw_qspi_set_hready_mode(HW_QSPIC_ID id, HW_QSPI_HREADY_MODE mode)
{
        ASSERT_WARNING(IS_HW_QSPI_HREADY_MODE(mode));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, HRDY_MD, mode);
}
 
__STATIC_FORCEINLINE HW_QSPI_HREADY_MODE hw_qspi_get_hready_mode(HW_QSPIC_ID id)
{
        return (HW_QSPI_HREADY_MODE) HW_QSPIC_REG_GETF(id, CTRLMODE, HRDY_MD);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_read_sampling_edge(HW_QSPIC_ID id, HW_QSPI_SAMPLING_EDGE edge)
{
        ASSERT_WARNING(IS_HW_QSPI_SAMPLING_EDGE(edge));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, RXD_NEG, edge);
}
 
__STATIC_FORCEINLINE HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge(HW_QSPIC_ID id)
{
        return (HW_QSPI_SAMPLING_EDGE) HW_QSPIC_REG_GETF(id, CTRLMODE, RXD_NEG);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_read_pipe(HW_QSPIC_ID id, HW_QSPI_READ_PIPE read_pipe)
{
        ASSERT_WARNING(IS_HW_QSPI_READ_PIPE(read_pipe));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, RPIPE_EN, read_pipe);
}
 
__STATIC_FORCEINLINE HW_QSPI_READ_PIPE hw_qspi_get_read_pipe(HW_QSPIC_ID id)
{
        return (HW_QSPI_READ_PIPE) HW_QSPIC_REG_GETF(id, CTRLMODE, RPIPE_EN);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_read_pipe_clock_delay(HW_QSPIC_ID id, HW_QSPI_READ_PIPE_DELAY delay)
{
        ASSERT_WARNING(IS_HW_QSPI_READ_PIPE_DELAY(delay));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, PCLK_MD, delay);
}
 
__STATIC_FORCEINLINE HW_QSPI_READ_PIPE_DELAY hw_qspi_get_read_pipe_clock_delay(HW_QSPIC_ID id)
{
        return (HW_QSPI_READ_PIPE_DELAY) HW_QSPIC_REG_GETF(id, CTRLMODE, PCLK_MD);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_address_size(HW_QSPIC_ID id, HW_QSPI_ADDR_SIZE addr_size)
{
        ASSERT_WARNING(IS_HW_QSPI_ADDR_SIZE(addr_size));
 
        HW_QSPIC_REG_SETF(id, CTRLMODE, USE_32BA, addr_size);
}
 
__STATIC_FORCEINLINE HW_QSPI_ADDR_SIZE hw_qspi_get_address_size(HW_QSPIC_ID id)
{
        return (HW_QSPI_ADDR_SIZE) HW_QSPIC_REG_GETF(id, CTRLMODE, USE_32BA);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_slew_rate(HW_QSPIC_ID id, HW_QSPI_SLEW_RATE slew_rate)
{
        ASSERT_WARNING(IS_HW_QSPI_SLEW_RATE(slew_rate));
 
        HW_QSPIC_REG_SETF(id, GP, PADS_SLEW , slew_rate);
}
 
__STATIC_FORCEINLINE HW_QSPI_SLEW_RATE hw_qspi_get_slew_rate(HW_QSPIC_ID id)
{
        return (HW_QSPI_SLEW_RATE) HW_QSPIC_REG_GETF(id, GP, PADS_SLEW);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_drive_current(HW_QSPIC_ID id, HW_QSPI_DRIVE_CURRENT drive_current)
{
        ASSERT_WARNING(IS_HW_QSPI_DRIVE_CURRENT(drive_current));
 
        HW_QSPIC_REG_SETF(id, GP, PADS_DRV, drive_current);
}
 
__STATIC_FORCEINLINE HW_QSPI_DRIVE_CURRENT hw_qspi_get_drive_current(HW_QSPIC_ID id)
{
        return (HW_QSPI_DRIVE_CURRENT) HW_QSPIC_REG_GETF(id, GP, PADS_DRV);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_dummy_bytes(HW_QSPIC_ID id, uint8_t dummy_bytes)
{
        ASSERT_WARNING(dummy_bytes < 5);
 
        if (dummy_bytes == 3) {
                HW_QSPIC_REG_SET_BIT(id, BURSTCMDB, DMY_FORCE);
        } else {
                HW_QSPIC_REG_CLR_BIT(id, BURSTCMDB, DMY_FORCE);
                HW_QSPIC_REG_SETF(id, BURSTCMDB, DMY_NUM, ((dummy_bytes == 4) ? 3 : dummy_bytes));
        }
}
 
__STATIC_FORCEINLINE uint8_t hw_qspi_get_dummy_bytes(HW_QSPIC_ID id)
{
        uint8_t dummy_bytes;
 
        if (HW_QSPIC_REG_GETF(id, BURSTCMDB, DMY_FORCE)) {
                return 3;
        }
 
        dummy_bytes = HW_QSPIC_REG_GETF(id, BURSTCMDB, DMY_NUM);
 
        return (dummy_bytes == 3) ? 4 : dummy_bytes;
}
 
__STATIC_FORCEINLINE void hw_qspi_set_read_cs_idle_delay(HW_QSPIC_ID id, uint16_t cs_idle_delay_nsec,
                                                         uint32_t clk_freq_hz)
{
        uint32_t cs_idle_delay_clk;
 
        cs_idle_delay_clk = NSEC_TO_CLK_CYCLES(cs_idle_delay_nsec, clk_freq_hz);
 
        ASSERT_WARNING(cs_idle_delay_clk < 8);
        HW_QSPIC_REG_SETF(id, BURSTCMDB, CS_HIGH_MIN, cs_idle_delay_clk);
}
 
__STATIC_FORCEINLINE void hw_qspi_set_erase_cs_idle_delay(HW_QSPIC_ID id, uint16_t cs_idle_delay_nsec,
                                                          uint32_t clk_freq_hz)
{
        uint32_t cs_idle_delay_clk;
 
        cs_idle_delay_clk = NSEC_TO_CLK_CYCLES(cs_idle_delay_nsec, clk_freq_hz);
 
        ASSERT_WARNING(cs_idle_delay_clk < 32);
        HW_QSPIC_REG_SETF(id, ERASECMDB, ERS_CS_HI, cs_idle_delay_clk);
}
 
__STATIC_FORCEINLINE uint32_t hw_qspi_read32(HW_QSPIC_ID id)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_READDATA_REG);
 
        return tmp->data32;
}
 
__STATIC_FORCEINLINE uint16_t hw_qspi_read16(HW_QSPIC_ID id)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_READDATA_REG);
 
        return tmp->data16;
}
 
__STATIC_FORCEINLINE uint8_t hw_qspi_read8(HW_QSPIC_ID id)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_READDATA_REG);
 
        return tmp->data8;
}
 
__STATIC_FORCEINLINE void hw_qspi_write32(HW_QSPIC_ID id, uint32_t data)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_WRITEDATA_REG);
 
        tmp->data32 = SWAP32(data);
}
 
__STATIC_FORCEINLINE void hw_qspi_write16(HW_QSPIC_ID id, uint16_t data)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_WRITEDATA_REG);
 
        tmp->data16 = SWAP16(data);
}
 
__STATIC_FORCEINLINE void hw_qspi_write8(HW_QSPIC_ID id, uint8_t data)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_WRITEDATA_REG);
 
        tmp->data8 = data;
}
 
__STATIC_FORCEINLINE void hw_qspi_dummy32(HW_QSPIC_ID id)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_DUMMYDATA_REG);
 
        tmp->data32 = 0;
}
 
__STATIC_FORCEINLINE void hw_qspi_dummy16(HW_QSPIC_ID id)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_DUMMYDATA_REG);
 
        tmp->data16 = 0;
}
 
__STATIC_FORCEINLINE void hw_qspi_dummy8(HW_QSPIC_ID id)
{
        hw_qspi_data_t *tmp = (hw_qspi_data_t *) &(QSPIBA(id)->QSPIC_DUMMYDATA_REG);
 
        tmp->data8 = 0;
}
 
__RETAINED_CODE void hw_qspi_init(HW_QSPIC_ID id, const hw_qspi_config_t *cfg);
 
__STATIC_FORCEINLINE void hw_qspi_read_instr_init(HW_QSPIC_ID id, const hw_qspi_read_instr_config_t *cfg,
                                                  uint8_t dummy_bytes, uint32_t sys_clk_freq_hz)
{
        uint32_t qspi_clk_freq_hz = sys_clk_freq_hz >> (uint32_t) hw_qspi_get_div(id);
        uint32_t delay_clk_cycles = NSEC_TO_CLK_CYCLES(cfg->cs_idle_delay_nsec, qspi_clk_freq_hz);
        uint32_t burstcmda_reg = QSPIBA(id)->QSPIC_BURSTCMDA_REG;
        uint32_t burstcmdb_reg = QSPIBA(id)->QSPIC_BURSTCMDB_REG;
 
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->opcode_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->addr_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->extra_byte_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->dummy_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->data_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_EXTRA_BYTE(cfg->extra_byte_cfg));
        ASSERT_WARNING(IS_HW_QSPI_EXTRA_BYTE_HALF(cfg->extra_byte_half_cfg));
        ASSERT_WARNING(IS_HW_QSPI_CONTINUOUS_MODE(cfg->continuous_mode));
        ASSERT_WARNING(dummy_bytes < 5);
        ASSERT_WARNING(delay_clk_cycles < 8);
 
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST, burstcmda_reg, cfg->opcode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_BYTE, burstcmda_reg, cfg->extra_byte_value);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_INST_TX_MD, burstcmda_reg, cfg->opcode_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_ADR_TX_MD, burstcmda_reg, cfg->addr_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_EXT_TX_MD, burstcmda_reg, cfg->extra_byte_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDA_REG, QSPIC_DMY_TX_MD, burstcmda_reg, cfg->dummy_bus_mode);
 
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DAT_RX_MD, burstcmdb_reg, cfg->data_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_BYTE_EN, burstcmdb_reg, cfg->extra_byte_cfg);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_EXT_HF_DS, burstcmdb_reg, cfg->extra_byte_half_cfg);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_INST_MD, burstcmdb_reg, cfg->continuous_mode);
 
        if (dummy_bytes == 3) {
                REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE, burstcmdb_reg, 1);
                REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, burstcmdb_reg, 0);
        } else {
                REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_FORCE, burstcmdb_reg, 0);
                REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_DMY_NUM, burstcmdb_reg,
                              ((dummy_bytes == 4) ? 3 : dummy_bytes));
        }
 
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_INST_MD, burstcmdb_reg, cfg->continuous_mode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTCMDB_REG, QSPIC_CS_HIGH_MIN, burstcmdb_reg, delay_clk_cycles);
 
        QSPIBA(id)->QSPIC_BURSTCMDA_REG = burstcmda_reg;
        QSPIBA(id)->QSPIC_BURSTCMDB_REG = burstcmdb_reg;
}
 
__STATIC_FORCEINLINE void hw_qspi_erase_instr_init(HW_QSPIC_ID id, const hw_qspi_erase_instr_config_t *cfg,
                                                   uint32_t sys_clk_freq_hz)
{
        uint32_t qspi_clk_freq_hz = sys_clk_freq_hz >> (uint32_t) hw_qspi_get_div(id);
        uint32_t delay_clk_cycles = NSEC_TO_CLK_CYCLES(cfg->cs_idle_delay_nsec, qspi_clk_freq_hz);
        uint32_t erasecmdb_reg = QSPIBA(id)->QSPIC_ERASECMDB_REG;
 
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->opcode_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->addr_bus_mode));
        ASSERT_WARNING(cfg->hclk_cycles < 16);
        ASSERT_WARNING(delay_clk_cycles < 32);
 
        HW_QSPIC_REG_SETF(id, ERASECMDA, ERS_INST, cfg->opcode);
 
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_TX_MD, erasecmdb_reg, cfg->opcode_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_EAD_TX_MD, erasecmdb_reg, cfg->addr_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERSRES_HLD, erasecmdb_reg, cfg->hclk_cycles);
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_ERS_CS_HI, erasecmdb_reg, delay_clk_cycles);
 
        QSPIBA(id)->QSPIC_ERASECMDB_REG = erasecmdb_reg;
}
 
__STATIC_FORCEINLINE void hw_qspi_read_status_instr_init(HW_QSPIC_ID id, const hw_qspi_read_status_instr_config_t *cfg,
                                                         uint32_t sys_clk_freq_hz)
{
        uint32_t qspi_clk_freq_hz = sys_clk_freq_hz >> (uint32_t) hw_qspi_get_div(id);
        uint32_t delay_clk_cycles = NSEC_TO_CLK_CYCLES(cfg->delay_nsec, qspi_clk_freq_hz);
        uint32_t statuscmd_reg = QSPIBA(id)->QSPIC_STATUSCMD_REG;
 
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->opcode_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->receive_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUSY_LEVEL(cfg->busy_level));
        ASSERT_WARNING(cfg->busy_pos < 8);
        ASSERT_WARNING(delay_clk_cycles < 64);
 
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_INST, statuscmd_reg, cfg->opcode);
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_TX_MD, statuscmd_reg, cfg->opcode_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RSTAT_RX_MD, statuscmd_reg, cfg->receive_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_POS, statuscmd_reg, cfg->busy_pos);
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_BUSY_VAL, statuscmd_reg, cfg->busy_level);
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_RESSTS_DLY, statuscmd_reg, delay_clk_cycles);
        REG_SET_FIELD(QSPIC, QSPIC_STATUSCMD_REG, QSPIC_STSDLY_SEL, statuscmd_reg, 0);
 
        QSPIBA(id)->QSPIC_STATUSCMD_REG = statuscmd_reg;
}
 
__STATIC_FORCEINLINE void hw_qspi_write_enable_instr_init(HW_QSPIC_ID id, const hw_qspi_write_enable_instr_config_t *cfg)
{
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->opcode_bus_mode));
 
        HW_QSPIC_REG_SETF(id, ERASECMDA, WEN_INST, cfg->opcode);
        HW_QSPIC_REG_SETF(id, ERASECMDB, WEN_TX_MD, cfg->opcode_bus_mode);
}
 
__STATIC_FORCEINLINE void hw_qspi_suspend_resume_instr_init(HW_QSPIC_ID id, const hw_qspi_suspend_resume_instr_config_t *cfg)
{
        uint32_t res_sus_latency_clk_cycles = NSEC_TO_CLK_CYCLES((1000 * cfg->res_sus_latency_usec), SUSPEND_RESUME_COUNTER_FREQ_HZ);
 
        uint32_t erasecmda_reg = QSPIBA(id)->QSPIC_ERASECMDA_REG;
        uint32_t erasecmdb_reg = QSPIBA(id)->QSPIC_ERASECMDB_REG;
 
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->suspend_bus_mode));
        ASSERT_WARNING(IS_HW_QSPI_BUS_MODE(cfg->resume_bus_mode));
        ASSERT_WARNING(res_sus_latency_clk_cycles < 64);
 
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDA_REG, QSPIC_SUS_INST, erasecmda_reg, cfg->suspend_opcode);
 
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_SUS_TX_MD, erasecmdb_reg, cfg->suspend_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RES_TX_MD, erasecmdb_reg, cfg->resume_bus_mode);
        REG_SET_FIELD(QSPIC, QSPIC_ERASECMDB_REG, QSPIC_RESSUS_DLY, erasecmdb_reg, res_sus_latency_clk_cycles);
 
        QSPIBA(id)->QSPIC_ERASECMDA_REG = erasecmda_reg;
        QSPIBA(id)->QSPIC_ERASECMDB_REG = erasecmdb_reg;
}
 
__STATIC_FORCEINLINE void hw_qspi_exit_continuous_mode_instr_init(HW_QSPIC_ID id, HW_QSPI_CONTINUOUS_MODE mode,
                                                                  HW_QSPI_ADDR_SIZE addr_size)
{
        uint32_t burstbrk_reg = QSPIBA(id)->QSPIC_BURSTBRK_REG;
 
        REG_SET_FIELD(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_WRD, burstbrk_reg, 0xFFFF);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_TX_MD, burstbrk_reg, HW_QSPI_BUS_MODE_SINGLE);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_SEC_HF_DS, burstbrk_reg, 0);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_EN, burstbrk_reg, mode);
        REG_SET_FIELD(QSPIC, QSPIC_BURSTBRK_REG, QSPIC_BRK_SZ, burstbrk_reg, ((addr_size == HW_QSPI_ADDR_SIZE_32) ? 1 : 0));
 
        QSPIBA(id)->QSPIC_BURSTBRK_REG = burstbrk_reg;
}
 
__STATIC_FORCEINLINE void hw_qspi_set_erase_address(HW_QSPIC_ID id, uint32_t erase_addr)
{
        HW_QSPIC_REG_SETF(id, ERASECTRL, ERS_ADDR, erase_addr);
}
 
__STATIC_FORCEINLINE void hw_qspi_trigger_erase(HW_QSPIC_ID id)
{
        HW_QSPIC_REG_SET_BIT(id, ERASECTRL, ERASE_EN);
}
 
__STATIC_FORCEINLINE HW_QSPI_ERASE_STATUS hw_qspi_get_erase_status(HW_QSPIC_ID id)
{
        // Dummy access to QSPIC_CHCKERASE_REG in order to trigger a read status command
        HW_QSPIC_REG_SETF(id, CHCKERASE, CHCKERASE, 0);
        return (HW_QSPI_ERASE_STATUS) HW_QSPIC_REG_GETF(id, ERASECTRL, ERS_STATE);
}
 
__RETAINED_CODE void hw_qspi_erase_block(HW_QSPIC_ID id, uint32_t addr);
 
__STATIC_FORCEINLINE void hw_qspi_set_extra_byte(HW_QSPIC_ID id, uint8_t extra_byte,
                                                 HW_QSPI_BUS_MODE bus_mode, bool half_disable_out)
{
        HW_QSPIC_REG_SETF(id, BURSTCMDA, EXT_BYTE, extra_byte);
        HW_QSPIC_REG_SETF(id, BURSTCMDA, EXT_TX_MD, bus_mode);
 
        HW_QSPIC_REG_SETF(id, BURSTCMDB, EXT_BYTE_EN, 1);
        HW_QSPIC_REG_SETF(id, BURSTCMDB, EXT_HF_DS, half_disable_out);
}
 
__STATIC_FORCEINLINE void hw_qspi_exit_continuous_mode_sequence_enable(HW_QSPIC_ID id)
{
        HW_QSPIC_REG_SET_BIT(id, BURSTBRK, BRK_EN);
}
 
__STATIC_FORCEINLINE void hw_qspi_exit_continuous_mode_sequence_disable(HW_QSPIC_ID id)
{
        HW_QSPIC_REG_CLR_BIT(id, BURSTBRK, BRK_EN);
}
#endif /* dg_configUSE_HW_QSPI */
 
 
#endif /* HW_QSPI_V2_H_ */