hw_src.h

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#ifndef HW_SRC_H_
#define HW_SRC_H_
 
#if dg_configUSE_HW_SRC
#include <stdbool.h>
#include <stdint.h>
#include "sdk_defs.h"
 
#define BASE_TYPE       SRC1_Type
 
#define HW_SRC1         ((void *)SRC1_BASE)
#define HW_SRC2         ((void *)SRC2_BASE)
 
/* SRC Base Address */
#define SRCBA(id)      ((BASE_TYPE *)id)
 
typedef void * HW_SRC_ID;
 
#define MUX_REG     SRC1_MUX_REG
 
#define CTRL_REG     SRC1_CTRL_REG
 
#define HW_SRC_REG_GETF(id, base, reg, field)                                                   \
        ((SRCBA(id)->SRC1_##reg & (base##_SRC1_##reg##_##field##_Msk)) >> (base##_SRC1_##reg##_##field##_Pos))
 
#define HW_SRC_REG_SETF(id, base, reg, field, val)                                                \
        SRCBA(id)->SRC1_##reg = ((SRCBA(id)->SRC1_##reg & ~(base##_SRC1_##reg##_##field##_Msk)) |                    \
        ((base##_SRC1_##reg##_##field##_Msk) &  ((val) << (base##_SRC1_##reg##_##field##_Pos))))
 
#define  HW_SRC_REG_SET_FIELD(base, reg, field, var, val)                                       \
        var = (((var & ~(base##_SRC1_##reg##_##field##_Msk))) |                                 \
                (((val) << (base##_SRC1_##reg##_##field##_Pos)) &                               \
                (base##_SRC1_##reg##_##field##_Msk)))
 
#define HW_SRC_REG_GET_FIELD(base, reg, field, var)                                             \
        ((var & (base##_SRC1_##reg##_##field##_Msk)) >>                                         \
                (base##_SRC1_##reg##_##field##_Pos))
 
#define HW_SRC_REG_CLR_FIELD(base, reg, field, var)                                             \
        var &= ~(base##_SRC1_##reg##_##field##_Msk)
 
#define HW_SRC_REG_SET_BIT(id, base, reg, field)                                                \
        do {                                                                                    \
                SRCBA(id)->SRC1_##reg |= (1 << (base##_SRC1_##reg##_##field##_Pos));            \
        } while (0)
 
 
#define HW_SRC_REG_CLR_BIT(id, base, reg, field)                                                \
        do {                                                                                    \
                SRCBA(id)->SRC1_##reg &= ~(base##_SRC1_##reg##_##field##_Msk);                  \
        } while (0)
 
typedef enum {
        HW_SRC_IN,  
        HW_SRC_OUT, 
} HW_SRC_DIRECTION;
 
typedef enum {
        HW_SRC_FLOW_OK = 0,         
        HW_SRC_FLOW_OVER,           
        HW_SRC_FLOW_UNDER,          
        HW_SRC_FLOW_OVER_UNDER,     
} HW_SRC_FLOW_STATUS;
 
typedef enum {
        HW_SRC_PCM = 1,         
        HW_SRC_PDM,         
        HW_SRC_REGS,        
# if dg_configUSE_HW_SDADC
        HW_SRC_SDADC,
# endif /* dg_configUSE_HW_SDADC */
        HW_SRC_SELECTION_SIZE
} HW_SRC_SELECTION;
 
typedef enum {
        HW_SRC_INPUT_MUX_OFF,              
        HW_SRC_INPUT_MUX_PCM_OUT_REG,      
        HW_SRC_INPUT_MUX_SRCx_IN_REG,      
        HW_SRC_INPUT_MUX_SDADC_OUT,        
        HW_SRCx_MUX_IN_SIZE
} HW_SRCx_MUX_IN;
 
typedef enum {
        HW_PDM_INPUT_MUX_SRCx_MUX_IN,        
        HW_PDM_INPUT_MUX_PDM_INPUT,          
} HW_PDM1_MUX_IN;
 
typedef struct {
        HW_SRC_ID       id;              
        uint16_t        src_clk;         
        uint32_t        in_sample_rate;  
        uint32_t        out_sample_rate; 
        HW_SRC_SELECTION  data_input;    
} hw_src_config_t;
 
/* *************************************************************************
 *
 *                       ENABLE-DISABLE FUNCTIONS
 *
 * ************************************************************************* */
 
__STATIC_INLINE void hw_src_enable(HW_SRC_ID id)
{
 
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        /*
         * The under/overflows that occur due to the reconfiguration can be
         * ignored, so we disable under/overflow notifications until
         * (SRC_IN_OK == 1 && SRC_OUT_OK == 1).
         */
        SRCBA(id)->SRC1_CTRL_REG |= REG_MSK(SRC1, SRC1_CTRL_REG, SRC_IN_FLOWCLR) |
                                    REG_MSK(SRC1, SRC1_CTRL_REG, SRC_OUT_FLOWCLR) |
                                    REG_MSK(SRC1, SRC1_CTRL_REG, SRC_EN);
 
        while (!(SRCBA(id)->SRC1_CTRL_REG & (REG_MSK(SRC1, SRC1_CTRL_REG, SRC_IN_OK) |
                                             REG_MSK(SRC1, SRC1_CTRL_REG, SRC_OUT_OK))));
 
        SRCBA(id)->SRC1_CTRL_REG &= ~(REG_MSK(SRC1, SRC1_CTRL_REG, SRC_IN_FLOWCLR) |
                                      REG_MSK(SRC1, SRC1_CTRL_REG, SRC_OUT_FLOWCLR));
}
 
__STATIC_INLINE void hw_src_disable(HW_SRC_ID id)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        HW_SRC_REG_CLR_BIT(id, SRC1, CTRL_REG, SRC_EN);
}
 
__STATIC_INLINE bool hw_src_is_enabled(HW_SRC_ID id)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        return (HW_SRC_REG_GETF(id, SRC1, CTRL_REG, SRC_EN));
}
 
__STATIC_INLINE void hw_src_enable_fifo(HW_SRC_ID id, HW_SRC_DIRECTION direction)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        uint32_t src1_ctrl_reg = SRCBA(id)->SRC1_CTRL_REG;
 
        switch (direction) {
        case HW_SRC_IN:
                REG_CLR_FIELD(SRC1, SRC1_CTRL_REG, SRC_FIFO_DIRECTION, src1_ctrl_reg);
                break;
        case HW_SRC_OUT:
                src1_ctrl_reg |= REG_MSK(SRC1, SRC1_CTRL_REG, SRC_FIFO_DIRECTION);
                break;
        default:
                ASSERT_WARNING(0);
        }
 
        src1_ctrl_reg |= REG_MSK(SRC1, SRC1_CTRL_REG, SRC_FIFO_ENABLE);
        SRCBA(id)->SRC1_CTRL_REG = src1_ctrl_reg;
}
 
__STATIC_INLINE void hw_src_disable_fifo(HW_SRC_ID id)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        HW_SRC_REG_CLR_BIT(id, SRC1, CTRL_REG, SRC_FIFO_ENABLE);
}
 
__STATIC_INLINE bool hw_src_is_fifo_enabled(HW_SRC_ID id)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        return(HW_SRC_REG_GETF(id, SRC1, CTRL_REG, SRC_FIFO_ENABLE));
}
 
/* *************************************************************************
 *
 *                              SET FUNCTIONS
 *
 * ************************************************************************* */
 
__STATIC_INLINE void hw_src_set_automode(HW_SRC_ID id, HW_SRC_DIRECTION direction)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        if (direction == HW_SRC_IN) {
                HW_SRC_REG_SET_BIT(id, SRC1, CTRL_REG, SRC_IN_AMODE);
        } else {
                HW_SRC_REG_SET_BIT(id, SRC1, CTRL_REG, SRC_OUT_AMODE);
        }
}
 
__STATIC_INLINE void hw_src_set_manual_mode(HW_SRC_ID id, HW_SRC_DIRECTION direction)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        if (direction == HW_SRC_IN) {
                HW_SRC_REG_CLR_BIT(id, SRC1, CTRL_REG, SRC_IN_AMODE);
        } else {
                HW_SRC_REG_CLR_BIT(id, SRC1, CTRL_REG, SRC_OUT_AMODE);
        }
}
 
__STATIC_INLINE void hw_src_select_input(HW_SRC_SELECTION input, hw_src_config_t *config)
{
        ASSERT_WARNING(input < HW_SRC_SELECTION_SIZE);
 
        config->data_input = input;
 
        ASSERT_WARNING(config->id == HW_SRC1 || config->id == HW_SRC2);
        uint32_t address = SRCBA(config->id)->MUX_REG;
 
        switch (config->data_input) {
        case HW_SRC_PDM:
                HW_SRC_REG_SET_FIELD(SRC1, MUX_REG, PDM1_MUX_IN, address, HW_PDM_INPUT_MUX_PDM_INPUT);
                HW_SRC_REG_CLR_FIELD(SRC1, MUX_REG, SRC1_MUX_IN, address);
                break;
        case HW_SRC_PCM:
                HW_SRC_REG_SET_FIELD(SRC1, MUX_REG, SRC1_MUX_IN, address, HW_SRC_INPUT_MUX_PCM_OUT_REG);
                HW_SRC_REG_CLR_FIELD(SRC1, MUX_REG, PDM1_MUX_IN, address); // HW_PDM_INPUT_MUX_SRCx_MUX_IN
                break;
        case HW_SRC_REGS:
                HW_SRC_REG_SET_FIELD(SRC1, MUX_REG, SRC1_MUX_IN, address, HW_SRC_INPUT_MUX_SRCx_IN_REG);
                HW_SRC_REG_CLR_FIELD(SRC1, MUX_REG, PDM1_MUX_IN, address);// HW_PDM_INPUT_MUX_SRCx_MUX_IN
                break;
# if dg_configUSE_HW_SDADC
        case HW_SRC_SDADC:
                HW_SRC_REG_SET_FIELD(SRC1, MUX_REG, SRC1_MUX_IN, address, HW_SRC_INPUT_MUX_SDADC_OUT);
                HW_SRC_REG_CLR_FIELD(SRC1, MUX_REG, PDM1_MUX_IN, address);// HW_PDM_INPUT_MUX_SRCx_MUX_IN
                break;
# endif /* dg_configUSE_HW_SDADC */
        default:
                ASSERT_WARNING(0);
        }
 
        SRCBA(config->id)->MUX_REG = address;
}
 
__STATIC_INLINE void hw_src_write_input(HW_SRC_ID id, uint8_t stream, uint32_t value)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        switch (stream) {
        case 1:
                HW_SRC_REG_SETF(id, SRC1, IN1_REG, SRC_IN, value);
                break;
        case 2:
                HW_SRC_REG_SETF(id, SRC1, IN2_REG, SRC_IN, value);
                break;
        default:
                ASSERT_WARNING(0);
        }
}
 
/* *************************************************************************
 *
 *                              GET FUNCTIONS
 *
 * ************************************************************************* */
 
__STATIC_INLINE bool hw_src_is_auto_mode(HW_SRC_ID id, HW_SRC_DIRECTION direction)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        if (direction == HW_SRC_IN) {
                return HW_SRC_REG_GETF(id, SRC1, CTRL_REG, SRC_IN_AMODE);
        } else {
                return HW_SRC_REG_GETF(id, SRC1, CTRL_REG, SRC_OUT_AMODE);
        }
}
 
__STATIC_INLINE uint32_t hw_src_read_output(HW_SRC_ID id, uint8_t stream)
{
 
        ASSERT_WARNING(id == HW_SRC1 || id == HW_SRC2);
 
        switch (stream) {
        case 1:
                return HW_SRC_REG_GETF(id, SRC1, OUT1_REG, SRC_OUT);
        case 2:
                return HW_SRC_REG_GETF(id, SRC1, OUT2_REG, SRC_OUT);
        default:
                ASSERT_WARNING(0);
                return 0;
        }
}
 
HW_SRC_FLOW_STATUS hw_src_get_flow_status(HW_SRC_ID id, HW_SRC_DIRECTION direction);
 
void hw_src_init(HW_SRC_ID id, hw_src_config_t *config);
#endif /* dg_configUSE_HW_SRC */
#endif /* HW_SRC_H_ */