hw_dma.h

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#ifndef HW_DMA_H_
#define HW_DMA_H_
 
 
#if dg_configUSE_HW_DMA
 
#include <stdint.h>
#include <sdk_defs.h>
 
#define HW_DMA_SECURE_DMA_CHANNEL               HW_DMA_CHANNEL_5
 
/*
* ENUMERATION DEFINITIONS
*****************************************************************************************
*/
 
typedef enum {
        HW_DMA_CHANNEL_0 = 0,   
        HW_DMA_CHANNEL_1 = 1,   
        HW_DMA_CHANNEL_2 = 2,   
        HW_DMA_CHANNEL_3 = 3,   
        HW_DMA_CHANNEL_4 = 4,   
        HW_DMA_CHANNEL_5 = 5,   
        HW_DMA_CHANNEL_INVALID  
} HW_DMA_CHANNEL;
 
typedef enum {
        HW_DMA_STATE_DISABLED = 0x0,    
        HW_DMA_STATE_ENABLED = 0x1      
} HW_DMA_STATE;
 
typedef enum {
        HW_DMA_BW_BYTE = 0x0,           
        HW_DMA_BW_HALFWORD = 0x2,       
        HW_DMA_BW_WORD = 0x4            
} HW_DMA_BW;
 
typedef enum {
        HW_DMA_IRQ_STATE_DISABLED = 0x0,        
        HW_DMA_IRQ_STATE_ENABLED = 0x8          
} HW_DMA_IRQ_STATE;
 
typedef enum {
        HW_DMA_DREQ_START = 0x0,                                        
        HW_DMA_DREQ_TRIGGERED = DMA_DMA0_CTRL_REG_DREQ_MODE_Msk         
} HW_DMA_DREQ;
 
typedef enum {
        HW_DMA_BURST_MODE_DISABLED      = 0x0,          
        HW_DMA_BURST_MODE_4x            = 0x2000,       
        HW_DMA_BURST_MODE_8x            = 0x4000,       
} HW_DMA_BURST_MODE;
 
typedef enum {
        HW_DMA_BINC_FALSE = 0x0,                        
        HW_DMA_BINC_TRUE  = DMA_DMA0_CTRL_REG_BINC_Msk  
} HW_DMA_BINC;
 
typedef enum {
        HW_DMA_AINC_FALSE = 0x0,                        
        HW_DMA_AINC_TRUE  = DMA_DMA0_CTRL_REG_AINC_Msk  
} HW_DMA_AINC;
 
typedef enum {
        HW_DMA_MODE_NORMAL = 0x0,                               
        HW_DMA_MODE_CIRCULAR = DMA_DMA0_CTRL_REG_CIRCULAR_Msk   
} HW_DMA_MODE;
 
typedef enum {
        HW_DMA_PRIO_0 = 0x000,  
        HW_DMA_PRIO_1 = 0x080,  
        HW_DMA_PRIO_2 = 0x100,  
        HW_DMA_PRIO_3 = 0x180,  
        HW_DMA_PRIO_4 = 0x200,  
        HW_DMA_PRIO_5 = 0x280,  
        HW_DMA_PRIO_6 = 0x300,  
        HW_DMA_PRIO_7 = 0x380   
} HW_DMA_PRIO;
 
typedef enum {
        HW_DMA_IDLE_BLOCKING_MODE = 0x000,                              
        HW_DMA_IDLE_INTERRUPTING_MODE = DMA_DMA0_CTRL_REG_DMA_IDLE_Msk  
} HW_DMA_IDLE;
 
typedef enum {
        HW_DMA_INIT_AX_BX_AY_BY = 0x0000,                               
        HW_DMA_INIT_AX_BX_BY    = DMA_DMA0_CTRL_REG_DMA_INIT_Msk        
} HW_DMA_INIT;
 
typedef enum {
        HW_DMA_TRIG_SPI_RXTX = 0x0,
        HW_DMA_TRIG_UART_RXTX = 0x1,
        HW_DMA_TRIG_UART2_RXTX = 0x2,
        HW_DMA_TRIG_I2C_RXTX = 0x3,
        HW_DMA_TRIG_PCM_RXTX = 0x4,
        HW_DMA_TRIG_SRC_RXRX = 0x5,
        HW_DMA_TRIG_SRC_TXTX = 0x6,
        HW_DMA_TRIG_SRC2_RXRX = 0x7,
        HW_DMA_TRIG_SRC2_TXTX = 0x8,
        HW_DMA_TRIG_SRC_SRC2_RXTX = 0x9,
        HW_DMA_TRIG_SRC2_SRC_RXTX = 0xA,
        HW_DMA_TRIG_SRC_RXTX = 0xB,
        HW_DMA_TRIG_SRC2_RXTX = 0xC,
        HW_DMA_TRIG_ADC = 0xD,
        HW_DMA_TRIG_SD_ADC_FCU = 0xE,
        HW_DMA_TRIG_NONE = 0xF
} HW_DMA_TRIG;
 
typedef uint32_t dma_size_t;
 
typedef void (*hw_dma_transfer_cb)(void *user_data, dma_size_t len);
 
typedef struct {
        HW_DMA_CHANNEL       channel_number;            
        HW_DMA_BW            bus_width;                 
        HW_DMA_IRQ_STATE     irq_enable;                
        uint16               irq_nr_of_trans;           
        HW_DMA_DREQ          dreq_mode;                 
        HW_DMA_BURST_MODE    burst_mode;                
        HW_DMA_AINC          a_inc;                     
        HW_DMA_BINC          b_inc;                     
        HW_DMA_MODE          circular;                  
        HW_DMA_PRIO          dma_prio;                  
        HW_DMA_IDLE          dma_idle;                  
        HW_DMA_INIT          dma_init;                  
        HW_DMA_TRIG          dma_req_mux;               
        uint32               src_address;               
        uint32               dest_address;              
        dma_size_t           length;                    
        hw_dma_transfer_cb   callback;                  
        void                 *user_data;                
} DMA_setup;
 
typedef struct {
        bool            use_prio;       
        HW_DMA_PRIO     rx_prio;        
        HW_DMA_PRIO     tx_prio;        
} hw_dma_periph_prio_t;
 
/*
* API FUNCTIONS DEFINITIONS
*****************************************************************************************
*/
 
void hw_dma_channel_initialization(DMA_setup *channel_setup);
 
void hw_dma_channel_update_source(HW_DMA_CHANNEL channel, void* addr, dma_size_t length,
                                                                        hw_dma_transfer_cb cb);
 
void hw_dma_channel_update_destination(HW_DMA_CHANNEL channel, void *addr, dma_size_t length,
                                                                        hw_dma_transfer_cb cb);
 
void hw_dma_channel_update_int_ix(HW_DMA_CHANNEL channel, uint16_t int_ix);
 
void hw_dma_channel_enable(HW_DMA_CHANNEL channel_number, HW_DMA_STATE dma_on);
 
void hw_dma_channel_stop(HW_DMA_CHANNEL channel_number);
 
dma_size_t hw_dma_transfered_bytes(HW_DMA_CHANNEL channel_number);
 
__STATIC_INLINE void hw_dma_freeze(void)
{
        GPREG->SET_FREEZE_REG = REG_MSK(GPREG, SET_FREEZE_REG, FRZ_DMA);
}
 
__STATIC_INLINE void hw_dma_unfreeze(void)
{
        GPREG->RESET_FREEZE_REG = REG_MSK(GPREG, RESET_FREEZE_REG, FRZ_DMA);
}
 
__STATIC_INLINE bool hw_dma_is_aes_key_protection_enabled(void)
{
        return (REG_GETF(CRG_TOP, SECURE_BOOT_REG, PROT_APP_KEY) == 1);
}
 
__STATIC_INLINE bool hw_dma_secure_channel_is_free(void)
{
        uint32_t secure_features_msk = REG_MSK(CRG_TOP, SECURE_BOOT_REG, PROT_APP_KEY);
 
        return ((CRG_TOP->SECURE_BOOT_REG & secure_features_msk) == 0);
}
 
__STATIC_INLINE bool hw_dma_bus_error_detected(HW_DMA_CHANNEL channel_number)
{
        return ((DMA->DMA_INT_STATUS_REG & (REG_MSK(DMA, DMA_INT_STATUS_REG, DMA_BUS_ERR0) << channel_number)) != 0);
}
 
bool hw_dma_is_channel_active(HW_DMA_CHANNEL channel_number);
 
__RETAINED_CODE bool hw_dma_channel_active(void);
 
#endif /* dg_configUSE_HW_DMA */
#endif /* HW_DMA_H_ */