Enumeration, structure, type and macro definitions.
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| enum | HW_SDADC_INPUT_MODE { HW_SDADC_INPUT_MODE_DIFFERENTIAL = 0,
HW_SDADC_INPUT_MODE_SINGLE_ENDED = 1
} |
| | SDADC input mode. More...
|
| |
| enum | HW_SDADC_VREF_SEL { HW_SDADC_VREF_INTERNAL = 0,
HW_SDADC_VREFN_INTERNAL_VREFP_EXTERNAL = 1,
HW_SDADC_VREFN_EXTERNAL_VREFP_INTERNAL = 2,
HW_SDADC_VREF_EXTERNAL = 3
} |
| | SDADC VREF selection. More...
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| |
| enum | HW_SDADC_INPUT_CHANNEL {
HW_SDADC_IN_ADC0_P1_00 = 0,
HW_SDADC_IN_ADC1_P1_01 = 1,
HW_SDADC_IN_ADC2_P1_02 = 2,
HW_SDADC_IN_ADC3_P0_10 = 3,
HW_SDADC_IN_ADC4_P1_05 = 4,
HW_SDADC_IN_ADC5_P1_06 = 5,
HW_SDADC_IN_ADC6_P1_09 = 6,
HW_SDADC_IN_ADC7_P1_11 = 7,
HW_SDADC_IN_VBAT = 8
} |
| | SDADC Input Channel. More...
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| |
| enum | HW_SDADC_MODE { HW_SDADC_MODE_SENSOR = 0,
HW_SDADC_MODE_AUDIO = 1
} |
| | SDADC mode (sensor/audio) More...
|
| |
| enum | HW_SDADC_INPUT |
| | SDADC input selection. Generic names mapping to specific GPIO pins for both positive and negative channels. More...
|
| |
| enum | HW_SDADC_OSR { HW_SDADC_OSR_256,
HW_SDADC_OSR_512,
HW_SDADC_OSR_1024,
HW_SDADC_OSR_2048
} |
| | SDADC oversampling rate. More...
|
| |
| enum | HW_SDADC_PGA_GAIN {
HW_SDADC_PGA_GAIN_MINUS_12dB = 0,
HW_SDADC_PGA_GAIN_MINUS_6dB = 1,
HW_SDADC_PGA_GAIN_MINUS_0dB = 2,
HW_SDADC_PGA_GAIN_6dB = 3,
HW_SDADC_PGA_GAIN_12dB = 4,
HW_SDADC_PGA_GAIN_18dB = 5,
HW_SDADC_PGA_GAIN_24dB = 6,
HW_SDADC_PGA_GAIN_30dB = 7
} |
| | PGA gain selection. More...
|
| |
| enum | HW_SDADC_PGA_MODE { HW_SDADC_PGA_MODE_DIFF = 0,
HW_SDADC_PGA_MODE_SE_N = 1,
HW_SDADC_PGA_MODE_SE_P = 2,
HW_SDADC_PGA_MODE_RESERVED = 3
} |
| | PGA mode selection. More...
|
| |
| enum | HW_SDADC_PGA_BIAS {
HW_SDADC_PGA_BIAS_40 = 0,
HW_SDADC_PGA_BIAS_44 = 1,
HW_SDADC_PGA_BIAS_50 = 2,
HW_SDADC_PGA_BIAS_57 = 3,
HW_SDADC_PGA_BIAS_66 = 4,
HW_SDADC_PGA_BIAS_80 = 5,
HW_SDADC_PGA_BIAS_100 = 6,
HW_SDADC_PGA_BIAS_133 = 7
} |
| | PGA bias configuration. More...
|
| |
| enum | HW_SDADC_PGA_EN { HW_SDADC_PGA_ENABLE_NONE = 0,
HW_SDADC_PGA_ENABLE_POSITIVE = 1,
HW_SDADC_PGA_ENABLE_NEGATIVE = 2,
HW_SDADC_PGA_ENABLE_BOTH = 3
} |
| | PGA enabled branch(es) More...
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| |
Enumeration, structure, type and macro definitions.
◆ HW_SDADC_VREF_VOLTAGE_INTERNAL
| #define HW_SDADC_VREF_VOLTAGE_INTERNAL ( 900 ) |
SDADC Reference Voltage level in milliVolt.
Internal reference Voltage level is fixed to 900 millivolt. Do not change!
◆ HW_SDADC_VREF_VOLTAGE_MAX
Macro giving the maximum allowed reference voltage level in millivolt.
◆ hw_sdadc_interrupt_cb
| typedef void(* hw_sdadc_interrupt_cb) (void) |
◆ hw_sdadc_read_cb
| typedef void(* hw_sdadc_read_cb) (void *user_data, uint32_t conv_to_go) |
ADC callback for read function.
◆ HW_SDADC_INPUT
SDADC input selection. Generic names mapping to specific GPIO pins for both positive and negative channels.
- See also
- HW_SDADC_INPUT_CHANNEL
◆ HW_SDADC_INPUT_CHANNEL
SDADC Input Channel.
| Enumerator |
|---|
| HW_SDADC_IN_ADC0_P1_00 | GPIO P1_00
|
| HW_SDADC_IN_ADC1_P1_01 | GPIO P1_01
|
| HW_SDADC_IN_ADC2_P1_02 | GPIO P1_02
|
| HW_SDADC_IN_ADC3_P0_10 | GPIO P0_10
|
| HW_SDADC_IN_ADC4_P1_05 | GPIO P1_05
|
| HW_SDADC_IN_ADC5_P1_06 | GPIO P1_06
|
| HW_SDADC_IN_ADC6_P1_09 | GPIO P1_09
|
| HW_SDADC_IN_ADC7_P1_11 | GPIO P1_11
|
| HW_SDADC_IN_VBAT | VBAT via 4x attenuator, negative side (INN) connected to ground
|
◆ HW_SDADC_INPUT_MODE
SDADC input mode.
| Enumerator |
|---|
| HW_SDADC_INPUT_MODE_DIFFERENTIAL | Differential mode (default)
|
| HW_SDADC_INPUT_MODE_SINGLE_ENDED | Single ended mode. Input selection negative side is ignored
|
◆ HW_SDADC_MODE
SDADC mode (sensor/audio)
| Enumerator |
|---|
| HW_SDADC_MODE_SENSOR | 0: Sensor mode (default)
|
| HW_SDADC_MODE_AUDIO | 1: Audio mode
|
◆ HW_SDADC_OSR
SDADC oversampling rate.
| Enumerator |
|---|
| HW_SDADC_OSR_256 | 0: 256 samples (default)
|
| HW_SDADC_OSR_512 | 1: 512 samples
|
| HW_SDADC_OSR_1024 | 2: 1024 samples
|
| HW_SDADC_OSR_2048 | 3: 2048 samples
|
◆ HW_SDADC_PGA_BIAS
PGA bias configuration.
| Enumerator |
|---|
| HW_SDADC_PGA_BIAS_40 | 0 :0.40 x Ibias
|
| HW_SDADC_PGA_BIAS_44 | 1 :0.44 x Ibias
|
| HW_SDADC_PGA_BIAS_50 | 2 :0.50 x Ibias
|
| HW_SDADC_PGA_BIAS_57 | 3 :0.57 x Ibias
|
| HW_SDADC_PGA_BIAS_66 | 4 :0.66 x Ibias (default)
|
| HW_SDADC_PGA_BIAS_80 | 5 :0.80 x Ibias
|
| HW_SDADC_PGA_BIAS_100 | 6 :1.00 x Ibias
|
| HW_SDADC_PGA_BIAS_133 | 7 :1.33 x Ibias
|
◆ HW_SDADC_PGA_EN
PGA enabled branch(es)
| Enumerator |
|---|
| HW_SDADC_PGA_ENABLE_NONE | 00 : both branches of PGA disabled
|
| HW_SDADC_PGA_ENABLE_POSITIVE | 01 : Positive branch of PGA enabled, Negative branch disabled
|
| HW_SDADC_PGA_ENABLE_NEGATIVE | 10 : Positive branch of PGA disabled, Negative branch enabled
|
| HW_SDADC_PGA_ENABLE_BOTH | 11 : Both branches of PGA enabled
|
◆ HW_SDADC_PGA_GAIN
PGA gain selection.
| Enumerator |
|---|
| HW_SDADC_PGA_GAIN_MINUS_12dB | 0 : -12 dB (default)
|
| HW_SDADC_PGA_GAIN_MINUS_6dB | 1 : -6 dB
|
| HW_SDADC_PGA_GAIN_MINUS_0dB | 2 : 0 dB
|
| HW_SDADC_PGA_GAIN_6dB | 3 : 6 dB
|
| HW_SDADC_PGA_GAIN_12dB | 4 : 12 dB
|
| HW_SDADC_PGA_GAIN_18dB | 5 : 18 dB
|
| HW_SDADC_PGA_GAIN_24dB | 6 : 24 dB
|
| HW_SDADC_PGA_GAIN_30dB | 7 : 30 dB
|
◆ HW_SDADC_PGA_MODE
PGA mode selection.
| Enumerator |
|---|
| HW_SDADC_PGA_MODE_DIFF | 0 : Differential mode (default)
|
| HW_SDADC_PGA_MODE_SE_N | 1 : Use N-branch as single ended mode
|
| HW_SDADC_PGA_MODE_SE_P | 2 : Use P-branch as single ended mode
|
| HW_SDADC_PGA_MODE_RESERVED | 3 : Reserved (do not use)
|
◆ HW_SDADC_VREF_SEL
SDADC VREF selection.
| Enumerator |
|---|
| HW_SDADC_VREF_INTERNAL | VREFN=internal VREFP=internal
|
| HW_SDADC_VREFN_INTERNAL_VREFP_EXTERNAL | VREFN=internal VREFP=external
|
| HW_SDADC_VREFN_EXTERNAL_VREFP_INTERNAL | VREFN=external VREFP=internal
|
| HW_SDADC_VREF_EXTERNAL | VREFN=external VREFP=external
|