CRG_TOP registers (CRG_TOP) More...

#include <DA1459x-00.h>

Data Fields
__IOM uint32_t	CLK_AMBA_REG

__IOM uint32_t	RST_CTRL_REG

__IOM uint32_t	CLK_RADIO_REG

__IOM uint32_t	CLK_CTRL_REG

__IOM uint32_t	CLK_TMR_REG

__IOM uint32_t	CLK_SWITCH2XTAL_REG

__IOM uint32_t	PMU_CTRL_REG

__IOM uint32_t	SYS_CTRL_REG

__IOM uint32_t	SYS_STAT_REG

__IOM uint32_t	CLK_RCLP_REG

__IOM uint32_t	CLK_XTAL32K_REG

__IOM uint32_t	CLK_RC32M_REG

__IOM uint32_t	CLK_RCX_REG

__IOM uint32_t	CLK_RTCDIV_REG

__IOM uint32_t	BANDGAP_REG

__IOM uint32_t	P0_PAD_LATCH_REG

__IOM uint32_t	P0_SET_PAD_LATCH_REG

__IOM uint32_t	P0_RESET_PAD_LATCH_REG

__IOM uint32_t	P1_PAD_LATCH_REG

__IOM uint32_t	P1_SET_PAD_LATCH_REG

__IOM uint32_t	P1_RESET_PAD_LATCH_REG

__IOM uint32_t	POR_PIN_REG

__IOM uint32_t	POR_TIMER_REG

__IOM uint32_t	BIAS_VREF_SEL_REG

__IOM uint32_t	RESET_STAT_REG

__IOM uint32_t	RAM_PWR_CTRL_REG

__IOM uint32_t	SECURE_BOOT_REG

__IOM uint32_t	BOD_CTRL_REG

__IOM uint32_t	DISCHARGE_RAIL_REG

__IOM uint32_t	ANA_STATUS_REG

__IOM uint32_t	POWER_CTRL_REG

__IOM uint32_t	POWER_LEVEL_REG

__IOM uint32_t	HIBERN_CTRL_REG

__IOM uint32_t	PMU_SLEEP_REG

__IOM uint32_t	STARTUP_STATUS_REG

Detailed Description

CRG_TOP registers (CRG_TOP)

Field Documentation

◆ ANA_STATUS_REG

__IOM uint32_t CRG_TOP_Type::ANA_STATUS_REG

(@ 0x000000DC) Analog Signals Status Register

◆ BANDGAP_REG

__IOM uint32_t CRG_TOP_Type::BANDGAP_REG

(@ 0x00000050) bandgap trimming

◆ BIAS_VREF_SEL_REG

__IOM uint32_t CRG_TOP_Type::BIAS_VREF_SEL_REG

(@ 0x000000A4) BIAS_VREF_SEL_REG

◆ BOD_CTRL_REG

__IOM uint32_t CRG_TOP_Type::BOD_CTRL_REG

(@ 0x000000D0) BOD control register

◆ CLK_AMBA_REG

__IOM uint32_t CRG_TOP_Type::CLK_AMBA_REG

< (@ 0x50000000) CRG_TOP Structure
(@ 0x00000000) HCLK, PCLK, divider and clock gates

◆ CLK_CTRL_REG

__IOM uint32_t CRG_TOP_Type::CLK_CTRL_REG

(@ 0x00000014) Clock control register

◆ CLK_RADIO_REG

__IOM uint32_t CRG_TOP_Type::CLK_RADIO_REG

(@ 0x00000010) Radio PLL control register

◆ CLK_RC32M_REG

__IOM uint32_t CRG_TOP_Type::CLK_RC32M_REG

(@ 0x00000044) Fast RC control register

◆ CLK_RCLP_REG

__IOM uint32_t CRG_TOP_Type::CLK_RCLP_REG

(@ 0x0000003C) 32/512 kHz RC oscillator register

◆ CLK_RCX_REG

__IOM uint32_t CRG_TOP_Type::CLK_RCX_REG

(@ 0x00000048) RCX-oscillator control register

◆ CLK_RTCDIV_REG

__IOM uint32_t CRG_TOP_Type::CLK_RTCDIV_REG

(@ 0x0000004C) Divisor for RTC 100 Hz clock

◆ CLK_SWITCH2XTAL_REG

__IOM uint32_t CRG_TOP_Type::CLK_SWITCH2XTAL_REG

(@ 0x0000001C) Switches clock from RC32M to XTAL32M

◆ CLK_TMR_REG

__IOM uint32_t CRG_TOP_Type::CLK_TMR_REG

(@ 0x00000018) Clock control for the timers

◆ CLK_XTAL32K_REG

__IOM uint32_t CRG_TOP_Type::CLK_XTAL32K_REG

(@ 0x00000040) 32 kHz XTAL oscillator register

◆ DISCHARGE_RAIL_REG

__IOM uint32_t CRG_TOP_Type::DISCHARGE_RAIL_REG

(@ 0x000000D4) Immediate rail resetting. There is no LDO/DCDC gating

◆ HIBERN_CTRL_REG

__IOM uint32_t CRG_TOP_Type::HIBERN_CTRL_REG

(@ 0x000000F0) Hibernation control register

◆ P0_PAD_LATCH_REG

__IOM uint32_t CRG_TOP_Type::P0_PAD_LATCH_REG

(@ 0x00000070) Control the state retention of the GPIO ports

◆ P0_RESET_PAD_LATCH_REG

__IOM uint32_t CRG_TOP_Type::P0_RESET_PAD_LATCH_REG

(@ 0x00000078) Control the state retention of the GPIO ports

◆ P0_SET_PAD_LATCH_REG

__IOM uint32_t CRG_TOP_Type::P0_SET_PAD_LATCH_REG

(@ 0x00000074) Control the state retention of the GPIO ports

◆ P1_PAD_LATCH_REG

__IOM uint32_t CRG_TOP_Type::P1_PAD_LATCH_REG

(@ 0x0000007C) Control the state retention of the GPIO ports

◆ P1_RESET_PAD_LATCH_REG

__IOM uint32_t CRG_TOP_Type::P1_RESET_PAD_LATCH_REG

(@ 0x00000084) Control the state retention of the GPIO ports

◆ P1_SET_PAD_LATCH_REG

__IOM uint32_t CRG_TOP_Type::P1_SET_PAD_LATCH_REG

(@ 0x00000080) Control the state retention of the GPIO ports

◆ PMU_CTRL_REG

__IOM uint32_t CRG_TOP_Type::PMU_CTRL_REG

(@ 0x00000020) Power Management Unit control register

◆ PMU_SLEEP_REG

__IOM uint32_t CRG_TOP_Type::PMU_SLEEP_REG

(@ 0x000000F4) Configures the sleep/wake-up strategy

◆ POR_PIN_REG

__IOM uint32_t CRG_TOP_Type::POR_PIN_REG

(@ 0x00000098) Selects a GPIO pin for POR generation

◆ POR_TIMER_REG

__IOM uint32_t CRG_TOP_Type::POR_TIMER_REG

(@ 0x0000009C) Time for POR to happen

◆ POWER_CTRL_REG

__IOM uint32_t CRG_TOP_Type::POWER_CTRL_REG

(@ 0x000000E0) Power control register

◆ POWER_LEVEL_REG

__IOM uint32_t CRG_TOP_Type::POWER_LEVEL_REG

(@ 0x000000E4) Power level settings

◆ RAM_PWR_CTRL_REG

__IOM uint32_t CRG_TOP_Type::RAM_PWR_CTRL_REG

(@ 0x000000C0) Control power state of System RAMS

◆ RESET_STAT_REG

__IOM uint32_t CRG_TOP_Type::RESET_STAT_REG

(@ 0x000000BC) Reset status register

◆ RST_CTRL_REG

__IOM uint32_t CRG_TOP_Type::RST_CTRL_REG

(@ 0x0000000C) Reset control register

◆ SECURE_BOOT_REG

__IOM uint32_t CRG_TOP_Type::SECURE_BOOT_REG

(@ 0x000000CC) Controls secure booting (only ROM software can write)

◆ STARTUP_STATUS_REG

__IOM uint32_t CRG_TOP_Type::STARTUP_STATUS_REG

(@ 0x000000FC) Startup Statemachine Status Register

◆ SYS_CTRL_REG

__IOM uint32_t CRG_TOP_Type::SYS_CTRL_REG

(@ 0x00000024) System Control register

◆ SYS_STAT_REG

__IOM uint32_t CRG_TOP_Type::SYS_STAT_REG

(@ 0x00000028) System status register

The documentation for this struct was generated from the following file:

sdk/bsp/include/DA1459x-00.h

Data Fields