QSPI Flash Memory Controller. More...

Files
file	hw_qspi_v2.h
	Definition of API for the QSPI Low Level Driver.

Data Structures
union	hw_qspi_data_t
	This union is used in order to allow different size access when reading/writing to QSPIC_READDATA_REG, QSPIC_WRITEDATA_REG, QSPIC_DUMMYDATA_REG because. More...

struct	hw_qspi_config_t
	QSPIC configuration structure. More...

struct	hw_qspi_read_instr_config_t
	Read instruction configuration structure (auto access mode) More...

struct	hw_qspi_erase_instr_config_t
	QSPIC Erase instruction configuration structure (auto access mode) More...

struct	hw_qspi_read_status_instr_config_t
	QSPIC read status instruction configuration structure (auto access mode) More...

struct	hw_qspi_write_enable_instr_config_t
	QSPIC write enable instruction configuration structure (auto access mode) More...

struct	hw_qspi_page_program_instr_config_t
	QSPIC Page Program instruction configuration structure (manual access mode) More...

struct	hw_qspi_suspend_resume_instr_config_t
	QSPIC Erase suspend/resume instruction structure (auto access mode) More...

Macros
#define	HW_QSPIC_REG_GETF(id, reg, field)
	Get the value of a field of a QSPIC register. More...

#define	HW_QSPIC_REG_SETF(id, reg, field, new_val)
	Set the value of a field of a QSPIC register. More...

#define	HW_QSPIC_REG_SET_BIT(id, reg, field) QSPIBA(id)->QSPIC_##reg##_REG \|= (1 << QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)
	Set a bit of a QSPIC register. More...

#define	HW_QSPIC_REG_CLR_BIT(id, reg, field) QSPIBA(id)->QSPIC_##reg##_REG &= ~QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk
	Clear a bit of a QSPIC register. More...

Typedefs
typedef void *	HW_QSPIC_ID
	QSPI Controller ID. More...

Enumerations
enum	HW_QSPI_ACCESS_MODE { HW_QSPI_ACCESS_MODE_MANUAL = 0, HW_QSPI_ACCESS_MODE_AUTO = 1 }
	QSPIC memory access mode. More...

enum	HW_QSPI_ADDR_SIZE { HW_QSPI_ADDR_SIZE_24 = 0, HW_QSPI_ADDR_SIZE_32 = 1 }
	QSPIC memory address size. More...

enum	HW_QSPI_BUS_MODE { HW_QSPI_BUS_MODE_SINGLE = 0, HW_QSPI_BUS_MODE_DUAL = 1, HW_QSPI_BUS_MODE_QUAD = 2 }
	QSPIC bus mode. More...

enum	HW_QSPI_BUS_STATUS { HW_QSPI_BUS_STATUS_IDLE = 0, HW_QSPI_BUS_STATUS_ACTIVE = 1 }
	QSPIC Bus status. More...

enum	HW_QSPI_BUSY_LEVEL { HW_QSPI_BUSY_LEVEL_LOW = 0, HW_QSPI_BUSY_LEVEL_HIGH = 1 }
	QSPIC device busy status setting. More...

enum	HW_QSPI_CLK_DIV { HW_QSPI_CLK_DIV_1 = 0, HW_QSPI_CLK_DIV_2 = 1, HW_QSPI_CLK_DIV_4 = 2, HW_QSPI_CLK_DIV_8 = 3 }
	QSPIC clock divider. More...

enum	HW_QSPI_CLK_MODE { HW_QSPI_CLK_MODE_LOW = 0, HW_QSPI_CLK_MODE_HIGH = 1 }
	QSPIC clock mode. More...

enum	HW_QSPI_CONTINUOUS_MODE { HW_QSPI_CONTINUOUS_MODE_DISABLE = 0, HW_QSPI_CONTINUOUS_MODE_ENABLE = 1 }
	QSPIC continuous mode. More...

enum	HW_QSPI_DRIVE_CURRENT { HW_QSPI_DRIVE_CURRENT_4 = 0, HW_QSPI_DRIVE_CURRENT_8 = 1, HW_QSPI_DRIVE_CURRENT_12 = 2, HW_QSPI_DRIVE_CURRENT_16 = 3 }
	QSPIC pads drive current strength. More...

enum	HW_QSPI_EXTRA_BYTE { HW_QSPI_EXTRA_BYTE_DISABLE = 0, HW_QSPI_EXTRA_BYTE_ENABLE = 1 }
	QSPIC extra byte setting in auto access mode. More...

enum	HW_QSPI_EXTRA_BYTE_HALF { HW_QSPI_EXTRA_BYTE_HALF_DISABLE = 0, HW_QSPI_EXTRA_BYTE_HALF_ENABLE = 1 }
	QSPIC extra byte half setting in auto access mode. More...

enum	HW_QSPI_HREADY_MODE { HW_QSPI_HREADY_MODE_WAIT = 0, HW_QSPI_HREADY_MODE_NO_WAIT = 1 }
	QSPIC HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers. More...

enum	HW_QSPI_IO_DIR { HW_QSPI_IO_DIR_AUTO_SEL = 0, HW_QSPI_IO_DIR_OUTPUT = 1 }
	QSPIC pad direction. More...

enum	HW_QSPI_IO_VALUE { HW_QSPI_IO_VALUE_LOW = 0, HW_QSPI_IO_VALUE_HIGH = 1 }
	QSPIC IO2/IO3 pad value. More...

enum	HW_QSPI_READ_PIPE { HW_QSPI_READ_PIPE_DISABLE = 0, HW_QSPI_READ_PIPE_ENABLE = 1 }
	QSPIC read pipe setting. More...

enum	HW_QSPI_READ_PIPE_DELAY { HW_QSPI_READ_PIPE_DELAY_0 = 0, HW_QSPI_READ_PIPE_DELAY_1 = 1, HW_QSPI_READ_PIPE_DELAY_2 = 2, HW_QSPI_READ_PIPE_DELAY_3 = 3, HW_QSPI_READ_PIPE_DELAY_4 = 4, HW_QSPI_READ_PIPE_DELAY_5 = 5, HW_QSPI_READ_PIPE_DELAY_6 = 6, HW_QSPI_READ_PIPE_DELAY_7 = 7 }
	QSPIC Read pipe clock delay in relation to the falling edge of QSPI_SCK. More...

enum	HW_QSPI_SAMPLING_EDGE { HW_QSPI_SAMPLING_EDGE_POS = 0, HW_QSPI_SAMPLING_EDGE_NEG = 1 }
	QSPIC clock edge setting for the sampling of the incoming data when the read pipe is disabled. More...

enum	HW_QSPI_SLEW_RATE { HW_QSPI_SLEW_RATE_0 = 0, HW_QSPI_SLEW_RATE_1 = 1, HW_QSPI_SLEW_RATE_2 = 2, HW_QSPI_SLEW_RATE_3 = 3 }
	QSPIC pads slew rate. More...

enum	HW_QSPI_ERASE_STATUS { HW_QSPI_ERASE_STATUS_NO = 0, HW_QSPI_ERASE_STATUS_PENDING = 1, HW_QSPI_ERASE_STATUS_RUNNING = 2, HW_QSPI_ERASE_STATUS_SUSPENDED = 3, HW_QSPI_ERASE_STATUS_FINISHING = 4 }
	The status of sector/block erasing. More...

Functions
__STATIC_FORCEINLINE void	hw_qspi_clock_enable (HW_QSPIC_ID id)
	Enable QSPI controller clock. More...

__STATIC_FORCEINLINE void	hw_qspi_clock_disable (HW_QSPIC_ID id)
	Disable QSPI controller clock. More...

__STATIC_FORCEINLINE void	hw_qspi_cs_enable (HW_QSPIC_ID id)
	Enable CS on QSPI bus in manual access mode. More...

__STATIC_FORCEINLINE void	hw_qspi_cs_disable (HW_QSPIC_ID id)
	Disable CS on QSPI bus in manual access mode. More...

__STATIC_FORCEINLINE HW_QSPI_BUS_STATUS	hw_qspi_get_bus_status (HW_QSPIC_ID id)
	Get QSPIC Bus status. More...

__STATIC_FORCEINLINE void	hw_qspi_set_div (HW_QSPIC_ID id, HW_QSPI_CLK_DIV div)
	Set QSPIC clock divider. More...

__STATIC_FORCEINLINE HW_QSPI_CLK_DIV	hw_qspi_get_div (HW_QSPIC_ID id)
	Get QSPIC clock divider. More...

__STATIC_FORCEINLINE void	hw_qspi_set_manual_access_bus_mode (HW_QSPIC_ID id, HW_QSPI_BUS_MODE bus_mode)
	Set QSPIC bus mode in manual access mode. More...

__STATIC_FORCEINLINE void	hw_qspi_set_access_mode (HW_QSPIC_ID id, HW_QSPI_ACCESS_MODE access_mode)
	Set QSPIC access mode. More...

__STATIC_FORCEINLINE HW_QSPI_ACCESS_MODE	hw_qspi_get_access_mode (HW_QSPIC_ID id)
	Get QSPIC access mode. More...

__STATIC_FORCEINLINE void	hw_qspi_set_clock_mode (HW_QSPIC_ID id, HW_QSPI_CLK_MODE clk_mode)
	Set QSPIC clock mode. More...

__STATIC_FORCEINLINE HW_QSPI_CLK_MODE	hw_qspi_get_clock_mode (HW_QSPIC_ID id)
	Get QSPIC clock mode. More...

__STATIC_FORCEINLINE void	hw_qspi_set_io2_direction (HW_QSPIC_ID id, HW_QSPI_IO_DIR dir)
	Set QSPI_IO2 direction. More...

__STATIC_FORCEINLINE HW_QSPI_IO_DIR	hw_qspi_get_io2_direction (HW_QSPIC_ID id)
	Get QSPI_IO2 direction. More...

__STATIC_FORCEINLINE void	hw_qspi_set_io3_direction (HW_QSPIC_ID id, HW_QSPI_IO_DIR dir)
	Set QSPI_IO3 direction. More...

__STATIC_FORCEINLINE HW_QSPI_IO_DIR	hw_qspi_get_io3_direction (HW_QSPIC_ID id)
	Get QSPI_IO3 direction. More...

__STATIC_FORCEINLINE void	hw_qspi_set_io2_value (HW_QSPIC_ID id, HW_QSPI_IO_VALUE value)
	Set the value of QSPI_IO2 pad when QSPI_IO2 direction is output. More...

__STATIC_FORCEINLINE HW_QSPI_IO_VALUE	hw_qspi_get_io2_value (HW_QSPIC_ID id)
	Get the value of QSPI_IO2 pad when QSPI_IO2 direction is output. More...

__STATIC_FORCEINLINE void	hw_qspi_set_io3_value (HW_QSPIC_ID id, HW_QSPI_IO_VALUE value)
	Set the value of QSPI_IO3 pad when QSPI_IO3 direction is output. More...

__STATIC_FORCEINLINE HW_QSPI_IO_VALUE	hw_qspi_get_io3_value (HW_QSPIC_ID id)
	Get the value of QSPI_IO3 pad when QSPI_IO3 direction is output. More...

__STATIC_FORCEINLINE void	hw_qspi_set_io (HW_QSPIC_ID id, HW_QSPI_BUS_MODE bus_mode)
	Set the direction and the level of QSPIC IOs based on the Bus Mode. More...

__STATIC_FORCEINLINE void	hw_qspi_set_hready_mode (HW_QSPIC_ID id, HW_QSPI_HREADY_MODE mode)
	Set QSPIC HReady signal mode. More...

__STATIC_FORCEINLINE HW_QSPI_HREADY_MODE	hw_qspi_get_hready_mode (HW_QSPIC_ID id)
	Get QSPIC HReady signal mode. More...

__STATIC_FORCEINLINE void	hw_qspi_set_read_sampling_edge (HW_QSPIC_ID id, HW_QSPI_SAMPLING_EDGE edge)
	Set QSPIC read sampling edge. More...

__STATIC_FORCEINLINE HW_QSPI_SAMPLING_EDGE	hw_qspi_get_read_sampling_edge (HW_QSPIC_ID id)
	Get QSPIC read sampling edge. More...

__STATIC_FORCEINLINE void	hw_qspi_set_read_pipe (HW_QSPIC_ID id, HW_QSPI_READ_PIPE read_pipe)
	Set QSPIC data read pipe status. More...

__STATIC_FORCEINLINE HW_QSPI_READ_PIPE	hw_qspi_get_read_pipe (HW_QSPIC_ID id)
	Get QSPIC read pipe status. More...

__STATIC_FORCEINLINE void	hw_qspi_set_read_pipe_clock_delay (HW_QSPIC_ID id, HW_QSPI_READ_PIPE_DELAY delay)
	Set the QSPIC read pipe clock delay. More...

__STATIC_FORCEINLINE HW_QSPI_READ_PIPE_DELAY	hw_qspi_get_read_pipe_clock_delay (HW_QSPIC_ID id)
	Get QSPIC read pipe clock delay. More...

__STATIC_FORCEINLINE void	hw_qspi_set_address_size (HW_QSPIC_ID id, HW_QSPI_ADDR_SIZE addr_size)
	Set QSPIC address size. More...

__STATIC_FORCEINLINE HW_QSPI_ADDR_SIZE	hw_qspi_get_address_size (HW_QSPIC_ID id)
	Get QSPIC address size. More...

__STATIC_FORCEINLINE void	hw_qspi_set_slew_rate (HW_QSPIC_ID id, HW_QSPI_SLEW_RATE slew_rate)
	Set slew rate of QSPIC pads. More...

__STATIC_FORCEINLINE HW_QSPI_SLEW_RATE	hw_qspi_get_slew_rate (HW_QSPIC_ID id)
	Get slew rate of QSPIC pads. More...

__STATIC_FORCEINLINE void	hw_qspi_set_drive_current (HW_QSPIC_ID id, HW_QSPI_DRIVE_CURRENT drive_current)
	Set drive current of QSPIC pads. More...

__STATIC_FORCEINLINE HW_QSPI_DRIVE_CURRENT	hw_qspi_get_drive_current (HW_QSPIC_ID id)
	Get drive current of QSPIC pads. More...

__STATIC_FORCEINLINE void	hw_qspi_set_dummy_bytes (HW_QSPIC_ID id, uint8_t dummy_bytes)
	Set the number of dummy bytes in auto access mode. More...

__STATIC_FORCEINLINE uint8_t	hw_qspi_get_dummy_bytes (HW_QSPIC_ID id)
	Get the number of dummy bytes in auto access mode. More...

__STATIC_FORCEINLINE void	hw_qspi_set_read_cs_idle_delay (HW_QSPIC_ID id, uint16_t cs_idle_delay_nsec, uint32_t clk_freq_hz)
	Set the minimum number of clocks cycles that CS stays in idle mode, between two consecutive read commands. More...

__STATIC_FORCEINLINE void	hw_qspi_set_erase_cs_idle_delay (HW_QSPIC_ID id, uint16_t cs_idle_delay_nsec, uint32_t clk_freq_hz)
	Set the minimum number of clocks cycles that CS stays in idle mode, between a write enable, erase, erase suspend and erase resume instruction and the next consecutive command. More...

__STATIC_FORCEINLINE uint32_t	hw_qspi_read32 (HW_QSPIC_ID id)
	Generate 32 bits data transfer from the external device to the QSPIC (manual mode) More...

__STATIC_FORCEINLINE uint16_t	hw_qspi_read16 (HW_QSPIC_ID id)
	Generate 16 bits data transfer from the external device to the QSPIC (manual mode) More...

__STATIC_FORCEINLINE uint8_t	hw_qspi_read8 (HW_QSPIC_ID id)
	Generate 8 bits data transfer from the external device to the QSPIC (manual mode) More...

__STATIC_FORCEINLINE void	hw_qspi_write32 (HW_QSPIC_ID id, uint32_t data)
	Generate 32 bits data transfer from the QSPIC to the external device (manual mode) More...

__STATIC_FORCEINLINE void	hw_qspi_write16 (HW_QSPIC_ID id, uint16_t data)
	Generate 16 bits data transfer from the QSPIC to the external device (manual mode) More...

__STATIC_FORCEINLINE void	hw_qspi_write8 (HW_QSPIC_ID id, uint8_t data)
	Generate 8 bits data transfer from the QSPIC to the external device (manual mode) More...

__STATIC_FORCEINLINE void	hw_qspi_dummy32 (HW_QSPIC_ID id)
	Generate clock pulses on the SPI bus for a 32-bit transfer. More...

__STATIC_FORCEINLINE void	hw_qspi_dummy16 (HW_QSPIC_ID id)
	Generate clock pulses on the SPI bus for a 16-bit transfer. More...

__STATIC_FORCEINLINE void	hw_qspi_dummy8 (HW_QSPIC_ID id)
	Generate clock pulses on the SPI bus for an 8-bit transfer. More...

__RETAINED_CODE void	hw_qspi_init (HW_QSPIC_ID id, const hw_qspi_config_t *cfg)
	Initialize the QSPI controller (QSPIC) More...

__STATIC_FORCEINLINE void	hw_qspi_read_instr_init (HW_QSPIC_ID id, const hw_qspi_read_instr_config_t *cfg, uint8_t dummy_bytes, uint32_t sys_clk_freq_hz)
	Initialize the read instruction of the QSPIC. More...

__STATIC_FORCEINLINE void	hw_qspi_erase_instr_init (HW_QSPIC_ID id, const hw_qspi_erase_instr_config_t *cfg, uint32_t sys_clk_freq_hz)
	Initialize the erase instruction of the QSPIC. More...

__STATIC_FORCEINLINE void	hw_qspi_read_status_instr_init (HW_QSPIC_ID id, const hw_qspi_read_status_instr_config_t *cfg, uint32_t sys_clk_freq_hz)
	Initialize the read status register instruction of the QSPIC. More...

__STATIC_FORCEINLINE void	hw_qspi_write_enable_instr_init (HW_QSPIC_ID id, const hw_qspi_write_enable_instr_config_t *cfg)
	Initialize the write enable instruction of the QSPIC. More...

__STATIC_FORCEINLINE void	hw_qspi_suspend_resume_instr_init (HW_QSPIC_ID id, const hw_qspi_suspend_resume_instr_config_t *cfg)
	Initialize the program and erase suspend/resume instruction of the QSPIC. More...

__STATIC_FORCEINLINE void	hw_qspi_exit_continuous_mode_instr_init (HW_QSPIC_ID id, HW_QSPI_CONTINUOUS_MODE mode, HW_QSPI_ADDR_SIZE addr_size)
	Initialize the exit from continuous mode instruction of the QSPIC. More...

__STATIC_FORCEINLINE void	hw_qspi_set_erase_address (HW_QSPIC_ID id, uint32_t erase_addr)
	Set the address of the block/sector that is requested to be erased. More...

__STATIC_FORCEINLINE void	hw_qspi_trigger_erase (HW_QSPIC_ID id)
	Trigger erase block/sector. More...

__STATIC_FORCEINLINE HW_QSPI_ERASE_STATUS	hw_qspi_get_erase_status (HW_QSPIC_ID id)
	Get erase status. More...

__RETAINED_CODE void	hw_qspi_erase_block (HW_QSPIC_ID id, uint32_t addr)
	Erase block/sector of flash memory. More...

__STATIC_FORCEINLINE void	hw_qspi_set_extra_byte (HW_QSPIC_ID id, uint8_t extra_byte, HW_QSPI_BUS_MODE bus_mode, bool half_disable_out)
	Set an extra byte to use with read instructions. More...

__STATIC_FORCEINLINE void	hw_qspi_exit_continuous_mode_sequence_enable (HW_QSPIC_ID id)
	Enable the 'exit from continuous read mode' sequence in automode. More...

__STATIC_FORCEINLINE void	hw_qspi_exit_continuous_mode_sequence_disable (HW_QSPIC_ID id)
	Disable the 'exit from continuous read mode' sequence in automode. More...

Detailed Description

QSPI Flash Memory Controller.

Macro Definition Documentation

◆ HW_QSPIC_REG_CLR_BIT

#define HW_QSPIC_REG_CLR_BIT	(	id,
		reg,
		field
	)	QSPIBA(id)->QSPIC_##reg##_REG &= ~QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk

Clear a bit of a QSPIC register.

Parameters

[in]	id	QSPI controller id
[in]	reg	is the register to access
[in]	field	is the register bit to clear

◆ HW_QSPIC_REG_GETF

#define HW_QSPIC_REG_GETF	(	id,
		reg,
		field
	)

Value:

((QSPIBA(id)->QSPIC_##reg##_REG & QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) >> \

QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)

Get the value of a field of a QSPIC register.

Parameters

[in]	id	QSPI controller id
[in]	reg	is the register to access
[in]	field	is the register field to write

Returns: the value of the register field

◆ HW_QSPIC_REG_SET_BIT

#define HW_QSPIC_REG_SET_BIT	(	id,
		reg,
		field
	)	QSPIBA(id)->QSPIC_##reg##_REG \|= (1 << QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)

Set a bit of a QSPIC register.

Parameters

[in]	id	QSPI controller id
[in]	reg	is the register to access
[in]	field	is the register bit to set

◆ HW_QSPIC_REG_SETF

#define HW_QSPIC_REG_SETF	(	id,
		reg,
		field,
		new_val
	)

Value:

QSPIBA(id)->QSPIC_##reg##_REG = ((QSPIBA(id)->QSPIC_##reg##_REG & \
                                         ~QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk) | \
                                        (QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Msk & \
                                         ((new_val) << QSPIC_QSPIC_##reg##_REG_##QSPIC_##field##_Pos)))

Set the value of a field of a QSPIC register.

Parameters

[in]	id	QSPI controller id
[in]	reg	is the register to access
[in]	field	is the register field to write
[in]	new_val	is the value to write

Typedef Documentation

◆ HW_QSPIC_ID

typedef void* HW_QSPIC_ID

QSPI Controller ID.

Enumeration Type Documentation

◆ HW_QSPI_ACCESS_MODE

enum HW_QSPI_ACCESS_MODE

QSPIC memory access mode.

Enumerator
HW_QSPI_ACCESS_MODE_MANUAL	Manual Mode is selected
HW_QSPI_ACCESS_MODE_AUTO	Auto Mode is selected

◆ HW_QSPI_ADDR_SIZE

enum HW_QSPI_ADDR_SIZE

QSPIC memory address size.

Enumerator
HW_QSPI_ADDR_SIZE_24	24 bits address
HW_QSPI_ADDR_SIZE_32	32 bits address

◆ HW_QSPI_BUS_MODE

enum HW_QSPI_BUS_MODE

QSPIC bus mode.

Enumerator
HW_QSPI_BUS_MODE_SINGLE	Bus mode in single mode
HW_QSPI_BUS_MODE_DUAL	Bus mode in dual mode
HW_QSPI_BUS_MODE_QUAD	Bus mode in quad mode

◆ HW_QSPI_BUS_STATUS

enum HW_QSPI_BUS_STATUS

QSPIC Bus status.

Enumerator
HW_QSPI_BUS_STATUS_IDLE	The SPI Bus is idle
HW_QSPI_BUS_STATUS_ACTIVE	The SPI Bus is active. Read data, write data or dummy data activity is in progress.

◆ HW_QSPI_BUSY_LEVEL

enum HW_QSPI_BUSY_LEVEL

QSPIC device busy status setting.

Enumerator
HW_QSPI_BUSY_LEVEL_LOW	The QSPI device is busy when the pin level bit is low
HW_QSPI_BUSY_LEVEL_HIGH	The QSPI device is busy when the pin level bit is high

◆ HW_QSPI_CLK_DIV

enum HW_QSPI_CLK_DIV

QSPIC clock divider.

Enumerator
HW_QSPI_CLK_DIV_1	divide by 1
HW_QSPI_CLK_DIV_2	divide by 2
HW_QSPI_CLK_DIV_4	divide by 4
HW_QSPI_CLK_DIV_8	divide by 8

◆ HW_QSPI_CLK_MODE

enum HW_QSPI_CLK_MODE

QSPIC clock mode.

Enumerator
HW_QSPI_CLK_MODE_LOW	Mode 0: QSPI_SCK is low when QSPI_CS is high.
HW_QSPI_CLK_MODE_HIGH	Mode 3: QSPI_SCK is high when QSPI_CS is high.

◆ HW_QSPI_CONTINUOUS_MODE

enum HW_QSPI_CONTINUOUS_MODE

QSPIC continuous mode.

Enumerator
HW_QSPI_CONTINUOUS_MODE_DISABLE	Disable continuous mode of operation
HW_QSPI_CONTINUOUS_MODE_ENABLE	Enable continuous mode of operation

◆ HW_QSPI_DRIVE_CURRENT

enum HW_QSPI_DRIVE_CURRENT

QSPIC pads drive current strength.

Enumerator
HW_QSPI_DRIVE_CURRENT_4	4 mA
HW_QSPI_DRIVE_CURRENT_8	8 mA
HW_QSPI_DRIVE_CURRENT_12	12 mA
HW_QSPI_DRIVE_CURRENT_16	16 mA

◆ HW_QSPI_ERASE_STATUS

enum HW_QSPI_ERASE_STATUS

The status of sector/block erasing.

Enumerator
HW_QSPI_ERASE_STATUS_NO	no erase
HW_QSPI_ERASE_STATUS_PENDING	pending erase request
HW_QSPI_ERASE_STATUS_RUNNING	erase procedure is running
HW_QSPI_ERASE_STATUS_SUSPENDED	suspended erase procedure
HW_QSPI_ERASE_STATUS_FINISHING	finishing the erase procedure

◆ HW_QSPI_EXTRA_BYTE

enum HW_QSPI_EXTRA_BYTE

QSPIC extra byte setting in auto access mode.

Enumerator
HW_QSPI_EXTRA_BYTE_DISABLE	Disable extra byte phase
HW_QSPI_EXTRA_BYTE_ENABLE	Enable extra byte phase

◆ HW_QSPI_EXTRA_BYTE_HALF

enum HW_QSPI_EXTRA_BYTE_HALF

QSPIC extra byte half setting in auto access mode.

Note: This setting is out of scope if the extra byte is disabled.

Enumerator
HW_QSPI_EXTRA_BYTE_HALF_DISABLE	Transmit the complete extra byte
HW_QSPI_EXTRA_BYTE_HALF_ENABLE	The output switches to Hi-Z during the transmission of the low nibble of the extra byte

◆ HW_QSPI_HREADY_MODE

enum HW_QSPI_HREADY_MODE

QSPIC HREADY signal mode when accessing the WRITEDATA, READDATA and DUMMYDATA registers.

Note: This configuration is useful when the frequency of the QSPI clock is much lower than the clock of the AMBA bus, in order to avoid locking the AMBA bus for a long time. When is set to HW_QSPI_HREADY_MODE_WAIT there is no need to check the QSPIC_BUSY for detecting completion of the requested access.

Enumerator
HW_QSPI_HREADY_MODE_WAIT	Adds wait states via hready signal when accessing the QSPIC_WRITEDATA, QSPIC_READDATA and QSPIC_DUMMYDATA registers.
HW_QSPI_HREADY_MODE_NO_WAIT	Don't add wait states via the HREADY signal

◆ HW_QSPI_IO_DIR

enum HW_QSPI_IO_DIR

QSPIC pad direction.

Note: Set this enum to HW_QSPI_IO_DIR_OUTPUT only when the SPI or Dual SPI mode is enabled in order to control the /WP signal. When the Quad SPI bus mode is enabled this setting MUST be set to HW_QSPI_IO_DIR_AUTO_SEL.

Enumerator
HW_QSPI_IO_DIR_AUTO_SEL	The QSPI pad is determined by the controller.
HW_QSPI_IO_DIR_OUTPUT	The QSPI pad is output

◆ HW_QSPI_IO_VALUE

enum HW_QSPI_IO_VALUE

QSPIC IO2/IO3 pad value.

Note: Use this enum to set the value of QSPI_IOx when the corresponding HW_QSPI_IO_DIR is set to HW_QSPI_IO_DIR_OUTPUT.

Enumerator
HW_QSPI_IO_VALUE_LOW	Set the level of the QSPI bus IO low
HW_QSPI_IO_VALUE_HIGH	Set the level of the QSPI bus IO high

◆ HW_QSPI_READ_PIPE

enum HW_QSPI_READ_PIPE

QSPIC read pipe setting.

Note: When read pipe is disabled the sampling clock is determined by HW_QSPI_SAMPLING_EDGE otherwise by HW_QSPI_READ_PIPE_DELAY.

Enumerator
HW_QSPI_READ_PIPE_DISABLE	Disable read pipe delay
HW_QSPI_READ_PIPE_ENABLE	Enable read pipe delay

◆ HW_QSPI_READ_PIPE_DELAY

enum HW_QSPI_READ_PIPE_DELAY

QSPIC Read pipe clock delay in relation to the falling edge of QSPI_SCK.

Note: The read pipe delay should be set based on the voltage level of the power rail V12. Recommended values: V12 = 0.9V: HW_QSPI_READ_PIPE_DELAY_0 V12 = 1.2V: HW_QSPI_READ_PIPE_DELAY_7

Enumerator
HW_QSPI_READ_PIPE_DELAY_0	Set read pipe delay to 0
HW_QSPI_READ_PIPE_DELAY_1	Set read pipe delay to 1
HW_QSPI_READ_PIPE_DELAY_2	Set read pipe delay to 2
HW_QSPI_READ_PIPE_DELAY_3	Set read pipe delay to 3
HW_QSPI_READ_PIPE_DELAY_4	Set read pipe delay to 4
HW_QSPI_READ_PIPE_DELAY_5	Set read pipe delay to 5
HW_QSPI_READ_PIPE_DELAY_6	Set read pipe delay to 6
HW_QSPI_READ_PIPE_DELAY_7	Set read pipe delay to 7

◆ HW_QSPI_SAMPLING_EDGE

enum HW_QSPI_SAMPLING_EDGE

QSPIC clock edge setting for the sampling of the incoming data when the read pipe is disabled.

Enumerator
HW_QSPI_SAMPLING_EDGE_POS	The incoming data sampling is triggered by the positive edge of QSPIC clock signal
HW_QSPI_SAMPLING_EDGE_NEG	The incoming data sampling is triggered by the negative edge of QSPIC clock signal

◆ HW_QSPI_SLEW_RATE

enum HW_QSPI_SLEW_RATE

QSPIC pads slew rate.

Enumerator
HW_QSPI_SLEW_RATE_0	Rise = 1.7 V/ns, Fall = 1.9 V/ns (weak)
HW_QSPI_SLEW_RATE_1	Rise = 2.0 V/ns, Fall = 2.3 V/ns
HW_QSPI_SLEW_RATE_2	Rise = 2.3 V/ns, Fall = 2.6 V/ns
HW_QSPI_SLEW_RATE_3	Rise = 2.4 V/ns, Fall = 2.7 V/ns (strong)

[in] id QSPI controller id

Note: During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus can be 1, 2 or 4 for Single, Dual, Quad SPI mode respectively.

◆ hw_qspi_dummy32()

__STATIC_FORCEINLINE void hw_qspi_dummy32 ( HW_QSPIC_ID id )

Generate clock pulses on the SPI bus for a 32-bit transfer.

Parameters

[in] id QSPI controller id

Note: During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus can be 1, 2 or 4 for Single, Dual, Quad SPI bus mode respectively.

◆ hw_qspi_dummy8()

__STATIC_FORCEINLINE void hw_qspi_dummy8 ( HW_QSPIC_ID id )

Generate clock pulses on the SPI bus for an 8-bit transfer.

Parameters

[in] id QSPI controller id

Note: During the last clock of this activity in the SPI bus, the QSPI_IOx data pads are in hi-z state. The number of generated pulses is equal to: (size of AHB bus access) / (size of SPI bus). The size of SPI bus can be 1, 2 or 4 for Single, Dual, Quad SPI mode respectively.

◆ hw_qspi_erase_block()

__RETAINED_CODE void hw_qspi_erase_block	(	HW_QSPIC_ID	id,
		uint32_t	addr
	)

Erase block/sector of flash memory.

Note: Before erasing the flash memory, it is mandatory to set up the erase instructions first by calling hw_qspi_erase_instr_init().; Call hw_qspi_get_erase_status() to check whether the erase operation has finished.; Before switching the QSPI controller to manual mode check that hw_qspi_get_erase_status() == HW_QSPI_ERASE_STATUS_NO.

Parameters

[in]	id	QSPI controller id
[in]	addr	memory address of the block/sector to be erased

See also: hw_qspi_erase_instr_init; hw_qspi_get_erase_status

◆ hw_qspi_erase_instr_init()

__STATIC_FORCEINLINE void hw_qspi_erase_instr_init	(	HW_QSPIC_ID	id,
		const hw_qspi_erase_instr_config_t *	cfg,
		uint32_t	sys_clk_freq_hz
	)

Initialize the erase instruction of the QSPIC.

Parameters

[in]	id	QSPI controller id
[in]	cfg	Pointer to configuration structure of the erase instruction.
[in]	sys_clk_freq_hz	The system clock frequency in Hz, which is used to calculate the minimum QSPI bus clock cycles that the Chip Select (CS) signal remain must high between an erase instruction and the next consecutive instruction.

See also: hw_qspi_erase_instr_config_t

◆ hw_qspi_exit_continuous_mode_instr_init()

__STATIC_FORCEINLINE void hw_qspi_exit_continuous_mode_instr_init	(	HW_QSPIC_ID	id,
		HW_QSPI_CONTINUOUS_MODE	mode,
		HW_QSPI_ADDR_SIZE	addr_size
	)

Initialize the exit from continuous mode instruction of the QSPIC.

Parameters

[in]	id	QSPI controller id
[in]	mode	Enable/Disable continuous mode of operation.
[in]	addr_size	The address size which determines the length of the sequence to exit the connected memory from continuous mode of operation. If the address size is 32 bits, the length of the command sequence is 2 bytes. Otherwise, for address size 24 bits only 1 byte is required.

See also: HW_QSPI_CONTINUOUS_MODE; HW_QSPI_ADDR_SIZE

◆ hw_qspi_exit_continuous_mode_sequence_disable()

__STATIC_FORCEINLINE void hw_qspi_exit_continuous_mode_sequence_disable ( HW_QSPIC_ID id )

Disable the 'exit from continuous read mode' sequence in automode.

Parameters

[in] id QSPI controller id

◆ hw_qspi_exit_continuous_mode_sequence_enable()

__STATIC_FORCEINLINE void hw_qspi_exit_continuous_mode_sequence_enable ( HW_QSPIC_ID id )

Enable the 'exit from continuous read mode' sequence in automode.

Parameters

[in] id QSPI controller id

◆ hw_qspi_get_access_mode()

__STATIC_FORCEINLINE HW_QSPI_ACCESS_MODE hw_qspi_get_access_mode ( HW_QSPIC_ID id )

Get QSPIC access mode.

Parameters

[in] id QSPI controller id

Returns: QSPIC access mode

See also: HW_QSPI_ACCESS_MODE

◆ hw_qspi_get_address_size()

__STATIC_FORCEINLINE HW_QSPI_ADDR_SIZE hw_qspi_get_address_size ( HW_QSPIC_ID id )

Get QSPIC address size.

Parameters

[in] id QSPI controller id

Returns: QSPIC address size

See also: HW_QSPI_ADDR_SIZE

◆ hw_qspi_get_bus_status()

__STATIC_FORCEINLINE HW_QSPI_BUS_STATUS hw_qspi_get_bus_status ( HW_QSPIC_ID id )

Get QSPIC Bus status.

Parameters

[in] id QSPI controller id

See also: HW_QSPI_BUS_STATUS

◆ hw_qspi_get_clock_mode()

__STATIC_FORCEINLINE HW_QSPI_CLK_MODE hw_qspi_get_clock_mode ( HW_QSPIC_ID id )

Get QSPIC clock mode.

Parameters

[in] id QSPI controller id

Returns: QSPIC clock mode

See also: HW_QSPI_CLK_MODE

◆ hw_qspi_get_div()

__STATIC_FORCEINLINE HW_QSPI_CLK_DIV hw_qspi_get_div ( HW_QSPIC_ID id )

Get QSPIC clock divider.

Parameters

[in] id QSPI controller id

Returns: QSPIC clock divider setting

See also: HW_QSPI_CLK_DIV

◆ hw_qspi_get_drive_current()

__STATIC_FORCEINLINE HW_QSPI_DRIVE_CURRENT hw_qspi_get_drive_current ( HW_QSPIC_ID id )

Get drive current of QSPIC pads.

Parameters

[in] id QSPI controller id

Returns: Drive current of QSPIC pads

See also: HW_QSPI_DRIVE_CURRENT

◆ hw_qspi_get_dummy_bytes()

__STATIC_FORCEINLINE uint8_t hw_qspi_get_dummy_bytes ( HW_QSPIC_ID id )

Get the number of dummy bytes in auto access mode.

Parameters

[in] id QSPI controller id

Returns: Number of dummy bytes (0 - 4)

◆ hw_qspi_get_erase_status()

__STATIC_FORCEINLINE HW_QSPI_ERASE_STATUS hw_qspi_get_erase_status ( HW_QSPIC_ID id )

Get erase status.

Parameters

[in] id QSPI controller id

Returns: The status of sector/block erasing

See also: HW_QSPI_ERASE_STATUS

◆ hw_qspi_get_hready_mode()

__STATIC_FORCEINLINE HW_QSPI_HREADY_MODE hw_qspi_get_hready_mode ( HW_QSPIC_ID id )

Get QSPIC HReady signal mode.

Parameters

[in] id QSPI controller id

Returns: HReady signal mode

See also: HW_QSPI_HREADY_MODE

◆ hw_qspi_get_io2_direction()

__STATIC_FORCEINLINE HW_QSPI_IO_DIR hw_qspi_get_io2_direction ( HW_QSPIC_ID id )

Get QSPI_IO2 direction.

Parameters

[in] id QSPI controller id

Returns: QSPI_IO2 direction

See also: HW_QSPI_IO_DIR

◆ hw_qspi_get_io2_value()

__STATIC_FORCEINLINE HW_QSPI_IO_VALUE hw_qspi_get_io2_value ( HW_QSPIC_ID id )

Get the value of QSPI_IO2 pad when QSPI_IO2 direction is output.

Parameters

[in] id QSPI controller id

Returns: The value of QSPI_IO2 pad

See also: HW_QSPI_IO_VALUE

◆ hw_qspi_get_io3_direction()

__STATIC_FORCEINLINE HW_QSPI_IO_DIR hw_qspi_get_io3_direction ( HW_QSPIC_ID id )

Get QSPI_IO3 direction.

Parameters

[in] id QSPI controller id

Returns: QSPI_IO3 direction

See also: HW_QSPI_IO_DIR

◆ hw_qspi_get_io3_value()

__STATIC_FORCEINLINE HW_QSPI_IO_VALUE hw_qspi_get_io3_value ( HW_QSPIC_ID id )

Get the value of QSPI_IO3 pad when QSPI_IO3 direction is output.

Parameters

[in] id QSPI controller id

Returns: The value of QSPI_IO3 pad

See also: HW_QSPI_IO_VALUE

◆ hw_qspi_get_read_pipe()

__STATIC_FORCEINLINE HW_QSPI_READ_PIPE hw_qspi_get_read_pipe ( HW_QSPIC_ID id )

Get QSPIC read pipe status.

Parameters

[in] id QSPI controller id

Returns: Status of data read pipe

See also: HW_QSPI_READ_PIPE

◆ hw_qspi_get_read_pipe_clock_delay()

__STATIC_FORCEINLINE HW_QSPI_READ_PIPE_DELAY hw_qspi_get_read_pipe_clock_delay ( HW_QSPIC_ID id )

Get QSPIC read pipe clock delay.

Parameters

[in] id QSPI controller id

Returns: Read pipe clock delay

See also: HW_QSPI_READ_PIPE_DELAY

◆ hw_qspi_get_read_sampling_edge()

__STATIC_FORCEINLINE HW_QSPI_SAMPLING_EDGE hw_qspi_get_read_sampling_edge ( HW_QSPIC_ID id )

Get QSPIC read sampling edge.

Parameters

[in] id QSPI controller id

Returns: Read sampling edge

See also: HW_QSPI_SAMPLING_EDGE

◆ hw_qspi_get_slew_rate()

__STATIC_FORCEINLINE HW_QSPI_SLEW_RATE hw_qspi_get_slew_rate ( HW_QSPIC_ID id )

Get slew rate of QSPIC pads.

Parameters

[in] id QSPI controller id

Returns: Slew rate of QSPIC pads

See also: HW_QSPI_SLEW_RATE

◆ hw_qspi_init()

__RETAINED_CODE void hw_qspi_init	(	HW_QSPIC_ID	id,
		const hw_qspi_config_t *	cfg
	)

Initialize the QSPI controller (QSPIC)

Parameters

[in]	id	QSPI controller id
[in]	cfg	Pointer to QSPIC configuration structure.

See also: hw_qspi_config_t

◆ hw_qspi_read16()

__STATIC_FORCEINLINE uint16_t hw_qspi_read16 ( HW_QSPIC_ID id )

Generate 16 bits data transfer from the external device to the QSPIC (manual mode)

Parameters

[in] id QSPI controller id

Returns: 16 bits value read from the bus

◆ hw_qspi_read32()

__STATIC_FORCEINLINE uint32_t hw_qspi_read32 ( HW_QSPIC_ID id )

Generate 32 bits data transfer from the external device to the QSPIC (manual mode)

Parameters

[in] id QSPI controller id

Returns: 32 bits value read from the bus

◆ hw_qspi_read8()

__STATIC_FORCEINLINE uint8_t hw_qspi_read8 ( HW_QSPIC_ID id )

Generate 8 bits data transfer from the external device to the QSPIC (manual mode)

Parameters

[in] id QSPI controller id

Returns: 8 bits value read from the bus

◆ hw_qspi_read_instr_init()

__STATIC_FORCEINLINE void hw_qspi_read_instr_init	(	HW_QSPIC_ID	id,
		const hw_qspi_read_instr_config_t *	cfg,
		uint8_t	dummy_bytes,
		uint32_t	sys_clk_freq_hz
	)

Initialize the read instruction of the QSPIC.

Parameters

[in]	id	QSPI controller id
[in]	cfg	Pointer to configuration structure of the read instruction.
[in]	dummy_bytes	The number of dummy bytes.
[in]	sys_clk_freq_hz	The system clock frequency in Hz, which is used to calculate the minimum QSPI bus clock cycles that the Chip Select (CS) signal must remain high between two consecutive read instructions.

See also: hw_qspi_read_instr_config_t

◆ hw_qspi_read_status_instr_init()

__STATIC_FORCEINLINE void hw_qspi_read_status_instr_init	(	HW_QSPIC_ID	id,
		const hw_qspi_read_status_instr_config_t *	cfg,
		uint32_t	sys_clk_freq_hz
	)

Initialize the read status register instruction of the QSPIC.

Parameters

[in]	id	QSPI controller id
[in]	cfg	Pointer to configuration structure of the read status register instruction.
[in]	sys_clk_freq_hz	The system clock frequency in Hz, which is used to calculate the minimum required delay, in QSPI bus clock cycles, between an erase or erase resume instruction and the next consecutive read status register instruction.

See also: hw_qspi_read_status_instr_config_t

◆ hw_qspi_set_access_mode()

__STATIC_FORCEINLINE void hw_qspi_set_access_mode	(	HW_QSPIC_ID	id,
		HW_QSPI_ACCESS_MODE	access_mode
	)

Set QSPIC access mode.

Parameters

[in]	id	QSPI controller id
[in]	access_mode	QSPIC access mode

See also: HW_QSPI_ACCESS_MODE

◆ hw_qspi_set_address_size()

__STATIC_FORCEINLINE void hw_qspi_set_address_size	(	HW_QSPIC_ID	id,
		HW_QSPI_ADDR_SIZE	addr_size
	)

Set QSPIC address size.

Parameters

[in]	id	QSPI controller id
[in]	addr_size	QSPIC address size

See also: HW_QSPI_ADDR_SIZE

◆ hw_qspi_set_clock_mode()

__STATIC_FORCEINLINE void hw_qspi_set_clock_mode	(	HW_QSPIC_ID	id,
		HW_QSPI_CLK_MODE	clk_mode
	)

Set QSPIC clock mode.

Parameters

[in]	id	QSPI controller id
[in]	clk_mode	QSPIC clock mode

See also: HW_QSPI_CLK_MODE

◆ hw_qspi_set_div()

__STATIC_FORCEINLINE void hw_qspi_set_div	(	HW_QSPIC_ID	id,
		HW_QSPI_CLK_DIV	div
	)

Set QSPIC clock divider.

Parameters

[in]	id	QSPI controller id
[in]	div	QSPIC clock divider

See also: HW_QSPI_CLK_DIV

◆ hw_qspi_set_drive_current()

__STATIC_FORCEINLINE void hw_qspi_set_drive_current	(	HW_QSPIC_ID	id,
		HW_QSPI_DRIVE_CURRENT	drive_current
	)

Set drive current of QSPIC pads.

Parameters

[in]	id	QSPI controller id
[in]	drive_current	QSPIC pads drive current

See also: HW_QSPI_DRIVE_CURRENT

◆ hw_qspi_set_dummy_bytes()

__STATIC_FORCEINLINE void hw_qspi_set_dummy_bytes	(	HW_QSPIC_ID	id,
		uint8_t	dummy_bytes
	)

Set the number of dummy bytes in auto access mode.

Parameters

[in]	id	QSPI controller id
[in]	dummy_bytes	Number of dummy bytes (0 - 4)

◆ hw_qspi_set_erase_address()

__STATIC_FORCEINLINE void hw_qspi_set_erase_address	(	HW_QSPIC_ID	id,
		uint32_t	erase_addr
	)

Set the address of the block/sector that is requested to be erased.

Parameters

[in]	id	QSPI controller id
[in]	erase_addr	Address to erase.

◆ hw_qspi_set_erase_cs_idle_delay()

__STATIC_FORCEINLINE void hw_qspi_set_erase_cs_idle_delay	(	HW_QSPIC_ID	id,
		uint16_t	cs_idle_delay_nsec,
		uint32_t	clk_freq_hz
	)

Set the minimum number of clocks cycles that CS stays in idle mode, between a write enable, erase, erase suspend and erase resume instruction and the next consecutive command.

Parameters

[in]	id	QSPI controller id
[in]	cs_idle_delay_nsec	The minimum time in nsec that the CS signal stays idle
[in]	clk_freq_hz	The QSPI controller clock frequency (in Hz)

◆ hw_qspi_set_extra_byte()

__STATIC_FORCEINLINE void hw_qspi_set_extra_byte	(	HW_QSPIC_ID	id,
		uint8_t	extra_byte,
		HW_QSPI_BUS_MODE	bus_mode,
		bool	half_disable_out
	)

Set an extra byte to use with read instructions.

Parameters

[in]	id	QSPI controller id
[in]	extra_byte	an extra byte transferred after the address asking memory to stay in continuous read mode or wait for a normal instruction after CS goes inactive
[in]	bus_mode	the mode of the SPI bus during the extra byte phase.
[in]	half_disable_out	true - disable (hi-z) output during the transmission of bits [3:0] of extra byte false - transmit the complete extra byte

See also: hw_qspi_set_read_instruction

◆ hw_qspi_set_hready_mode()

__STATIC_FORCEINLINE void hw_qspi_set_hready_mode	(	HW_QSPIC_ID	id,
		HW_QSPI_HREADY_MODE	mode
	)

Set QSPIC HReady signal mode.

Parameters

[in]	id	QSPI controller id
[in]	mode	HReady signal mode

See also: HW_QSPI_HREADY_MODE

◆ hw_qspi_set_io()

__STATIC_FORCEINLINE void hw_qspi_set_io	(	HW_QSPIC_ID	id,
		HW_QSPI_BUS_MODE	bus_mode
	)

Set the direction and the level of QSPIC IOs based on the Bus Mode.

Parameters

[in]	id	QSPI controller id
[in]	bus_mode	The QSPIC Bus Mode

See also: bus_mode

◆ hw_qspi_set_io2_direction()

__STATIC_FORCEINLINE void hw_qspi_set_io2_direction	(	HW_QSPIC_ID	id,
		HW_QSPI_IO_DIR	dir
	)

Set QSPI_IO2 direction.

Parameters

[in]	id	QSPI controller id
[in]	dir	QSPI_IO2 direction

Note: Set QSPI_IO2 direction to HW_QSPI_IO_DIR_OUTPUT only in Single or Dual SPI mode to control the /WP signal. When the Quad SPI is enabled, dir MUST be set to HW_QSPI_IO_DIR_AUTO_SEL.

See also: HW_QSPI_IO_DIR

◆ hw_qspi_set_io2_value()

__STATIC_FORCEINLINE void hw_qspi_set_io2_value	(	HW_QSPIC_ID	id,
		HW_QSPI_IO_VALUE	value
	)

Set the value of QSPI_IO2 pad when QSPI_IO2 direction is output.

Parameters

[in]	id	QSPI controller id
[in]	value	The value of QSPI_IO2 pad

See also: HW_QSPI_IO_VALUE

◆ hw_qspi_set_io3_direction()

__STATIC_FORCEINLINE void hw_qspi_set_io3_direction	(	HW_QSPIC_ID	id,
		HW_QSPI_IO_DIR	dir
	)

Set QSPI_IO3 direction.

Parameters

[in]	id	QSPI controller id
[in]	dir	QSPI_IO3 direction

Note: Set QSPI_IO3 direction to HW_QSPI_IO_DIR_OUTPUT only in Single or Dual SPI mode to control the /WP signal. When the Quad SPI is enabled, dir MUST be set to HW_QSPI_IO_DIR_AUTO_SEL.

See also: HW_QSPI_IO_DIR

◆ hw_qspi_set_io3_value()

__STATIC_FORCEINLINE void hw_qspi_set_io3_value	(	HW_QSPIC_ID	id,
		HW_QSPI_IO_VALUE	value
	)

Set the value of QSPI_IO3 pad when QSPI_IO3 direction is output.

Parameters

[in]	id	QSPI controller id
[in]	value	The value of QSPI_IO3 pad

See also: HW_QSPI_IO_VALUE

◆ hw_qspi_set_manual_access_bus_mode()

__STATIC_FORCEINLINE void hw_qspi_set_manual_access_bus_mode	(	HW_QSPIC_ID	id,
		HW_QSPI_BUS_MODE	bus_mode
	)

Set QSPIC bus mode in manual access mode.

Parameters

[in]	id	QSPI controller id
[in]	bus_mode	QSPIC bus mode in manual access mode

See also: HW_QSPI_BUS_MODE

◆ hw_qspi_set_read_cs_idle_delay()

__STATIC_FORCEINLINE void hw_qspi_set_read_cs_idle_delay	(	HW_QSPIC_ID	id,
		uint16_t	cs_idle_delay_nsec,
		uint32_t	clk_freq_hz
	)

Set the minimum number of clocks cycles that CS stays in idle mode, between two consecutive read commands.

Parameters

[in]	id	QSPI controller id
[in]	cs_idle_delay_nsec	The minimum time in nsec that the CS signal stays idle
[in]	clk_freq_hz	The QSPI controller clock frequency (in Hz)

◆ hw_qspi_set_read_pipe()

__STATIC_FORCEINLINE void hw_qspi_set_read_pipe	(	HW_QSPIC_ID	id,
		HW_QSPI_READ_PIPE	read_pipe
	)

Set QSPIC data read pipe status.

Parameters

[in]	id	QSPI controller id
[in]	read_pipe	Status of data read pipe

See also: HW_QSPI_READ_PIPE

◆ hw_qspi_set_read_pipe_clock_delay()

__STATIC_FORCEINLINE void hw_qspi_set_read_pipe_clock_delay	(	HW_QSPIC_ID	id,
		HW_QSPI_READ_PIPE_DELAY	delay
	)

Set the QSPIC read pipe clock delay.

Parameters

[in]	id	QSPI controller id
[in]	delay	Read pipe clock delay

See also: HW_QSPI_READ_PIPE_DELAY

◆ hw_qspi_set_read_sampling_edge()

__STATIC_FORCEINLINE void hw_qspi_set_read_sampling_edge	(	HW_QSPIC_ID	id,
		HW_QSPI_SAMPLING_EDGE	edge
	)

Set QSPIC read sampling edge.

Parameters

[in]	id	QSPI controller id
[in]	edge	Read sampling edge

See also: HW_QSPI_SAMPLING_EDGE

◆ hw_qspi_set_slew_rate()

__STATIC_FORCEINLINE void hw_qspi_set_slew_rate	(	HW_QSPIC_ID	id,
		HW_QSPI_SLEW_RATE	slew_rate
	)

Set slew rate of QSPIC pads.

Parameters

[in]	id	QSPI controller id
[in]	slew_rate	QSPIC pads slew rate

See also: HW_QSPI_SLEW_RATE

◆ hw_qspi_suspend_resume_instr_init()

__STATIC_FORCEINLINE void hw_qspi_suspend_resume_instr_init	(	HW_QSPIC_ID	id,
		const hw_qspi_suspend_resume_instr_config_t *	cfg
	)

Initialize the program and erase suspend/resume instruction of the QSPIC.

Parameters

[in]	id	QSPI controller id
[in]	cfg	Pointer to configuration structure of the program and erase suspend/resume instruction.

See also: hw_qspi_suspend_resume_instr_config_t

◆ hw_qspi_trigger_erase()

__STATIC_FORCEINLINE void hw_qspi_trigger_erase ( HW_QSPIC_ID id )

Trigger erase block/sector.

Parameters

[in] id QSPI controller id

◆ hw_qspi_write16()

__STATIC_FORCEINLINE void hw_qspi_write16	(	HW_QSPIC_ID	id,
		uint16_t	data
	)

Generate 16 bits data transfer from the QSPIC to the external device (manual mode)

Parameters

[in]	id	QSPI controller id
[in]	data	16 bits value to be written on the device

◆ hw_qspi_write32()

__STATIC_FORCEINLINE void hw_qspi_write32	(	HW_QSPIC_ID	id,
		uint32_t	data
	)

Generate 32 bits data transfer from the QSPIC to the external device (manual mode)

Parameters

[in]	id	QSPI controller id
[in]	data	32 bits value to be written on the device

◆ hw_qspi_write8()

__STATIC_FORCEINLINE void hw_qspi_write8	(	HW_QSPIC_ID	id,
		uint8_t	data
	)

Generate 8 bits data transfer from the QSPIC to the external device (manual mode)

Parameters

[in]	id	QSPI controller id
[in]	data	8 bits value to be written on the device

◆ hw_qspi_write_enable_instr_init()

__STATIC_FORCEINLINE void hw_qspi_write_enable_instr_init	(	HW_QSPIC_ID	id,
		const hw_qspi_write_enable_instr_config_t *	cfg
	)

Initialize the write enable instruction of the QSPIC.

Parameters

[in]	id	QSPI controller id
[in]	cfg	Pointer to configuration structure of the write enable instruction.

See also: hw_qspi_write_enable_instr_config_t

Files

Data Structures

Macros

Typedefs

Enumerations

Functions

Detailed Description

Macro Definition Documentation

◆ HW_QSPIC_REG_CLR_BIT

◆ HW_QSPIC_REG_GETF

◆ HW_QSPIC_REG_SET_BIT

◆ HW_QSPIC_REG_SETF

Typedef Documentation

◆ HW_QSPIC_ID

Enumeration Type Documentation

◆ HW_QSPI_ACCESS_MODE

◆ HW_QSPI_ADDR_SIZE

◆ HW_QSPI_BUS_MODE

◆ HW_QSPI_BUS_STATUS

◆ HW_QSPI_BUSY_LEVEL

◆ HW_QSPI_CLK_DIV

◆ HW_QSPI_CLK_MODE

◆ HW_QSPI_CONTINUOUS_MODE

◆ HW_QSPI_DRIVE_CURRENT

◆ HW_QSPI_ERASE_STATUS

◆ HW_QSPI_EXTRA_BYTE

◆ HW_QSPI_EXTRA_BYTE_HALF

◆ HW_QSPI_HREADY_MODE

◆ HW_QSPI_IO_DIR

◆ HW_QSPI_IO_VALUE

◆ HW_QSPI_READ_PIPE

◆ HW_QSPI_READ_PIPE_DELAY

◆ HW_QSPI_SAMPLING_EDGE

◆ HW_QSPI_SLEW_RATE

Function Documentation

◆ hw_qspi_clock_disable()

◆ hw_qspi_clock_enable()

◆ hw_qspi_cs_disable()

◆ hw_qspi_cs_enable()

◆ hw_qspi_dummy16()

◆ hw_qspi_dummy32()

◆ hw_qspi_dummy8()

◆ hw_qspi_erase_block()

◆ hw_qspi_erase_instr_init()

◆ hw_qspi_exit_continuous_mode_instr_init()

◆ hw_qspi_exit_continuous_mode_sequence_disable()

◆ hw_qspi_exit_continuous_mode_sequence_enable()

◆ hw_qspi_get_access_mode()

◆ hw_qspi_get_address_size()

◆ hw_qspi_get_bus_status()

◆ hw_qspi_get_clock_mode()

◆ hw_qspi_get_div()

◆ hw_qspi_get_drive_current()

◆ hw_qspi_get_dummy_bytes()

◆ hw_qspi_get_erase_status()

◆ hw_qspi_get_hready_mode()

◆ hw_qspi_get_io2_direction()

◆ hw_qspi_get_io2_value()

◆ hw_qspi_get_io3_direction()

◆ hw_qspi_get_io3_value()

◆ hw_qspi_get_read_pipe()

◆ hw_qspi_get_read_pipe_clock_delay()

◆ hw_qspi_get_read_sampling_edge()

◆ hw_qspi_get_slew_rate()

◆ hw_qspi_init()

◆ hw_qspi_read16()

◆ hw_qspi_read32()

◆ hw_qspi_read8()

◆ hw_qspi_read_instr_init()

◆ hw_qspi_read_status_instr_init()

◆ hw_qspi_set_access_mode()

◆ hw_qspi_set_address_size()

◆ hw_qspi_set_clock_mode()

◆ hw_qspi_set_div()

◆ hw_qspi_set_drive_current()

◆ hw_qspi_set_dummy_bytes()

◆ hw_qspi_set_erase_address()

◆ hw_qspi_set_erase_cs_idle_delay()

◆ hw_qspi_set_extra_byte()

◆ hw_qspi_set_hready_mode()