CACHE registers (CACHE) More...

#include <DA1459x-00.h>

Data Fields
__IM uint32_t	RESERVED [8]

__IOM uint32_t	CACHE_CTRL2_REG

__IOM uint32_t	CACHE_MRM_HITS_REG

__IOM uint32_t	CACHE_MRM_MISSES_REG

__IOM uint32_t	CACHE_MRM_CTRL_REG

__IOM uint32_t	CACHE_MRM_TINT_REG

__IOM uint32_t	CACHE_MRM_MISSES_THRES_REG

__IOM uint32_t	CACHE_MRM_HITS_THRES_REG

__IOM uint32_t	CACHE_FLASH_REG

__IOM uint32_t	CACHE_EFLASH_REG

__IOM uint32_t	CACHE_MRM_HITS1WS_REG

__IOM uint32_t	SWD_RESET_REG

Detailed Description

CACHE registers (CACHE)

Field Documentation

◆ CACHE_CTRL2_REG

__IOM uint32_t CACHE_Type::CACHE_CTRL2_REG

(@ 0x00000020) Cache control register 2 (only Word (32-bits) access supported).

◆ CACHE_EFLASH_REG

__IOM uint32_t CACHE_Type::CACHE_EFLASH_REG

(@ 0x00000044) Cache eFlash program size and base address register (only Word (32-bits) access supported). This register is NA for the CMAC Cache (no remapping done in the CMAC Cache).

◆ CACHE_FLASH_REG

__IOM uint32_t CACHE_Type::CACHE_FLASH_REG

(@ 0x00000040) Cache QSPI Flash program size and base address register (only Word (32-bits) access supported). This register is NA for the CMAC Cache (no remapping done in the CMAC Cache).

◆ CACHE_MRM_CTRL_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_CTRL_REG

(@ 0x00000030) Cache MRM (Miss Rate Monitor) CONTROL register (only Word (32-bits) access supported).

◆ CACHE_MRM_HITS1WS_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_HITS1WS_REG

(@ 0x00000048) Cache MRM (Miss Rate Monitor) HITS with 1 Wait State register (only Word (32-bits) access supported).

◆ CACHE_MRM_HITS_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_HITS_REG

(@ 0x00000028) Cache MRM (Miss Rate Monitor) HITS register (only Word (32-bits) access supported).

◆ CACHE_MRM_HITS_THRES_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_HITS_THRES_REG

(@ 0x0000003C) Cache MRM (Miss Rate Monitor) HITS THRESHOLD register (only Word (32-bits) access supported).

◆ CACHE_MRM_MISSES_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_MISSES_REG

(@ 0x0000002C) Cache MRM (Miss Rate Monitor) MISSES register (only Word (32-bits) access supported).

◆ CACHE_MRM_MISSES_THRES_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_MISSES_THRES_REG

(@ 0x00000038) Cache MRM (Miss Rate Monitor) THRESHOLD register (only Word (32-bits) access supported).

◆ CACHE_MRM_TINT_REG

__IOM uint32_t CACHE_Type::CACHE_MRM_TINT_REG

(@ 0x00000034) Cache MRM (Miss Rate Monitor) TIME INTERVAL register (only Word (32-bits) access supported).

◆ RESERVED

__IM uint32_t CACHE_Type::RESERVED[8]

< (@ 0x1A0C0000) CACHE Structure

◆ SWD_RESET_REG

__IOM uint32_t CACHE_Type::SWD_RESET_REG

(@ 0x00000050) SWD HW reset control register (only Word (32-bits) access supported).

The documentation for this struct was generated from the following file:

sdk/bsp/include/DA1459x-00.h

Data Fields