hw_quad_v2.h

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#ifndef HW_QUAD_V2_H_
#define HW_QUAD_V2_H_
 
#if dg_configUSE_HW_QUAD
 
#include <stdbool.h>
#include <stdint.h>
#include "sdk_defs.h"
 
typedef enum {
        HW_QUAD_REG_CLK_OFF = 0,
        HW_QUAD_REG_CLK_ON = 1
} HW_QUAD_REG_CLK;
 
typedef enum {
        HW_QUAD_REG_CTRL_IRQ_STATUS_OFF_NO_CLR = 0,
        HW_QUAD_REG_CTRL_IRQ_STATUS_ON_CLR = 1
} HW_QUAD_REG_CTRL_IRQ_STATUS;
 
typedef enum {
        HW_QUAD_REG_CTRL_EVENT_CNT_CLR_OFF = 0,
        HW_QUAD_REG_CTRL_EVENT_CNT_CLR_ON = 1
} HW_QUAD_REG_CTRL_EVENT_CNT_CLR;
 
typedef enum {
        HW_QUAD_REG_CTRL_IRQ_EN_OFF = 0,
        HW_QUAD_REG_CTRL_IRQ_EN_ON = 1
} HW_QUAD_REG_CTRL_IRQ_EN;
 
typedef enum {
        HW_QUAD_REG_CTRL2_CHANNEL_EVENT_MODE_NORMAL_CNT = 0,
        HW_QUAD_REG_CTRL2_CHANNEL_EVENT_MODE_EDGE_CNT = 1
} HW_QUAD_REG_CTRL2_CHANNEL_EVENT_MODE;
 
typedef enum {
        HW_QUAD_REG_INPUT_NONE          = 0,
        HW_QUAD_REG_INPUT_A_P000_B_P001 = 1,
        HW_QUAD_REG_INPUT_A_P002_B_P003 = 2,
        HW_QUAD_REG_INPUT_A_P004_B_P005 = 3,
        HW_QUAD_REG_INPUT_A_P008_B_P009 = 4,
        HW_QUAD_REG_INPUT_A_P010_B_P011 = 5,
        HW_QUAD_REG_INPUT_A_P100_B_P102 = 6,
        HW_QUAD_REG_INPUT_A_P103_B_P105 = 7,
        HW_QUAD_REG_INPUT_A_P106_B_P107 = 8,
        HW_QUAD_REG_INPUT_A_P108_B_P109 = 9,
        HW_QUAD_REG_INPUT_A_P110_B_P111 = 10,
        HW_QUAD_REG_INPUT_A_P112_B_P101 = 11,
        HW_QUAD_REG_INPUT_A_P104_B_P115 = 12
} HW_QUAD_GPIO_INPUT;
 
typedef enum {
        HW_QUAD_REG_CLOCKDIV_PRESCALER_OFF = 0,
        HW_QUAD_REG_CLOCKDIV_PRESCALER_ON = 1
} HW_QUAD_REG_CLOCKDIV_PRESCALER;
 
typedef struct {
        int16_t hw_quad_xcnt_raw;
        int16_t hw_quad_ycnt_raw;
        int16_t hw_quad_zcnt_raw;
        uint8_t hw_quad_event_cnt_raw;
        int16_t hw_quad_xcnt_delta;
        int16_t hw_quad_ycnt_delta;
        int16_t hw_quad_zcnt_delta;
} hw_quad_values_t;
 
typedef void (*hw_quad_handler_cb)(const volatile hw_quad_values_t *quad_values, void *user_data);
 
typedef struct {
        HW_QUAD_REG_CLOCKDIV_PRESCALER clk_prescaler;
        uint16_t clk_div;
        HW_QUAD_REG_CTRL2_CHANNEL_EVENT_MODE chz_event_mode;
        HW_QUAD_REG_CTRL2_CHANNEL_EVENT_MODE chy_event_mode;
        HW_QUAD_REG_CTRL2_CHANNEL_EVENT_MODE chx_event_mode;
        HW_QUAD_GPIO_INPUT chz_port_sel;
        HW_QUAD_GPIO_INPUT chy_port_sel;
        HW_QUAD_GPIO_INPUT chx_port_sel;
} hw_quad_config_t;
 
__STATIC_FORCEINLINE int16_t hw_quad_get_xcnt_reg(void)
{
        return QUADEC->QDEC_XCNT_REG;
}
 
__STATIC_FORCEINLINE int16_t hw_quad_get_ycnt_reg(void)
{
        return QUADEC->QDEC_YCNT_REG;
}
 
__STATIC_FORCEINLINE int16_t hw_quad_get_zcnt_reg(void)
{
        return QUADEC->QDEC_ZCNT_REG;
}
 
__STATIC_FORCEINLINE uint8_t hw_quad_get_event_cnt_reg(void)
{
        return QUADEC->QDEC_EVENT_CNT_REG;
}
 
__STATIC_FORCEINLINE void hw_quad_qdec_clk_en(HW_QUAD_REG_CLK enable)
{
        GLOBAL_INT_DISABLE();
        REG_SETF(CRG_TOP, CLK_AMBA_REG, QDEC_CLK_ENABLE, enable);
        GLOBAL_INT_RESTORE();
}
 
__STATIC_FORCEINLINE void hw_quad_clr_event_cnt(void)
{
        REG_SETF(QUADEC, QDEC_CTRL_REG, QDEC_EVENT_CNT_CLR, HW_QUAD_REG_CTRL_EVENT_CNT_CLR_ON);
}
 
__STATIC_FORCEINLINE void hw_quad_clr_irq_status(void)
{
        REG_SETF(QUADEC, QDEC_CTRL_REG, QDEC_IRQ_STATUS, HW_QUAD_REG_CTRL_IRQ_STATUS_ON_CLR);
}
 
__STATIC_FORCEINLINE HW_QUAD_REG_CTRL_IRQ_EN hw_quad_return_irq_status(void)
{
        return REG_GETF(QUADEC, QDEC_CTRL_REG, QDEC_IRQ_STATUS);
}
 
void hw_quad_interrupt_enable_and_register(hw_quad_handler_cb cb, uint8_t thres_num, void *user_data_p);
 
void hw_quad_interrupt_disable_and_unregister(void);
 
void hw_quad_start(void);
 
void hw_quad_stop(void);
 
void hw_quad_disable(void);
 
void hw_quad_init(const hw_quad_config_t *init_data);
 
#endif /* dg_configUSE_HW_QUAD */
 
 
#endif /* HW_QUAD_V2_H_ */