SmartSnippets DA1459x SDK
DA1459x-00.h
1 /*
2  * Copyright (C) 2020-2023 Renesas Electronics Corporation and/or its affiliates.
3  * All rights reserved. Confidential Information.
4  *
5  * This software ("Software") is supplied by Renesas Electronics Corporation and/or its
6  * affiliates ("Renesas"). Renesas grants you a personal, non-exclusive, non-transferable,
7  * revocable, non-sub-licensable right and license to use the Software, solely if used in
8  * or together with Renesas products. You may make copies of this Software, provided this
9  * copyright notice and disclaimer ("Notice") is included in all such copies. Renesas
10  * reserves the right to change or discontinue the Software at any time without notice.
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS". RENESAS DISCLAIMS ALL WARRANTIES OF ANY KIND,
13  * WHETHER EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
14  * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. TO THE
15  * MAXIMUM EXTENT PERMITTED UNDER LAW, IN NO EVENT SHALL RENESAS BE LIABLE FOR ANY DIRECT,
16  * INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING FROM, OUT OF OR IN
17  * CONNECTION WITH THE SOFTWARE, EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY OF
18  * SUCH DAMAGES. USE OF THIS SOFTWARE MAY BE SUBJECT TO TERMS AND CONDITIONS CONTAINED IN
19  * AN ADDITIONAL AGREEMENT BETWEEN YOU AND RENESAS. IN CASE OF CONFLICT BETWEEN THE TERMS
20  * OF THIS NOTICE AND ANY SUCH ADDITIONAL LICENSE AGREEMENT, THE TERMS OF THE AGREEMENT
21  * SHALL TAKE PRECEDENCE. BY CONTINUING TO USE THIS SOFTWARE, YOU AGREE TO THE TERMS OF
22  * THIS NOTICE.IF YOU DO NOT AGREE TO THESE TERMS, YOU ARE NOT PERMITTED TO USE THIS
23  * SOFTWARE.
24  *
25  * @file DA1459x-00.h
26  * @brief CMSIS HeaderFile
27  * @version 1.2
28  * @date 10. October 2023
29  * @note Generated by SVDConv V3.3.42 on Tuesday, 10.10.2023 12:59:21
30  * from File 'config/embsys/Dialog_Semiconductor/DA1459x-00.xml',
31  * last modified on Tuesday, 10.10.2023 13:02:31.
32  */
33 
34 
35 
46 #ifndef DA1459X_H
47 #define DA1459X_H
48 
49 #ifdef __cplusplus
50 extern "C" {
51 #endif
52 
53 
60 /* =========================================================================================================================== */
61 /* ================ Interrupt Number Definition ================ */
62 /* =========================================================================================================================== */
63 
67 typedef enum {
68 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */
69  Reset_IRQn = -15,
70  NonMaskableInt_IRQn = -14,
71  HardFault_IRQn = -13,
72  MemoryManagement_IRQn = -12,
74  BusFault_IRQn = -11,
76  UsageFault_IRQn = -10,
77  SecureFault_IRQn = -9,
78  SVCall_IRQn = -5,
79  DebugMonitor_IRQn = -4,
80  PendSV_IRQn = -2,
81  SysTick_IRQn = -1,
82 /* ========================================== DA1459x Specific Interrupt Numbers =========================================== */
83  RESERVED0_IRQn = 0,
84  DMA_IRQn = 1,
85  CMAC2SYS_IRQn = 2,
86  UART_IRQn = 3,
87  UART2_IRQn = 4,
88  I2C_IRQn = 5,
89  SPI_IRQn = 6,
90  FCU_IRQn = 7,
91  PCM_IRQn = 8,
92  SRC_IN_IRQn = 9,
93  SRC_OUT_IRQn = 10,
94  SRC2_IN_IRQn = 11,
95  SRC2_OUT_IRQn = 12,
96  MDCT_IRQn = 13,
97  TIMER_IRQn = 14,
98  TIMER2_IRQn = 15,
99  RTC_IRQn = 16,
100  KEY_WKUP_GPIO_IRQn = 17,
101  PDC_M33_IRQn = 18,
102  MRM_IRQn = 19,
103  RESERVED20_IRQn = 20,
104  QUADDEC_IRQn = 21,
105  RESERVED22_IRQn = 22,
106  XTAL32M_RDY_IRQn = 23,
107  CLK_CALIBRATION_IRQn = 24,
108  GPADC_IRQn = 25,
110  SDADC_IRQn = 26,
111  CRYPTO_IRQn = 27,
112  CAPTIMER_IRQn = 28,
113  RFDIAG_IRQn = 29,
114  TIMER3_IRQn = 30,
115  TIMER4_IRQn = 31,
116  RTC_EVENT_IRQn = 32,
117  GPIO_P0_IRQn = 33,
118  GPIO_P1_IRQn = 34
119 } IRQn_Type;
120 
121 
122 
123 /* =========================================================================================================================== */
124 /* ================ Processor and Core Peripheral Section ================ */
125 /* =========================================================================================================================== */
126 
127 /* ========================== Configuration of the ARM Cortex-M33 Processor and Core Peripherals =========================== */
128 #define __CM33_REV 0x0002U
129 #define __NVIC_PRIO_BITS 4
130 #define __Vendor_SysTickConfig 0
131 #define __VTOR_PRESENT 1
132 #define __MPU_PRESENT 1
133 #define __FPU_PRESENT 1
134 #define __FPU_DP 0
135 #define __DSP_PRESENT 1
136 #define __SAUREGION_PRESENT 0 /* End of group Configuration_of_CMSIS */
140 
141 #include "core_cm33.h"
142 #include "system_DA1459x.h"
144 #ifndef __IM
145  #define __IM __I
146 #endif
147 #ifndef __OM
148  #define __OM __O
149 #endif
150 #ifndef __IOM
151  #define __IOM __IO
152 #endif
153 
154 
155 /* =========================================================================================================================== */
156 /* ================ Device Specific Peripheral Section ================ */
157 /* =========================================================================================================================== */
158 
159 
166 /* =========================================================================================================================== */
167 /* ================ AES_HASH ================ */
168 /* =========================================================================================================================== */
169 
170 
175 typedef struct {
176  __IOM uint32_t CRYPTO_CTRL_REG;
177  __IOM uint32_t CRYPTO_START_REG;
178  __IOM uint32_t CRYPTO_FETCH_ADDR_REG;
179  __IOM uint32_t CRYPTO_LEN_REG;
180  __IOM uint32_t CRYPTO_DEST_ADDR_REG;
181  __IOM uint32_t CRYPTO_STATUS_REG;
182  __IOM uint32_t CRYPTO_CLRIRQ_REG;
183  __IOM uint32_t CRYPTO_MREG0_REG;
184  __IOM uint32_t CRYPTO_MREG1_REG;
185  __IOM uint32_t CRYPTO_MREG2_REG;
186  __IOM uint32_t CRYPTO_MREG3_REG;
187  __IM uint32_t RESERVED[53];
188  __IOM uint32_t CRYPTO_KEYS_START;
190 } AES_HASH_Type;
194 /* =========================================================================================================================== */
195 /* ================ ANAMISC_BIF ================ */
196 /* =========================================================================================================================== */
197 
198 
203 typedef struct {
204  __IM uint32_t RESERVED[4];
205  __IOM uint32_t CLK_REF_SEL_REG;
206  __IOM uint32_t CLK_REF_CNT_REG;
207  __IOM uint32_t CLK_REF_VAL_REG;
208  __IOM uint32_t CLK_CAL_IRQ_REG;
209 } ANAMISC_BIF_Type;
213 /* =========================================================================================================================== */
214 /* ================ CACHE ================ */
215 /* =========================================================================================================================== */
216 
217 
222 typedef struct {
223  __IM uint32_t RESERVED[8];
224  __IOM uint32_t CACHE_CTRL2_REG;
226  __IM uint32_t RESERVED1;
227  __IOM uint32_t CACHE_MRM_HITS_REG;
229  __IOM uint32_t CACHE_MRM_MISSES_REG;
231  __IOM uint32_t CACHE_MRM_CTRL_REG;
233  __IOM uint32_t CACHE_MRM_TINT_REG;
235  __IOM uint32_t CACHE_MRM_MISSES_THRES_REG;
237  __IOM uint32_t CACHE_MRM_HITS_THRES_REG;
239  __IOM uint32_t CACHE_FLASH_REG;
243  __IOM uint32_t CACHE_EFLASH_REG;
247  __IOM uint32_t CACHE_MRM_HITS1WS_REG;
250  __IM uint32_t RESERVED2;
251  __IOM uint32_t SWD_RESET_REG;
253 } CACHE_Type;
257 /* =========================================================================================================================== */
258 /* ================ CHIP_VERSION ================ */
259 /* =========================================================================================================================== */
260 
261 
266 typedef struct {
267  __IOM uint32_t CHIP_ID1_REG;
268  __IOM uint32_t CHIP_ID2_REG;
269  __IOM uint32_t CHIP_ID3_REG;
270  __IOM uint32_t CHIP_ID4_REG;
271  __IOM uint32_t CHIP_SWC_REG;
272  __IOM uint32_t CHIP_REVISION_REG;
273  __IM uint32_t RESERVED[56];
274  __IOM uint32_t CHIP_TEST1_REG;
275  __IOM uint32_t CHIP_TEST2_REG;
276 } CHIP_VERSION_Type;
280 /* =========================================================================================================================== */
281 /* ================ CMAC_CACHE ================ */
282 /* =========================================================================================================================== */
283 
284 
289 typedef struct {
290  __IM uint32_t RESERVED[8];
291  __IOM uint32_t CM_CACHE_CTRL2_REG;
293  __IM uint32_t RESERVED1;
294  __IOM uint32_t CM_CACHE_MRM_HITS_REG;
296  __IOM uint32_t CM_CACHE_MRM_MISSES_REG;
298  __IOM uint32_t CM_CACHE_MRM_CTRL_REG;
300  __IOM uint32_t CM_CACHE_MRM_TINT_REG;
302  __IOM uint32_t CM_CACHE_MRM_MISSES_THRES_REG;
304  __IOM uint32_t CM_CACHE_MRM_HITS_THRES_REG;
306  __IOM uint32_t CM_CACHE_FLASH_REG;
310  __IOM uint32_t CM_CACHE_EFLASH_REG;
314  __IOM uint32_t CM_CACHE_MRM_HITS1WS_REG;
317  __IM uint32_t RESERVED2;
318  __IOM uint32_t CM_CACHE_RESET_REG;
320 } CMAC_CACHE_Type;
324 /* =========================================================================================================================== */
325 /* ================ CRG_AUD ================ */
326 /* =========================================================================================================================== */
327 
328 
333 typedef struct {
334  __IM uint32_t RESERVED[16];
335  __IOM uint32_t PCM_DIV_REG;
336  __IOM uint32_t PCM_FDIV_REG;
337  __IOM uint32_t PDM_DIV_REG;
338  __IOM uint32_t SRC_DIV_REG;
339 } CRG_AUD_Type;
343 /* =========================================================================================================================== */
344 /* ================ CRG_COM ================ */
345 /* =========================================================================================================================== */
346 
347 
352 typedef struct {
353  __IM uint32_t RESERVED;
354  __IOM uint32_t CLK_COM_REG;
355  __IOM uint32_t SET_CLK_COM_REG;
357  __IOM uint32_t RESET_CLK_COM_REG;
359 } CRG_COM_Type;
363 /* =========================================================================================================================== */
364 /* ================ CRG_PER ================ */
365 /* =========================================================================================================================== */
366 
367 
372 typedef struct {
373  __IM uint32_t RESERVED;
374  __IOM uint32_t CLK_PER_REG;
375  __IOM uint32_t SET_CLK_PER_REG;
377  __IOM uint32_t RESET_CLK_PER_REG;
379 } CRG_PER_Type;
383 /* =========================================================================================================================== */
384 /* ================ CRG_SYS ================ */
385 /* =========================================================================================================================== */
386 
387 
392 typedef struct {
393  __IOM uint32_t CLK_SYS_REG;
394 } CRG_SYS_Type;
398 /* =========================================================================================================================== */
399 /* ================ CRG_TOP ================ */
400 /* =========================================================================================================================== */
401 
402 
407 typedef struct {
408  __IOM uint32_t CLK_AMBA_REG;
409  __IM uint32_t RESERVED[2];
410  __IOM uint32_t RST_CTRL_REG;
411  __IOM uint32_t CLK_RADIO_REG;
412  __IOM uint32_t CLK_CTRL_REG;
413  __IOM uint32_t CLK_TMR_REG;
414  __IOM uint32_t CLK_SWITCH2XTAL_REG;
415  __IOM uint32_t PMU_CTRL_REG;
416  __IOM uint32_t SYS_CTRL_REG;
417  __IOM uint32_t SYS_STAT_REG;
418  __IM uint32_t RESERVED1[4];
419  __IOM uint32_t CLK_RCLP_REG;
420  __IOM uint32_t CLK_XTAL32K_REG;
421  __IOM uint32_t CLK_RC32M_REG;
422  __IOM uint32_t CLK_RCX_REG;
423  __IOM uint32_t CLK_RTCDIV_REG;
424  __IOM uint32_t BANDGAP_REG;
425  __IM uint32_t RESERVED2[7];
426  __IOM uint32_t P0_PAD_LATCH_REG;
427  __IOM uint32_t P0_SET_PAD_LATCH_REG;
428  __IOM uint32_t P0_RESET_PAD_LATCH_REG;
429  __IOM uint32_t P1_PAD_LATCH_REG;
430  __IOM uint32_t P1_SET_PAD_LATCH_REG;
431  __IOM uint32_t P1_RESET_PAD_LATCH_REG;
432  __IM uint32_t RESERVED3[4];
433  __IOM uint32_t POR_PIN_REG;
434  __IOM uint32_t POR_TIMER_REG;
435  __IM uint32_t RESERVED4;
436  __IOM uint32_t BIAS_VREF_SEL_REG;
437  __IM uint32_t RESERVED5[5];
438  __IOM uint32_t RESET_STAT_REG;
439  __IOM uint32_t RAM_PWR_CTRL_REG;
440  __IM uint32_t RESERVED6[2];
441  __IOM uint32_t SECURE_BOOT_REG;
443  __IOM uint32_t BOD_CTRL_REG;
444  __IOM uint32_t DISCHARGE_RAIL_REG;
446  __IM uint32_t RESERVED7;
447  __IOM uint32_t ANA_STATUS_REG;
448  __IOM uint32_t POWER_CTRL_REG;
449  __IOM uint32_t POWER_LEVEL_REG;
450  __IM uint32_t RESERVED8[2];
451  __IOM uint32_t HIBERN_CTRL_REG;
452  __IOM uint32_t PMU_SLEEP_REG;
453  __IM uint32_t RESERVED9;
454  __IOM uint32_t STARTUP_STATUS_REG;
455 } CRG_TOP_Type;
459 /* =========================================================================================================================== */
460 /* ================ CRG_XTAL ================ */
461 /* =========================================================================================================================== */
462 
463 
468 typedef struct {
469  __IOM uint32_t XTAL32M_START_REG;
470  __IOM uint32_t XTAL32M_SETTLE_REG;
471  __IOM uint32_t XTAL32M_TRIM_REG;
472  __IOM uint32_t XTAL32M_CAP_MEAS_REG;
473  __IOM uint32_t XTAL32M_FSM_REG;
474  __IOM uint32_t XTAL32M_CTRL_REG;
475  __IOM uint32_t XTAL32M_IRQ_CTRL_REG;
476  __IM uint32_t RESERVED[2];
477  __IOM uint32_t XTAL32M_STAT0_REG;
478  __IOM uint32_t XTAL32M_IRQ_STAT_REG;
479  __IM uint32_t RESERVED1[13];
480  __IOM uint32_t CLKDBLR_CTRL1_REG;
482  __IOM uint32_t CLKDBLR_CTRL2_REG;
484  __IOM uint32_t CLKDBLR_STATUS_REG;
485 } CRG_XTAL_Type;
489 /* =========================================================================================================================== */
490 /* ================ DCDC ================ */
491 /* =========================================================================================================================== */
492 
493 
498 typedef struct {
499  __IOM uint32_t DCDC_CTRL_REG;
500 } DCDC_Type;
504 /* =========================================================================================================================== */
505 /* ================ DMA ================ */
506 /* =========================================================================================================================== */
507 
508 
513 typedef struct {
514  __IOM uint32_t DMA0_A_START_REG;
515  __IOM uint32_t DMA0_B_START_REG;
516  __IOM uint32_t DMA0_INT_REG;
517  __IOM uint32_t DMA0_LEN_REG;
518  __IOM uint32_t DMA0_CTRL_REG;
519  __IOM uint32_t DMA0_IDX_REG;
520  __IM uint32_t RESERVED[2];
521  __IOM uint32_t DMA1_A_START_REG;
522  __IOM uint32_t DMA1_B_START_REG;
523  __IOM uint32_t DMA1_INT_REG;
524  __IOM uint32_t DMA1_LEN_REG;
525  __IOM uint32_t DMA1_CTRL_REG;
526  __IOM uint32_t DMA1_IDX_REG;
527  __IM uint32_t RESERVED1[2];
528  __IOM uint32_t DMA2_A_START_REG;
529  __IOM uint32_t DMA2_B_START_REG;
530  __IOM uint32_t DMA2_INT_REG;
531  __IOM uint32_t DMA2_LEN_REG;
532  __IOM uint32_t DMA2_CTRL_REG;
533  __IOM uint32_t DMA2_IDX_REG;
534  __IM uint32_t RESERVED2[2];
535  __IOM uint32_t DMA3_A_START_REG;
536  __IOM uint32_t DMA3_B_START_REG;
537  __IOM uint32_t DMA3_INT_REG;
538  __IOM uint32_t DMA3_LEN_REG;
539  __IOM uint32_t DMA3_CTRL_REG;
540  __IOM uint32_t DMA3_IDX_REG;
541  __IM uint32_t RESERVED3[2];
542  __IOM uint32_t DMA4_A_START_REG;
543  __IOM uint32_t DMA4_B_START_REG;
544  __IOM uint32_t DMA4_INT_REG;
545  __IOM uint32_t DMA4_LEN_REG;
546  __IOM uint32_t DMA4_CTRL_REG;
547  __IOM uint32_t DMA4_IDX_REG;
548  __IM uint32_t RESERVED4[2];
549  __IOM uint32_t DMA5_A_START_REG;
550  __IOM uint32_t DMA5_B_START_REG;
551  __IOM uint32_t DMA5_INT_REG;
552  __IOM uint32_t DMA5_LEN_REG;
553  __IOM uint32_t DMA5_CTRL_REG;
554  __IOM uint32_t DMA5_IDX_REG;
555  __IM uint32_t RESERVED5[18];
556  __IOM uint32_t DMA_REQ_MUX_REG;
557  __IOM uint32_t DMA_INT_STATUS_REG;
558  __IOM uint32_t DMA_CLEAR_INT_REG;
559  __IOM uint32_t DMA_INT_MASK_REG;
560  __IOM uint32_t DMA_SET_INT_MASK_REG;
561  __IOM uint32_t DMA_RESET_INT_MASK_REG;
562 } DMA_Type;
566 /* =========================================================================================================================== */
567 /* ================ DW ================ */
568 /* =========================================================================================================================== */
569 
570 
575 typedef struct {
576  __IOM uint32_t AHB_DMA_PL1_REG;
578  __IOM uint32_t AHB_DMA_PL2_REG;
580  __IOM uint32_t AHB_DMA_PL3_REG;
582  __IOM uint32_t AHB_DMA_PL4_REG;
584  __IM uint32_t RESERVED[14];
585  __IOM uint32_t AHB_DMA_DFLT_MASTER_REG;
586  __IOM uint32_t AHB_DMA_WTEN_REG;
588  __IOM uint32_t AHB_DMA_TCL_REG;
589  __IOM uint32_t AHB_DMA_CCLM1_REG;
590  __IOM uint32_t AHB_DMA_CCLM2_REG;
591  __IOM uint32_t AHB_DMA_CCLM3_REG;
593  __IOM uint32_t AHB_DMA_CCLM4_REG;
594  __IM uint32_t RESERVED1[11];
595  __IOM uint32_t AHB_DMA_VERSION_REG;
596 } DW_Type;
600 /* =========================================================================================================================== */
601 /* ================ FCU ================ */
602 /* =========================================================================================================================== */
603 
604 
609 typedef struct {
610  __IOM uint32_t FLASH_CTRL_REG;
611  __IOM uint32_t FLASH_PTNVH1_REG;
612  __IOM uint32_t FLASH_PTPROG_REG;
613  __IOM uint32_t FLASH_PTERASE_REG;
614  __IOM uint32_t FLASH_PTME_REG;
615  __IOM uint32_t FLASH_PTWK_SP_REG;
616  __IOM uint32_t FLASH_PTERASE_SEG_REG;
617  __IOM uint32_t FLASH_RTERASE_TOT_CNT_REG;
618  __IOM uint32_t FLASH_RTERASE_SEG_CNT_REG;
619 } FCU_Type;
623 /* =========================================================================================================================== */
624 /* ================ GPADC ================ */
625 /* =========================================================================================================================== */
626 
627 
632 typedef struct {
633  __IOM uint32_t GP_ADC_CTRL_REG;
634  __IOM uint32_t GP_ADC_CTRL2_REG;
635  __IOM uint32_t GP_ADC_CTRL3_REG;
636  __IOM uint32_t GP_ADC_SEL_REG;
637  __IOM uint32_t GP_ADC_OFFP_REG;
638  __IOM uint32_t GP_ADC_OFFN_REG;
639  __IM uint32_t RESERVED;
640  __IOM uint32_t GP_ADC_CLEAR_INT_REG;
641  __IOM uint32_t GP_ADC_RESULT_REG;
642 } GPADC_Type;
646 /* =========================================================================================================================== */
647 /* ================ GPIO ================ */
648 /* =========================================================================================================================== */
649 
650 
655 typedef struct {
656  __IOM uint32_t P0_DATA_REG;
657  __IOM uint32_t P1_DATA_REG;
658  __IOM uint32_t P0_SET_DATA_REG;
659  __IOM uint32_t P1_SET_DATA_REG;
660  __IOM uint32_t P0_RESET_DATA_REG;
661  __IOM uint32_t P1_RESET_DATA_REG;
662  __IOM uint32_t P0_00_MODE_REG;
663  __IOM uint32_t P0_01_MODE_REG;
664  __IOM uint32_t P0_02_MODE_REG;
665  __IOM uint32_t P0_03_MODE_REG;
666  __IOM uint32_t P0_04_MODE_REG;
667  __IOM uint32_t P0_05_MODE_REG;
668  __IOM uint32_t P0_06_MODE_REG;
669  __IOM uint32_t P0_07_MODE_REG;
670  __IOM uint32_t P0_08_MODE_REG;
671  __IOM uint32_t P0_09_MODE_REG;
672  __IOM uint32_t P0_10_MODE_REG;
673  __IOM uint32_t P0_11_MODE_REG;
674  __IOM uint32_t P0_12_MODE_REG;
675  __IOM uint32_t P0_13_MODE_REG;
676  __IOM uint32_t P0_14_MODE_REG;
677  __IOM uint32_t P0_15_MODE_REG;
678  __IOM uint32_t P1_00_MODE_REG;
679  __IOM uint32_t P1_01_MODE_REG;
680  __IOM uint32_t P1_02_MODE_REG;
681  __IOM uint32_t P1_03_MODE_REG;
682  __IOM uint32_t P1_04_MODE_REG;
683  __IOM uint32_t P1_05_MODE_REG;
684  __IOM uint32_t P1_06_MODE_REG;
685  __IOM uint32_t P1_07_MODE_REG;
686  __IOM uint32_t P1_08_MODE_REG;
687  __IOM uint32_t P1_09_MODE_REG;
688  __IOM uint32_t P1_10_MODE_REG;
689  __IOM uint32_t P1_11_MODE_REG;
690  __IOM uint32_t P1_12_MODE_REG;
691  __IOM uint32_t P1_13_MODE_REG;
692  __IOM uint32_t P1_14_MODE_REG;
693  __IOM uint32_t P1_15_MODE_REG;
694  __IM uint32_t RESERVED[2];
695  __IOM uint32_t GPIO_CLK_SEL_REG;
696  __IOM uint32_t P0_WEAK_CTRL_REG;
697  __IOM uint32_t P1_WEAK_CTRL_REG;
698 } GPIO_Type;
702 /* =========================================================================================================================== */
703 /* ================ GPREG ================ */
704 /* =========================================================================================================================== */
705 
706 
711 typedef struct {
712  __IOM uint32_t SET_FREEZE_REG;
714  __IOM uint32_t RESET_FREEZE_REG;
716  __IOM uint32_t DEBUG_REG;
717  __IOM uint32_t GP_STATUS_REG;
718  __IM uint32_t RESERVED;
719  __IOM uint32_t SCPU_FCU_TAG_REG;
720 } GPREG_Type;
724 /* =========================================================================================================================== */
725 /* ================ I2C ================ */
726 /* =========================================================================================================================== */
727 
728 
733 typedef struct {
734  __IOM uint32_t I2C_CON_REG;
735  __IOM uint32_t I2C_TAR_REG;
736  __IOM uint32_t I2C_SAR_REG;
737  __IOM uint32_t I2C_HS_MADDR_REG;
738  __IOM uint32_t I2C_DATA_CMD_REG;
739  __IOM uint32_t I2C_SS_SCL_HCNT_REG;
740  __IOM uint32_t I2C_SS_SCL_LCNT_REG;
741  __IOM uint32_t I2C_FS_SCL_HCNT_REG;
742  __IOM uint32_t I2C_FS_SCL_LCNT_REG;
743  __IOM uint32_t I2C_HS_SCL_HCNT_REG;
744  __IOM uint32_t I2C_HS_SCL_LCNT_REG;
745  __IOM uint32_t I2C_INTR_STAT_REG;
746  __IOM uint32_t I2C_INTR_MASK_REG;
747  __IOM uint32_t I2C_RAW_INTR_STAT_REG;
748  __IOM uint32_t I2C_RX_TL_REG;
749  __IOM uint32_t I2C_TX_TL_REG;
750  __IOM uint32_t I2C_CLR_INTR_REG;
751  __IOM uint32_t I2C_CLR_RX_UNDER_REG;
752  __IOM uint32_t I2C_CLR_RX_OVER_REG;
753  __IOM uint32_t I2C_CLR_TX_OVER_REG;
754  __IOM uint32_t I2C_CLR_RD_REQ_REG;
755  __IOM uint32_t I2C_CLR_TX_ABRT_REG;
756  __IOM uint32_t I2C_CLR_RX_DONE_REG;
757  __IOM uint32_t I2C_CLR_ACTIVITY_REG;
758  __IOM uint32_t I2C_CLR_STOP_DET_REG;
759  __IOM uint32_t I2C_CLR_START_DET_REG;
760  __IOM uint32_t I2C_CLR_GEN_CALL_REG;
761  __IOM uint32_t I2C_ENABLE_REG;
762  __IOM uint32_t I2C_STATUS_REG;
763  __IOM uint32_t I2C_TXFLR_REG;
764  __IOM uint32_t I2C_RXFLR_REG;
765  __IOM uint32_t I2C_SDA_HOLD_REG;
766  __IOM uint32_t I2C_TX_ABRT_SOURCE_REG;
767  __IM uint32_t RESERVED;
768  __IOM uint32_t I2C_DMA_CR_REG;
769  __IOM uint32_t I2C_DMA_TDLR_REG;
770  __IOM uint32_t I2C_DMA_RDLR_REG;
771  __IOM uint32_t I2C_SDA_SETUP_REG;
772  __IOM uint32_t I2C_ACK_GENERAL_CALL_REG;
773  __IOM uint32_t I2C_ENABLE_STATUS_REG;
774  __IOM uint32_t I2C_IC_FS_SPKLEN_REG;
775  __IOM uint32_t I2C_IC_HS_SPKLEN_REG;
776 } I2C_Type;
780 /* =========================================================================================================================== */
781 /* ================ MDCT ================ */
782 /* =========================================================================================================================== */
783 
784 
789 typedef struct {
790  __IOM uint32_t MDCT_CTRL_REG;
791  __IOM uint32_t MDCT_XBASE_ADDR_REG;
792  __IOM uint32_t MDCT_YBASE_ADDR_REG;
793  __IOM uint32_t MDCT_ZBASE_ADDR_REG;
794  __IOM uint32_t MDCT_STAGE0_REG;
795  __IOM uint32_t MDCT_STAGE1_REG;
796  __IOM uint32_t MDCT_STAGE2_REG;
797  __IOM uint32_t MDCT_STAGE3_REG;
798  __IOM uint32_t MDCT_STAGE4_REG;
799  __IOM uint32_t MDCT_STAGE5_REG;
800  __IOM uint32_t MDCT_STAGE6_REG;
801  __IOM uint32_t MDCT_STAGE7_REG;
802  __IOM uint32_t MDCT_PHASE_INC_REG;
803 } MDCT_Type;
807 /* =========================================================================================================================== */
808 /* ================ MEMCTRL ================ */
809 /* =========================================================================================================================== */
810 
811 
816 typedef struct {
817  __IM uint32_t RESERVED;
818  __IOM uint32_t MEM_PRIO_REG;
819  __IOM uint32_t MEM_STALL_REG;
820  __IOM uint32_t MEM_STATUS_REG;
821  __IOM uint32_t MEM_STATUS2_REG;
822  __IM uint32_t RESERVED1[3];
823  __IOM uint32_t CMI_CODE_BASE_REG;
824  __IOM uint32_t CMI_DATA_BASE_REG;
825  __IOM uint32_t CMI_SHARED_BASE_REG;
826  __IM uint32_t RESERVED2[18];
827  __IOM uint32_t BUSY_SET_REG;
828  __IOM uint32_t BUSY_RESET_REG;
829  __IOM uint32_t BUSY_STAT_REG;
830 } MEMCTRL_Type;
834 /* =========================================================================================================================== */
835 /* ================ PCM1 ================ */
836 /* =========================================================================================================================== */
837 
838 
843 typedef struct {
844  __IOM uint32_t PCM1_CTRL_REG;
845  __IOM uint32_t PCM1_IN1_REG;
846  __IOM uint32_t PCM1_IN2_REG;
847  __IOM uint32_t PCM1_OUT1_REG;
848  __IOM uint32_t PCM1_OUT2_REG;
849 } PCM1_Type;
853 /* =========================================================================================================================== */
854 /* ================ PDC ================ */
855 /* =========================================================================================================================== */
856 
857 
862 typedef struct {
863  __IOM uint32_t PDC_CTRL0_REG;
864  __IOM uint32_t PDC_CTRL1_REG;
865  __IOM uint32_t PDC_CTRL2_REG;
866  __IOM uint32_t PDC_CTRL3_REG;
867  __IOM uint32_t PDC_CTRL4_REG;
868  __IOM uint32_t PDC_CTRL5_REG;
869  __IOM uint32_t PDC_CTRL6_REG;
870  __IOM uint32_t PDC_CTRL7_REG;
871  __IOM uint32_t PDC_CTRL8_REG;
872  __IOM uint32_t PDC_CTRL9_REG;
873  __IOM uint32_t PDC_CTRL10_REG;
874  __IOM uint32_t PDC_CTRL11_REG;
875  __IM uint32_t RESERVED[20];
876  __IOM uint32_t PDC_ACKNOWLEDGE_REG;
877  __IOM uint32_t PDC_PENDING_REG;
878  __IM uint32_t RESERVED1;
879  __IOM uint32_t PDC_PENDING_CM33_REG;
880  __IOM uint32_t PDC_PENDING_CMAC_REG;
881  __IOM uint32_t PDC_SET_PENDING_REG;
882  __IOM uint32_t PDC_CONFIG_REG;
883 } PDC_Type;
887 /* =========================================================================================================================== */
888 /* ================ QSPIC ================ */
889 /* =========================================================================================================================== */
890 
891 
896 typedef struct {
897  __IOM uint32_t QSPIC_CTRLBUS_REG;
898  __IOM uint32_t QSPIC_CTRLMODE_REG;
899  __IOM uint32_t QSPIC_RECVDATA_REG;
900  __IOM uint32_t QSPIC_BURSTCMDA_REG;
902  __IOM uint32_t QSPIC_BURSTCMDB_REG;
904  __IOM uint32_t QSPIC_STATUS_REG;
905  __IOM uint32_t QSPIC_WRITEDATA_REG;
906  __IOM uint32_t QSPIC_READDATA_REG;
907  __IOM uint32_t QSPIC_DUMMYDATA_REG;
908  __IOM uint32_t QSPIC_ERASECTRL_REG;
909  __IOM uint32_t QSPIC_ERASECMDA_REG;
911  __IOM uint32_t QSPIC_ERASECMDB_REG;
913  __IOM uint32_t QSPIC_BURSTBRK_REG;
914  __IOM uint32_t QSPIC_STATUSCMD_REG;
916  __IOM uint32_t QSPIC_CHCKERASE_REG;
917  __IOM uint32_t QSPIC_GP_REG;
918  __IOM uint32_t QSPIC_AWRITECMD_REG;
920  __IOM uint32_t QSPIC_MEMBLEN_REG;
921 } QSPIC_Type;
925 /* =========================================================================================================================== */
926 /* ================ QUADEC ================ */
927 /* =========================================================================================================================== */
928 
929 
934 typedef struct {
935  __IOM uint32_t QDEC_CTRL_REG;
936  __IOM uint32_t QDEC_XCNT_REG;
937  __IOM uint32_t QDEC_YCNT_REG;
938  __IOM uint32_t QDEC_CLOCKDIV_REG;
939  __IOM uint32_t QDEC_CTRL2_REG;
940  __IOM uint32_t QDEC_ZCNT_REG;
941  __IOM uint32_t QDEC_EVENT_CNT_REG;
942 } QUADEC_Type;
946 /* =========================================================================================================================== */
947 /* ================ RTC ================ */
948 /* =========================================================================================================================== */
949 
950 
955 typedef struct {
956  __IOM uint32_t RTC_CONTROL_REG;
957  __IOM uint32_t RTC_HOUR_MODE_REG;
958  __IOM uint32_t RTC_TIME_REG;
959  __IOM uint32_t RTC_CALENDAR_REG;
960  __IOM uint32_t RTC_TIME_ALARM_REG;
961  __IOM uint32_t RTC_CALENDAR_ALARM_REG;
962  __IOM uint32_t RTC_ALARM_ENABLE_REG;
963  __IOM uint32_t RTC_EVENT_FLAGS_REG;
964  __IOM uint32_t RTC_INTERRUPT_ENABLE_REG;
965  __IOM uint32_t RTC_INTERRUPT_DISABLE_REG;
966  __IOM uint32_t RTC_INTERRUPT_MASK_REG;
967  __IOM uint32_t RTC_STATUS_REG;
968  __IOM uint32_t RTC_KEEP_RTC_REG;
969  __IM uint32_t RESERVED[19];
970  __IOM uint32_t RTC_EVENT_CTRL_REG;
971  __IM uint32_t RESERVED1;
972  __IOM uint32_t RTC_PDC_EVENT_PERIOD_REG;
973  __IOM uint32_t RTC_PDC_EVENT_CLEAR_REG;
974  __IM uint32_t RESERVED2;
975  __IOM uint32_t RTC_PDC_EVENT_CNT_REG;
976 } RTC_Type;
980 /* =========================================================================================================================== */
981 /* ================ SDADC ================ */
982 /* =========================================================================================================================== */
983 
984 
989 typedef struct {
990  __IOM uint32_t SDADC_CTRL_REG;
991  __IOM uint32_t SDADC_PGA_CTRL_REG;
992  __IM uint32_t RESERVED;
993  __IOM uint32_t SDADC_GAIN_CORR_REG;
994  __IOM uint32_t SDADC_OFFS_CORR_REG;
995  __IOM uint32_t SDADC_CLEAR_INT_REG;
996  __IOM uint32_t SDADC_RESULT_REG;
997  __IOM uint32_t SDADC_AUDIO_FILT_REG;
998 } SDADC_Type;
1002 /* =========================================================================================================================== */
1003 /* ================ SPI ================ */
1004 /* =========================================================================================================================== */
1005 
1006 
1011 typedef struct {
1012  __IOM uint32_t SPI_CTRL_REG;
1013  __IOM uint32_t SPI_CONFIG_REG;
1014  __IOM uint32_t SPI_CLOCK_REG;
1015  __IOM uint32_t SPI_FIFO_CONFIG_REG;
1016  __IOM uint32_t SPI_IRQ_MASK_REG;
1017  __IOM uint32_t SPI_STATUS_REG;
1018  __IOM uint32_t SPI_FIFO_STATUS_REG;
1019  __IOM uint32_t SPI_FIFO_READ_REG;
1020  __IOM uint32_t SPI_FIFO_WRITE_REG;
1021  __IOM uint32_t SPI_CS_CONFIG_REG;
1022  __IM uint32_t RESERVED;
1023  __IOM uint32_t SPI_TXBUFFER_FORCE_REG;
1024 } SPI_Type;
1028 /* =========================================================================================================================== */
1029 /* ================ SRC1 ================ */
1030 /* =========================================================================================================================== */
1031 
1032 
1037 typedef struct {
1038  __IOM uint32_t SRC1_CTRL_REG;
1039  __IOM uint32_t SRC1_IN_FS_REG;
1040  __IOM uint32_t SRC1_OUT_FS_REG;
1041  __IOM uint32_t SRC1_IN1_REG;
1042  __IOM uint32_t SRC1_IN2_REG;
1043  __IOM uint32_t SRC1_OUT1_REG;
1044  __IOM uint32_t SRC1_OUT2_REG;
1045  __IOM uint32_t SRC1_MUX_REG;
1046  __IOM uint32_t SRC1_COEF10_SET1_REG;
1047  __IOM uint32_t SRC1_COEF32_SET1_REG;
1048  __IOM uint32_t SRC1_COEF54_SET1_REG;
1049  __IOM uint32_t SRC1_COEF76_SET1_REG;
1050  __IOM uint32_t SRC1_COEF98_SET1_REG;
1051  __IOM uint32_t SRC1_COEF0A_SET1_REG;
1052 } SRC1_Type;
1056 /* =========================================================================================================================== */
1057 /* ================ SRC2 ================ */
1058 /* =========================================================================================================================== */
1059 
1060 
1065 typedef struct {
1066  __IOM uint32_t SRC2_CTRL_REG;
1067  __IOM uint32_t SRC2_IN_FS_REG;
1068  __IOM uint32_t SRC2_OUT_FS_REG;
1069  __IOM uint32_t SRC2_IN1_REG;
1070  __IOM uint32_t SRC2_IN2_REG;
1071  __IOM uint32_t SRC2_OUT1_REG;
1072  __IOM uint32_t SRC2_OUT2_REG;
1073  __IOM uint32_t SRC2_MUX_REG;
1074  __IOM uint32_t SRC2_COEF10_SET1_REG;
1075  __IOM uint32_t SRC2_COEF32_SET1_REG;
1076  __IOM uint32_t SRC2_COEF54_SET1_REG;
1077  __IOM uint32_t SRC2_COEF76_SET1_REG;
1078  __IOM uint32_t SRC2_COEF98_SET1_REG;
1079  __IOM uint32_t SRC2_COEF0A_SET1_REG;
1080 } SRC2_Type;
1084 /* =========================================================================================================================== */
1085 /* ================ SYS_WDOG ================ */
1086 /* =========================================================================================================================== */
1087 
1088 
1093 typedef struct {
1094  __IOM uint32_t WATCHDOG_REG;
1095  __IOM uint32_t WATCHDOG_CTRL_REG;
1096 } SYS_WDOG_Type;
1100 /* =========================================================================================================================== */
1101 /* ================ SYSB ================ */
1102 /* =========================================================================================================================== */
1103 
1104 
1109 typedef struct {
1110  __IOM uint32_t QSPI_ARB_REG;
1111  __IOM uint32_t BRIDGE_REG;
1112  __IOM uint32_t FLASH_ARB_REG;
1113 } SYSB_Type;
1117 /* =========================================================================================================================== */
1118 /* ================ TIMER ================ */
1119 /* =========================================================================================================================== */
1120 
1121 
1126 typedef struct {
1127  __IOM uint32_t TIMER_CTRL_REG;
1128  __IOM uint32_t TIMER_TIMER_VAL_REG;
1129  __IOM uint32_t TIMER_STATUS_REG;
1130  __IOM uint32_t TIMER_GPIO1_CONF_REG;
1131  __IOM uint32_t TIMER_GPIO2_CONF_REG;
1132  __IOM uint32_t TIMER_SETTINGS_REG;
1133  __IOM uint32_t TIMER_SHOTWIDTH_REG;
1134  __IM uint32_t RESERVED;
1135  __IOM uint32_t TIMER_CAPTURE_GPIO1_REG;
1136  __IOM uint32_t TIMER_CAPTURE_GPIO2_REG;
1137  __IOM uint32_t TIMER_PRESCALER_VAL_REG;
1138  __IOM uint32_t TIMER_PWM_CTRL_REG;
1139  __IM uint32_t RESERVED1;
1140  __IOM uint32_t TIMER_GPIO3_CONF_REG;
1141  __IOM uint32_t TIMER_GPIO4_CONF_REG;
1142  __IOM uint32_t TIMER_CAPTURE_GPIO3_REG;
1143  __IOM uint32_t TIMER_CAPTURE_GPIO4_REG;
1144  __IOM uint32_t TIMER_CLEAR_GPIO_EVENT_REG;
1145  __IOM uint32_t TIMER_CLEAR_IRQ_REG;
1146 } TIMER_Type;
1150 /* =========================================================================================================================== */
1151 /* ================ TIMER2 ================ */
1152 /* =========================================================================================================================== */
1153 
1154 
1159 typedef struct {
1160  __IOM uint32_t TIMER2_CTRL_REG;
1161  __IOM uint32_t TIMER2_TIMER_VAL_REG;
1162  __IOM uint32_t TIMER2_STATUS_REG;
1163  __IOM uint32_t TIMER2_GPIO1_CONF_REG;
1164  __IOM uint32_t TIMER2_GPIO2_CONF_REG;
1165  __IOM uint32_t TIMER2_SETTINGS_REG;
1166  __IOM uint32_t TIMER2_SHOTWIDTH_REG;
1167  __IM uint32_t RESERVED;
1168  __IOM uint32_t TIMER2_CAPTURE_GPIO1_REG;
1169  __IOM uint32_t TIMER2_CAPTURE_GPIO2_REG;
1170  __IOM uint32_t TIMER2_PRESCALER_VAL_REG;
1171  __IOM uint32_t TIMER2_PWM_CTRL_REG;
1172  __IM uint32_t RESERVED1;
1173  __IOM uint32_t TIMER2_CLEAR_IRQ_REG;
1174 } TIMER2_Type;
1178 /* =========================================================================================================================== */
1179 /* ================ TIMER3 ================ */
1180 /* =========================================================================================================================== */
1181 
1182 
1187 typedef struct {
1188  __IOM uint32_t TIMER3_CTRL_REG;
1189  __IOM uint32_t TIMER3_TIMER_VAL_REG;
1190  __IOM uint32_t TIMER3_STATUS_REG;
1191  __IOM uint32_t TIMER3_GPIO1_CONF_REG;
1192  __IOM uint32_t TIMER3_GPIO2_CONF_REG;
1193  __IOM uint32_t TIMER3_SETTINGS_REG;
1194  __IM uint32_t RESERVED[2];
1195  __IOM uint32_t TIMER3_CAPTURE_GPIO1_REG;
1196  __IOM uint32_t TIMER3_CAPTURE_GPIO2_REG;
1197  __IOM uint32_t TIMER3_PRESCALER_VAL_REG;
1198  __IOM uint32_t TIMER3_PWM_CTRL_REG;
1199  __IM uint32_t RESERVED1;
1200  __IOM uint32_t TIMER3_CLEAR_IRQ_REG;
1201 } TIMER3_Type;
1205 /* =========================================================================================================================== */
1206 /* ================ TIMER4 ================ */
1207 /* =========================================================================================================================== */
1208 
1209 
1214 typedef struct {
1215  __IOM uint32_t TIMER4_CTRL_REG;
1216  __IOM uint32_t TIMER4_TIMER_VAL_REG;
1217  __IOM uint32_t TIMER4_STATUS_REG;
1218  __IOM uint32_t TIMER4_GPIO1_CONF_REG;
1219  __IOM uint32_t TIMER4_GPIO2_CONF_REG;
1220  __IOM uint32_t TIMER4_SETTINGS_REG;
1221  __IM uint32_t RESERVED[2];
1222  __IOM uint32_t TIMER4_CAPTURE_GPIO1_REG;
1223  __IOM uint32_t TIMER4_CAPTURE_GPIO2_REG;
1224  __IOM uint32_t TIMER4_PRESCALER_VAL_REG;
1225  __IOM uint32_t TIMER4_PWM_CTRL_REG;
1226  __IM uint32_t RESERVED1;
1227  __IOM uint32_t TIMER4_CLEAR_IRQ_REG;
1228 } TIMER4_Type;
1232 /* =========================================================================================================================== */
1233 /* ================ UART ================ */
1234 /* =========================================================================================================================== */
1235 
1236 
1241 typedef struct {
1242  __IOM uint32_t UART_RBR_THR_DLL_REG;
1243  __IOM uint32_t UART_IER_DLH_REG;
1244  __IOM uint32_t UART_IIR_FCR_REG;
1246  __IOM uint32_t UART_LCR_REG;
1247  __IOM uint32_t UART_MCR_REG;
1248  __IOM uint32_t UART_LSR_REG;
1249  __IM uint32_t RESERVED;
1250  __IOM uint32_t UART_SCR_REG;
1251  __IM uint32_t RESERVED1[4];
1252  __IOM uint32_t UART_SRBR_STHR0_REG;
1253  __IOM uint32_t UART_SRBR_STHR1_REG;
1254  __IOM uint32_t UART_SRBR_STHR2_REG;
1255  __IOM uint32_t UART_SRBR_STHR3_REG;
1256  __IOM uint32_t UART_SRBR_STHR4_REG;
1257  __IOM uint32_t UART_SRBR_STHR5_REG;
1258  __IOM uint32_t UART_SRBR_STHR6_REG;
1259  __IOM uint32_t UART_SRBR_STHR7_REG;
1260  __IOM uint32_t UART_SRBR_STHR8_REG;
1261  __IOM uint32_t UART_SRBR_STHR9_REG;
1262  __IOM uint32_t UART_SRBR_STHR10_REG;
1263  __IOM uint32_t UART_SRBR_STHR11_REG;
1264  __IOM uint32_t UART_SRBR_STHR12_REG;
1265  __IOM uint32_t UART_SRBR_STHR13_REG;
1266  __IOM uint32_t UART_SRBR_STHR14_REG;
1267  __IOM uint32_t UART_SRBR_STHR15_REG;
1268  __IM uint32_t RESERVED2[3];
1269  __IOM uint32_t UART_USR_REG;
1270  __IOM uint32_t UART_TFL_REG;
1271  __IOM uint32_t UART_RFL_REG;
1272  __IOM uint32_t UART_SRR_REG;
1273  __IM uint32_t RESERVED3;
1274  __IOM uint32_t UART_SBCR_REG;
1275  __IOM uint32_t UART_SDMAM_REG;
1276  __IOM uint32_t UART_SFE_REG;
1277  __IOM uint32_t UART_SRT_REG;
1278  __IOM uint32_t UART_STET_REG;
1279  __IOM uint32_t UART_HTX_REG;
1280  __IOM uint32_t UART_DMASA_REG;
1281  __IM uint32_t RESERVED4[5];
1282  __IOM uint32_t UART_DLF_REG;
1283  __IM uint32_t RESERVED5[13];
1284  __IOM uint32_t UART_UCV_REG;
1285  __IOM uint32_t UART_CTR_REG;
1286 } UART_Type;
1290 /* =========================================================================================================================== */
1291 /* ================ UART2 ================ */
1292 /* =========================================================================================================================== */
1293 
1294 
1299 typedef struct {
1300  __IOM uint32_t UART2_RBR_THR_DLL_REG;
1301  __IOM uint32_t UART2_IER_DLH_REG;
1302  __IOM uint32_t UART2_IIR_FCR_REG;
1304  __IOM uint32_t UART2_LCR_REG;
1305  __IOM uint32_t UART2_MCR_REG;
1306  __IOM uint32_t UART2_LSR_REG;
1307  __IOM uint32_t UART2_MSR_REG;
1308  __IOM uint32_t UART2_CONFIG_REG;
1309  __IM uint32_t RESERVED[4];
1310  __IOM uint32_t UART2_SRBR_STHR0_REG;
1311  __IOM uint32_t UART2_SRBR_STHR1_REG;
1312  __IOM uint32_t UART2_SRBR_STHR2_REG;
1313  __IOM uint32_t UART2_SRBR_STHR3_REG;
1314  __IOM uint32_t UART2_SRBR_STHR4_REG;
1315  __IOM uint32_t UART2_SRBR_STHR5_REG;
1316  __IOM uint32_t UART2_SRBR_STHR6_REG;
1317  __IOM uint32_t UART2_SRBR_STHR7_REG;
1318  __IOM uint32_t UART2_SRBR_STHR8_REG;
1319  __IOM uint32_t UART2_SRBR_STHR9_REG;
1320  __IOM uint32_t UART2_SRBR_STHR10_REG;
1321  __IOM uint32_t UART2_SRBR_STHR11_REG;
1322  __IOM uint32_t UART2_SRBR_STHR12_REG;
1323  __IOM uint32_t UART2_SRBR_STHR13_REG;
1324  __IOM uint32_t UART2_SRBR_STHR14_REG;
1325  __IOM uint32_t UART2_SRBR_STHR15_REG;
1326  __IM uint32_t RESERVED1[3];
1327  __IOM uint32_t UART2_USR_REG;
1328  __IOM uint32_t UART2_TFL_REG;
1329  __IOM uint32_t UART2_RFL_REG;
1330  __IOM uint32_t UART2_SRR_REG;
1331  __IOM uint32_t UART2_SRTS_REG;
1332  __IOM uint32_t UART2_SBCR_REG;
1333  __IOM uint32_t UART2_SDMAM_REG;
1334  __IOM uint32_t UART2_SFE_REG;
1335  __IOM uint32_t UART2_SRT_REG;
1336  __IOM uint32_t UART2_STET_REG;
1337  __IOM uint32_t UART2_HTX_REG;
1338  __IOM uint32_t UART2_DMASA_REG;
1339  __IM uint32_t RESERVED2[5];
1340  __IOM uint32_t UART2_DLF_REG;
1341  __IOM uint32_t UART2_RAR_REG;
1342  __IOM uint32_t UART2_TAR_REG;
1343  __IOM uint32_t UART2_LCR_EXT;
1344  __IM uint32_t RESERVED3[4];
1345  __IOM uint32_t UART2_CTRL_REG;
1346  __IOM uint32_t UART2_TIMER_REG;
1347  __IOM uint32_t UART2_ERR_CTRL_REG;
1348  __IOM uint32_t UART2_IRQ_STATUS_REG;
1349  __IM uint32_t RESERVED4[2];
1350  __IOM uint32_t UART2_UCV_REG;
1351  __IOM uint32_t UART2_CTR_REG;
1352 } UART2_Type;
1356 /* =========================================================================================================================== */
1357 /* ================ WAKEUP ================ */
1358 /* =========================================================================================================================== */
1359 
1360 
1365 typedef struct {
1366  __IOM uint32_t WKUP_CTRL_REG;
1367  __IM uint32_t RESERVED;
1368  __IOM uint32_t WKUP_RESET_IRQ_REG;
1369  __IM uint32_t RESERVED1[2];
1370  __IOM uint32_t WKUP_SELECT_P0_REG;
1372  __IOM uint32_t WKUP_SELECT_P1_REG;
1374  __IM uint32_t RESERVED2[3];
1375  __IOM uint32_t WKUP_POL_P0_REG;
1376  __IOM uint32_t WKUP_POL_P1_REG;
1377  __IM uint32_t RESERVED3[3];
1378  __IOM uint32_t WKUP_STATUS_P0_REG;
1379  __IOM uint32_t WKUP_STATUS_P1_REG;
1380  __IM uint32_t RESERVED4;
1381  __IOM uint32_t WKUP_CLEAR_P0_REG;
1382  __IOM uint32_t WKUP_CLEAR_P1_REG;
1383  __IM uint32_t RESERVED5;
1384  __IOM uint32_t WKUP_SEL_GPIO_P0_REG;
1385  __IOM uint32_t WKUP_SEL_GPIO_P1_REG;
1386  __IOM uint32_t WKUP_SEL1_GPIO_P0_REG;
1388  __IOM uint32_t WKUP_SEL1_GPIO_P1_REG;
1390 } WAKEUP_Type; /* End of group Device_Peripheral_peripherals */
1394 
1395 
1396 /* =========================================================================================================================== */
1397 /* ================ Device Specific Peripheral Address Map ================ */
1398 /* =========================================================================================================================== */
1399 
1400 
1405 #define AES_HASH_BASE 0x30040000UL
1406 #define ANAMISC_BIF_BASE 0x50040B00UL
1407 #define CACHE_BASE 0x1A0C0000UL
1408 #define CHIP_VERSION_BASE 0x50050200UL
1409 #define CMAC_CACHE_BASE 0x1A1C0000UL
1410 #define CRG_AUD_BASE 0x50030000UL
1411 #define CRG_COM_BASE 0x50020500UL
1412 #define CRG_PER_BASE 0x50040C00UL
1413 #define CRG_SYS_BASE 0x50050500UL
1414 #define CRG_TOP_BASE 0x50000000UL
1415 #define CRG_XTAL_BASE 0x50010000UL
1416 #define DCDC_BASE 0x50000300UL
1417 #define DMA_BASE 0x50060200UL
1418 #define DW_BASE 0x30020000UL
1419 #define FCU_BASE 0x50060100UL
1420 #define GPADC_BASE 0x50040900UL
1421 #define GPIO_BASE 0x50020600UL
1422 #define GPREG_BASE 0x50050300UL
1423 #define I2C_BASE 0x50020300UL
1424 #define MDCT_BASE 0x50030400UL
1425 #define MEMCTRL_BASE 0x50060000UL
1426 #define PCM1_BASE 0x50030300UL
1427 #define PDC_BASE 0x50000200UL
1428 #define QSPIC_BASE 0x34000000UL
1429 #define QUADEC_BASE 0x50000500UL
1430 #define RTC_BASE 0x50000400UL
1431 #define SDADC_BASE 0x50020400UL
1432 #define SPI_BASE 0x50020200UL
1433 #define SRC1_BASE 0x50030100UL
1434 #define SRC2_BASE 0x50030200UL
1435 #define SYS_WDOG_BASE 0x50000700UL
1436 #define SYSB_BASE 0x50060400UL
1437 #define TIMER_BASE 0x50010300UL
1438 #define TIMER2_BASE 0x50010400UL
1439 #define TIMER3_BASE 0x50010500UL
1440 #define TIMER4_BASE 0x50020A00UL
1441 #define UART_BASE 0x50020000UL
1442 #define UART2_BASE 0x50020100UL
1443 #define WAKEUP_BASE 0x50000100UL
1444  /* End of group Device_Peripheral_peripheralAddr */
1446 
1447 
1448 /* =========================================================================================================================== */
1449 /* ================ Peripheral declaration ================ */
1450 /* =========================================================================================================================== */
1451 
1452 
1457 #define AES_HASH ((AES_HASH_Type*) AES_HASH_BASE)
1458 #define ANAMISC_BIF ((ANAMISC_BIF_Type*) ANAMISC_BIF_BASE)
1459 #define CACHE ((CACHE_Type*) CACHE_BASE)
1460 #define CHIP_VERSION ((CHIP_VERSION_Type*) CHIP_VERSION_BASE)
1461 #define CMAC_CACHE ((CMAC_CACHE_Type*) CMAC_CACHE_BASE)
1462 #define CRG_AUD ((CRG_AUD_Type*) CRG_AUD_BASE)
1463 #define CRG_COM ((CRG_COM_Type*) CRG_COM_BASE)
1464 #define CRG_PER ((CRG_PER_Type*) CRG_PER_BASE)
1465 #define CRG_SYS ((CRG_SYS_Type*) CRG_SYS_BASE)
1466 #define CRG_TOP ((CRG_TOP_Type*) CRG_TOP_BASE)
1467 #define CRG_XTAL ((CRG_XTAL_Type*) CRG_XTAL_BASE)
1468 #define DCDC ((DCDC_Type*) DCDC_BASE)
1469 #define DMA ((DMA_Type*) DMA_BASE)
1470 #define DW ((DW_Type*) DW_BASE)
1471 #define FCU ((FCU_Type*) FCU_BASE)
1472 #define GPADC ((GPADC_Type*) GPADC_BASE)
1473 #define GPIO ((GPIO_Type*) GPIO_BASE)
1474 #define GPREG ((GPREG_Type*) GPREG_BASE)
1475 #define I2C ((I2C_Type*) I2C_BASE)
1476 #define MDCT ((MDCT_Type*) MDCT_BASE)
1477 #define MEMCTRL ((MEMCTRL_Type*) MEMCTRL_BASE)
1478 #define PCM1 ((PCM1_Type*) PCM1_BASE)
1479 #define PDC ((PDC_Type*) PDC_BASE)
1480 #define QSPIC ((QSPIC_Type*) QSPIC_BASE)
1481 #define QUADEC ((QUADEC_Type*) QUADEC_BASE)
1482 #define RTC ((RTC_Type*) RTC_BASE)
1483 #define SDADC ((SDADC_Type*) SDADC_BASE)
1484 #define SPI ((SPI_Type*) SPI_BASE)
1485 #define SRC1 ((SRC1_Type*) SRC1_BASE)
1486 #define SRC2 ((SRC2_Type*) SRC2_BASE)
1487 #define SYS_WDOG ((SYS_WDOG_Type*) SYS_WDOG_BASE)
1488 #define SYSB ((SYSB_Type*) SYSB_BASE)
1489 #define TIMER ((TIMER_Type*) TIMER_BASE)
1490 #define TIMER2 ((TIMER2_Type*) TIMER2_BASE)
1491 #define TIMER3 ((TIMER3_Type*) TIMER3_BASE)
1492 #define TIMER4 ((TIMER4_Type*) TIMER4_BASE)
1493 #define UART ((UART_Type*) UART_BASE)
1494 #define UART2 ((UART2_Type*) UART2_BASE)
1495 #define WAKEUP ((WAKEUP_Type*) WAKEUP_BASE)
1496  /* End of group Device_Peripheral_declaration */
1498 
1499 
1500 /* =========================================================================================================================== */
1501 /* ================ Pos/Mask Peripheral Section ================ */
1502 /* =========================================================================================================================== */
1503 
1504 
1511 /* =========================================================================================================================== */
1512 /* ================ AES_HASH ================ */
1513 /* =========================================================================================================================== */
1514 
1515 /* =================================================== CRYPTO_CLRIRQ_REG =================================================== */
1516 #define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL)
1517 #define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL)
1518 /* ==================================================== CRYPTO_CTRL_REG ==================================================== */
1519 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (16UL)
1520 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x10000UL)
1521 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (15UL)
1522 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x8000UL)
1523 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL)
1524 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0x7c00UL)
1525 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL)
1526 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL)
1527 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL)
1528 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL)
1529 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL)
1530 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL)
1531 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL)
1532 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL)
1533 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL)
1534 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL)
1535 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL)
1536 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL)
1537 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL)
1538 #define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL)
1539 /* ================================================= CRYPTO_DEST_ADDR_REG ================================================== */
1540 #define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL)
1541 #define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL)
1542 /* ================================================= CRYPTO_FETCH_ADDR_REG ================================================= */
1543 #define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL)
1544 #define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL)
1545 /* =================================================== CRYPTO_KEYS_START =================================================== */
1546 #define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL)
1547 #define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL)
1548 /* ==================================================== CRYPTO_LEN_REG ===================================================== */
1549 #define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL)
1550 #define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL)
1551 /* =================================================== CRYPTO_MREG0_REG ==================================================== */
1552 #define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL)
1553 #define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL)
1554 /* =================================================== CRYPTO_MREG1_REG ==================================================== */
1555 #define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL)
1556 #define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL)
1557 /* =================================================== CRYPTO_MREG2_REG ==================================================== */
1558 #define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL)
1559 #define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL)
1560 /* =================================================== CRYPTO_MREG3_REG ==================================================== */
1561 #define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL)
1562 #define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL)
1563 /* =================================================== CRYPTO_START_REG ==================================================== */
1564 #define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL)
1565 #define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL)
1566 /* =================================================== CRYPTO_STATUS_REG =================================================== */
1567 #define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL)
1568 #define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL)
1569 #define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL)
1570 #define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL)
1571 #define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL)
1572 #define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL)
1575 /* =========================================================================================================================== */
1576 /* ================ ANAMISC_BIF ================ */
1577 /* =========================================================================================================================== */
1578 
1579 /* ==================================================== CLK_CAL_IRQ_REG ==================================================== */
1580 #define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Pos (2UL)
1581 #define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Msk (0x4UL)
1582 #define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Pos (1UL)
1583 #define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Msk (0x2UL)
1584 #define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Pos (0UL)
1585 #define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Msk (0x1UL)
1586 /* ==================================================== CLK_REF_CNT_REG ==================================================== */
1587 #define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL)
1588 #define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL)
1589 /* ==================================================== CLK_REF_SEL_REG ==================================================== */
1590 #define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL)
1591 #define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL)
1592 #define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL)
1593 #define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL)
1594 #define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL)
1595 #define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL)
1596 #define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL)
1597 #define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL)
1598 /* ==================================================== CLK_REF_VAL_REG ==================================================== */
1599 #define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL)
1600 #define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL)
1603 /* =========================================================================================================================== */
1604 /* ================ CACHE ================ */
1605 /* =========================================================================================================================== */
1606 
1607 /* ==================================================== CACHE_CTRL2_REG ==================================================== */
1608 #define CACHE_CACHE_CTRL2_REG_CACHE_READY_Pos (28UL)
1609 #define CACHE_CACHE_CTRL2_REG_CACHE_READY_Msk (0x10000000UL)
1610 #define CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (27UL)
1611 #define CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x8000000UL)
1612 #define CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos (17UL)
1613 #define CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk (0x3fe0000UL)
1614 #define CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (16UL)
1615 #define CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x10000UL)
1616 #define CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (14UL)
1617 #define CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0xc000UL)
1618 #define CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (13UL)
1619 #define CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x2000UL)
1620 #define CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (12UL)
1621 #define CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x1000UL)
1622 #define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)
1623 #define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)
1624 #define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)
1625 #define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)
1626 #define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)
1627 #define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)
1628 /* =================================================== CACHE_EFLASH_REG ==================================================== */
1629 #define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos (16UL)
1630 #define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk (0xffff0000UL)
1631 #define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos (4UL)
1632 #define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk (0xfff0UL)
1633 #define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos (0UL)
1634 #define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk (0x7UL)
1635 /* ==================================================== CACHE_FLASH_REG ==================================================== */
1636 #define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)
1637 #define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)
1638 #define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)
1639 #define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)
1640 #define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)
1641 #define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)
1642 /* ================================================== CACHE_MRM_CTRL_REG =================================================== */
1643 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL)
1644 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL)
1645 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL)
1646 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL)
1647 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)
1648 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)
1649 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)
1650 #define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)
1651 #define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)
1652 #define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)
1653 /* ================================================= CACHE_MRM_HITS1WS_REG ================================================= */
1654 #define CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL)
1655 #define CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL)
1656 /* ================================================== CACHE_MRM_HITS_REG =================================================== */
1657 #define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)
1658 #define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)
1659 /* =============================================== CACHE_MRM_HITS_THRES_REG ================================================ */
1660 #define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)
1661 #define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL)
1662 /* ================================================= CACHE_MRM_MISSES_REG ================================================== */
1663 #define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)
1664 #define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)
1665 /* ============================================== CACHE_MRM_MISSES_THRES_REG =============================================== */
1666 #define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL)
1667 #define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL)
1668 /* ================================================== CACHE_MRM_TINT_REG =================================================== */
1669 #define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)
1670 #define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)
1671 /* ===================================================== SWD_RESET_REG ===================================================== */
1672 #define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)
1673 #define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)
1676 /* =========================================================================================================================== */
1677 /* ================ CHIP_VERSION ================ */
1678 /* =========================================================================================================================== */
1679 
1680 /* ===================================================== CHIP_ID1_REG ====================================================== */
1681 #define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL)
1682 #define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL)
1683 /* ===================================================== CHIP_ID2_REG ====================================================== */
1684 #define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL)
1685 #define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL)
1686 /* ===================================================== CHIP_ID3_REG ====================================================== */
1687 #define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL)
1688 #define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL)
1689 /* ===================================================== CHIP_ID4_REG ====================================================== */
1690 #define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL)
1691 #define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL)
1692 /* =================================================== CHIP_REVISION_REG =================================================== */
1693 #define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL)
1694 #define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL)
1695 /* ===================================================== CHIP_SWC_REG ====================================================== */
1696 #define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL)
1697 #define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL)
1698 /* ==================================================== CHIP_TEST1_REG ===================================================== */
1699 #define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL)
1700 #define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL)
1701 /* ==================================================== CHIP_TEST2_REG ===================================================== */
1702 #define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL)
1703 #define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL)
1706 /* =========================================================================================================================== */
1707 /* ================ CMAC_CACHE ================ */
1708 /* =========================================================================================================================== */
1709 
1710 /* ================================================== CM_CACHE_CTRL2_REG =================================================== */
1711 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Pos (28UL)
1712 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Msk (0x10000000UL)
1713 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (27UL)
1714 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x8000000UL)
1715 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos (17UL)
1716 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk (0x3fe0000UL)
1717 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (16UL)
1718 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x10000UL)
1719 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (14UL)
1720 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0xc000UL)
1721 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (13UL)
1722 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x2000UL)
1723 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (12UL)
1724 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x1000UL)
1725 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)
1726 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)
1727 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)
1728 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)
1729 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)
1730 #define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)
1731 /* ================================================== CM_CACHE_EFLASH_REG ================================================== */
1732 #define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos (16UL)
1733 #define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk (0xffff0000UL)
1734 #define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos (4UL)
1735 #define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk (0xfff0UL)
1736 #define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos (0UL)
1737 #define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk (0x7UL)
1738 /* ================================================== CM_CACHE_FLASH_REG =================================================== */
1739 #define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)
1740 #define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)
1741 #define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)
1742 #define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)
1743 #define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)
1744 #define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)
1745 /* ================================================= CM_CACHE_MRM_CTRL_REG ================================================= */
1746 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL)
1747 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL)
1748 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL)
1749 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL)
1750 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)
1751 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)
1752 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)
1753 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)
1754 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)
1755 #define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)
1756 /* =============================================== CM_CACHE_MRM_HITS1WS_REG ================================================ */
1757 #define CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL)
1758 #define CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL)
1759 /* ================================================= CM_CACHE_MRM_HITS_REG ================================================= */
1760 #define CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)
1761 #define CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)
1762 /* ============================================== CM_CACHE_MRM_HITS_THRES_REG ============================================== */
1763 #define CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)
1764 #define CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL)
1765 /* ================================================ CM_CACHE_MRM_MISSES_REG ================================================ */
1766 #define CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)
1767 #define CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)
1768 /* ============================================= CM_CACHE_MRM_MISSES_THRES_REG ============================================= */
1769 #define CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL)
1770 #define CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL)
1771 /* ================================================= CM_CACHE_MRM_TINT_REG ================================================= */
1772 #define CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)
1773 #define CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)
1774 /* ================================================== CM_CACHE_RESET_REG =================================================== */
1775 #define CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)
1776 #define CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)
1779 /* =========================================================================================================================== */
1780 /* ================ CRG_AUD ================ */
1781 /* =========================================================================================================================== */
1782 
1783 /* ====================================================== PCM_DIV_REG ====================================================== */
1784 #define CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL)
1785 #define CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL)
1786 #define CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL)
1787 #define CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL)
1788 #define CRG_AUD_PCM_DIV_REG_PCM_DIV_Pos (0UL)
1789 #define CRG_AUD_PCM_DIV_REG_PCM_DIV_Msk (0xfffUL)
1790 /* ===================================================== PCM_FDIV_REG ====================================================== */
1791 #define CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Pos (0UL)
1792 #define CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL)
1793 /* ====================================================== PDM_DIV_REG ====================================================== */
1794 #define CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL)
1795 #define CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL)
1796 #define CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL)
1797 #define CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL)
1798 #define CRG_AUD_PDM_DIV_REG_PDM_DIV_Pos (0UL)
1799 #define CRG_AUD_PDM_DIV_REG_PDM_DIV_Msk (0xffUL)
1800 /* ====================================================== SRC_DIV_REG ====================================================== */
1801 #define CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Pos (17UL)
1802 #define CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Msk (0x20000UL)
1803 #define CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Pos (16UL)
1804 #define CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Msk (0x10000UL)
1805 #define CRG_AUD_SRC_DIV_REG_SRC2_DIV_Pos (8UL)
1806 #define CRG_AUD_SRC_DIV_REG_SRC2_DIV_Msk (0xff00UL)
1807 #define CRG_AUD_SRC_DIV_REG_SRC_DIV_Pos (0UL)
1808 #define CRG_AUD_SRC_DIV_REG_SRC_DIV_Msk (0xffUL)
1811 /* =========================================================================================================================== */
1812 /* ================ CRG_COM ================ */
1813 /* =========================================================================================================================== */
1814 
1815 /* ====================================================== CLK_COM_REG ====================================================== */
1816 #define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)
1817 #define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)
1818 #define CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos (6UL)
1819 #define CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)
1820 #define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)
1821 #define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)
1822 #define CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos (4UL)
1823 #define CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)
1824 #define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)
1825 #define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)
1826 #define CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos (2UL)
1827 #define CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)
1828 #define CRG_COM_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)
1829 #define CRG_COM_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)
1830 #define CRG_COM_CLK_COM_REG_UART_ENABLE_Pos (0UL)
1831 #define CRG_COM_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)
1832 /* =================================================== RESET_CLK_COM_REG =================================================== */
1833 #define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)
1834 #define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)
1835 #define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos (6UL)
1836 #define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)
1837 #define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)
1838 #define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)
1839 #define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos (4UL)
1840 #define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)
1841 #define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)
1842 #define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)
1843 #define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos (2UL)
1844 #define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)
1845 #define CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)
1846 #define CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)
1847 #define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos (0UL)
1848 #define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)
1849 /* ==================================================== SET_CLK_COM_REG ==================================================== */
1850 #define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)
1851 #define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)
1852 #define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos (6UL)
1853 #define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)
1854 #define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)
1855 #define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)
1856 #define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos (4UL)
1857 #define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)
1858 #define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)
1859 #define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)
1860 #define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos (2UL)
1861 #define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)
1862 #define CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)
1863 #define CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)
1864 #define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos (0UL)
1865 #define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)
1868 /* =========================================================================================================================== */
1869 /* ================ CRG_PER ================ */
1870 /* =========================================================================================================================== */
1871 
1872 /* ====================================================== CLK_PER_REG ====================================================== */
1873 #define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)
1874 #define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)
1875 /* =================================================== RESET_CLK_PER_REG =================================================== */
1876 #define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)
1877 #define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)
1878 /* ==================================================== SET_CLK_PER_REG ==================================================== */
1879 #define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)
1880 #define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)
1883 /* =========================================================================================================================== */
1884 /* ================ CRG_SYS ================ */
1885 /* =========================================================================================================================== */
1886 
1887 /* ====================================================== CLK_SYS_REG ====================================================== */
1888 
1889 
1890 /* =========================================================================================================================== */
1891 /* ================ CRG_TOP ================ */
1892 /* =========================================================================================================================== */
1893 
1894 /* ==================================================== ANA_STATUS_REG ===================================================== */
1895 #define CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Pos (8UL)
1896 #define CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Msk (0x100UL)
1897 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Pos (7UL)
1898 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Msk (0x80UL)
1899 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Pos (6UL)
1900 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Msk (0x40UL)
1901 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Pos (5UL)
1902 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Msk (0x20UL)
1903 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Pos (4UL)
1904 #define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Msk (0x10UL)
1905 #define CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Pos (3UL)
1906 #define CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Msk (0x8UL)
1907 #define CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Pos (2UL)
1908 #define CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Msk (0x4UL)
1909 #define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (1UL)
1910 #define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x2UL)
1911 #define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (0UL)
1912 #define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x1UL)
1913 /* ====================================================== BANDGAP_REG ====================================================== */
1914 #define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (6UL)
1915 #define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0x7c0UL)
1916 #define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos (0UL)
1917 #define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk (0x1fUL)
1918 /* =================================================== BIAS_VREF_SEL_REG =================================================== */
1919 #define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos (4UL)
1920 #define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk (0xf0UL)
1921 #define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos (0UL)
1922 #define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk (0xfUL)
1923 /* ===================================================== BOD_CTRL_REG ====================================================== */
1924 #define CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Pos (8UL)
1925 #define CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Msk (0x100UL)
1926 #define CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Pos (7UL)
1927 #define CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Msk (0x80UL)
1928 #define CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Pos (6UL)
1929 #define CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Msk (0x40UL)
1930 #define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Pos (4UL)
1931 #define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Msk (0x10UL)
1932 #define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Pos (3UL)
1933 #define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Msk (0x8UL)
1934 #define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Pos (2UL)
1935 #define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Msk (0x4UL)
1936 #define CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Pos (0UL)
1937 #define CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Msk (0x3UL)
1938 /* ===================================================== CLK_AMBA_REG ====================================================== */
1939 #define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL)
1940 #define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL)
1941 #define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL)
1942 #define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL)
1943 #define CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Pos (7UL)
1944 #define CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Msk (0x80UL)
1945 #define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL)
1946 #define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL)
1947 #define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL)
1948 #define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL)
1949 #define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL)
1950 #define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL)
1951 /* ===================================================== CLK_CTRL_REG ====================================================== */
1952 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Pos (15UL)
1953 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Msk (0x8000UL)
1954 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos (14UL)
1955 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk (0x4000UL)
1956 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos (13UL)
1957 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk (0x2000UL)
1958 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (12UL)
1959 #define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x1000UL)
1960 #define CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Pos (5UL)
1961 #define CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Msk (0x20UL)
1962 #define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos (2UL)
1963 #define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk (0xcUL)
1964 #define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL)
1965 #define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL)
1966 /* ===================================================== CLK_RADIO_REG ===================================================== */
1967 #define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (3UL)
1968 #define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x8UL)
1969 #define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos (2UL)
1970 #define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk (0x4UL)
1971 #define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos (1UL)
1972 #define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk (0x2UL)
1973 #define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos (0UL)
1974 #define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk (0x1UL)
1975 /* ===================================================== CLK_RC32M_REG ===================================================== */
1976 #define CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Pos (7UL)
1977 #define CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Msk (0x780UL)
1978 #define CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Pos (5UL)
1979 #define CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Msk (0x60UL)
1980 #define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos (1UL)
1981 #define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk (0x1eUL)
1982 #define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos (0UL)
1983 #define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk (0x1UL)
1984 /* ===================================================== CLK_RCLP_REG ====================================================== */
1985 #define CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Pos (3UL)
1986 #define CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Msk (0x78UL)
1987 #define CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Pos (2UL)
1988 #define CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Msk (0x4UL)
1989 #define CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Pos (1UL)
1990 #define CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Msk (0x2UL)
1991 #define CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Pos (0UL)
1992 #define CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Msk (0x1UL)
1993 /* ====================================================== CLK_RCX_REG ====================================================== */
1994 #define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos (7UL)
1995 #define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk (0x780UL)
1996 #define CRG_TOP_CLK_RCX_REG_RCX_C0_Pos (6UL)
1997 #define CRG_TOP_CLK_RCX_REG_RCX_C0_Msk (0x40UL)
1998 #define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos (1UL)
1999 #define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk (0x3eUL)
2000 #define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos (0UL)
2001 #define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk (0x1UL)
2002 /* ==================================================== CLK_RTCDIV_REG ===================================================== */
2003 #define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos (21UL)
2004 #define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk (0x200000UL)
2005 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos (20UL)
2006 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk (0x100000UL)
2007 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos (19UL)
2008 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk (0x80000UL)
2009 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos (10UL)
2010 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk (0x7fc00UL)
2011 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos (0UL)
2012 #define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk (0x3ffUL)
2013 /* ================================================== CLK_SWITCH2XTAL_REG ================================================== */
2014 #define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos (0UL)
2015 #define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk (0x1UL)
2016 /* ====================================================== CLK_TMR_REG ====================================================== */
2017 #define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos (2UL)
2018 #define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk (0x4UL)
2019 #define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos (1UL)
2020 #define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk (0x2UL)
2021 #define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (0UL)
2022 #define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x1UL)
2023 /* ==================================================== CLK_XTAL32K_REG ==================================================== */
2024 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Pos (9UL)
2025 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Msk (0x1e00UL)
2026 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos (7UL)
2027 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x80UL)
2028 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos (3UL)
2029 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk (0x78UL)
2030 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos (1UL)
2031 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk (0x6UL)
2032 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos (0UL)
2033 #define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk (0x1UL)
2034 /* ================================================== DISCHARGE_RAIL_REG =================================================== */
2035 #define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Pos (2UL)
2036 #define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Msk (0x4UL)
2037 #define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Pos (1UL)
2038 #define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Msk (0x2UL)
2039 #define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Pos (0UL)
2040 #define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Msk (0x1UL)
2041 /* ==================================================== HIBERN_CTRL_REG ==================================================== */
2042 #define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Pos (4UL)
2043 #define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Msk (0x30UL)
2044 #define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Pos (2UL)
2045 #define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Msk (0xcUL)
2046 #define CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Pos (0UL)
2047 #define CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Msk (0x1UL)
2048 /* =================================================== P0_PAD_LATCH_REG ==================================================== */
2049 #define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos (0UL)
2050 #define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk (0xffffUL)
2051 /* ================================================ P0_RESET_PAD_LATCH_REG ================================================= */
2052 #define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos (0UL)
2053 #define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk (0xffffUL)
2054 /* ================================================= P0_SET_PAD_LATCH_REG ================================================== */
2055 #define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos (0UL)
2056 #define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk (0xffffUL)
2057 /* =================================================== P1_PAD_LATCH_REG ==================================================== */
2058 #define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos (0UL)
2059 #define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk (0xffffUL)
2060 /* ================================================ P1_RESET_PAD_LATCH_REG ================================================= */
2061 #define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos (0UL)
2062 #define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk (0xffffUL)
2063 /* ================================================= P1_SET_PAD_LATCH_REG ================================================== */
2064 #define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos (0UL)
2065 #define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk (0xffffUL)
2066 /* ===================================================== PMU_CTRL_REG ====================================================== */
2067 #define CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Pos (11UL)
2068 #define CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Msk (0x800UL)
2069 #define CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Pos (10UL)
2070 #define CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Msk (0x400UL)
2071 #define CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Pos (9UL)
2072 #define CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Msk (0x200UL)
2073 #define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (7UL)
2074 #define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x80UL)
2075 #define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos (6UL)
2076 #define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk (0x40UL)
2077 #define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL)
2078 #define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL)
2079 #define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL)
2080 #define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL)
2081 #define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos (3UL)
2082 #define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk (0x8UL)
2083 #define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos (2UL)
2084 #define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk (0x4UL)
2085 #define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL)
2086 #define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL)
2087 #define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL)
2088 #define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL)
2089 /* ===================================================== PMU_SLEEP_REG ===================================================== */
2090 #define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos (16UL)
2091 #define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk (0x10000UL)
2092 #define CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Pos (15UL)
2093 #define CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Msk (0x8000UL)
2094 #define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Pos (14UL)
2095 #define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Msk (0x4000UL)
2096 #define CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Pos (13UL)
2097 #define CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Msk (0x2000UL)
2098 #define CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Pos (12UL)
2099 #define CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Msk (0x1000UL)
2100 #define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos (0UL)
2101 #define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk (0xfffUL)
2102 /* ====================================================== POR_PIN_REG ====================================================== */
2103 #define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos (7UL)
2104 #define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk (0x80UL)
2105 #define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos (0UL)
2106 #define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk (0x3fUL)
2107 /* ===================================================== POR_TIMER_REG ===================================================== */
2108 #define CRG_TOP_POR_TIMER_REG_POR_TIME_Pos (0UL)
2109 #define CRG_TOP_POR_TIMER_REG_POR_TIME_Msk (0x7fUL)
2110 /* ==================================================== POWER_CTRL_REG ===================================================== */
2111 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Pos (14UL)
2112 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Msk (0x4000UL)
2113 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Pos (13UL)
2114 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Msk (0x2000UL)
2115 #define CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Pos (12UL)
2116 #define CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Msk (0x1000UL)
2117 #define CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Pos (11UL)
2118 #define CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Msk (0x800UL)
2119 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos (10UL)
2120 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk (0x400UL)
2121 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos (9UL)
2122 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk (0x200UL)
2123 #define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Pos (8UL)
2124 #define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Msk (0x100UL)
2125 #define CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Pos (7UL)
2126 #define CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Msk (0x80UL)
2127 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Pos (6UL)
2128 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Msk (0x40UL)
2129 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Pos (5UL)
2130 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Msk (0x20UL)
2131 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Pos (4UL)
2132 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Msk (0x10UL)
2133 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Pos (3UL)
2134 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Msk (0x8UL)
2135 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos (2UL)
2136 #define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk (0x4UL)
2137 #define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Pos (1UL)
2138 #define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Msk (0x2UL)
2139 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Pos (0UL)
2140 #define CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Msk (0x1UL)
2141 /* ==================================================== POWER_LEVEL_REG ==================================================== */
2142 #define CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Pos (11UL)
2143 #define CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Msk (0x3800UL)
2144 #define CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Pos (7UL)
2145 #define CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Msk (0x780UL)
2146 #define CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Pos (4UL)
2147 #define CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Msk (0x70UL)
2148 #define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Pos (3UL)
2149 #define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Msk (0x8UL)
2150 #define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Pos (0UL)
2151 #define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Msk (0x7UL)
2152 /* =================================================== RAM_PWR_CTRL_REG ==================================================== */
2153 #define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos (4UL)
2154 #define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk (0x30UL)
2155 #define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos (2UL)
2156 #define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk (0xcUL)
2157 #define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos (0UL)
2158 #define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk (0x3UL)
2159 /* ==================================================== RESET_STAT_REG ===================================================== */
2160 #define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos (5UL)
2161 #define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk (0x20UL)
2162 #define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL)
2163 #define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL)
2164 #define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL)
2165 #define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL)
2166 #define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL)
2167 #define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL)
2168 #define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL)
2169 #define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL)
2170 #define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL)
2171 #define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL)
2172 /* ===================================================== RST_CTRL_REG ====================================================== */
2173 #define CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Pos (2UL)
2174 #define CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Msk (0x4UL)
2175 #define CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Pos (1UL)
2176 #define CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Msk (0x2UL)
2177 #define CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Pos (0UL)
2178 #define CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Msk (0x1UL)
2179 /* ==================================================== SECURE_BOOT_REG ==================================================== */
2180 #define CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Pos (8UL)
2181 #define CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Msk (0x100UL)
2182 #define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (6UL)
2183 #define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x40UL)
2184 #define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos (5UL)
2185 #define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk (0x20UL)
2186 #define CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Pos (4UL)
2187 #define CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Msk (0x10UL)
2188 #define CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Pos (3UL)
2189 #define CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Msk (0x8UL)
2190 #define CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Pos (2UL)
2191 #define CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Msk (0x4UL)
2192 #define CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Pos (1UL)
2193 #define CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Msk (0x2UL)
2194 #define CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Pos (0UL)
2195 #define CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Msk (0x1UL)
2196 /* ================================================== STARTUP_STATUS_REG =================================================== */
2197 #define CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Pos (9UL)
2198 #define CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Msk (0x200UL)
2199 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Pos (8UL)
2200 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Msk (0x100UL)
2201 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Pos (7UL)
2202 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Msk (0x80UL)
2203 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Pos (6UL)
2204 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Msk (0x40UL)
2205 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Pos (5UL)
2206 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Msk (0x20UL)
2207 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Pos (3UL)
2208 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Msk (0x18UL)
2209 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Pos (2UL)
2210 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Msk (0x4UL)
2211 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Pos (1UL)
2212 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Msk (0x2UL)
2213 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Pos (0UL)
2214 #define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Msk (0x1UL)
2215 /* ===================================================== SYS_CTRL_REG ====================================================== */
2216 #define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL)
2217 #define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL)
2218 #define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL)
2219 #define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL)
2220 #define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL)
2221 #define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL)
2222 #define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL)
2223 #define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL)
2224 #define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL)
2225 #define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL)
2226 /* ===================================================== SYS_STAT_REG ====================================================== */
2227 #define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos (15UL)
2228 #define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk (0x8000UL)
2229 #define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (14UL)
2230 #define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x4000UL)
2231 #define CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Pos (13UL)
2232 #define CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Msk (0x2000UL)
2233 #define CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Pos (12UL)
2234 #define CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Msk (0x1000UL)
2235 #define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos (11UL)
2236 #define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk (0x800UL)
2237 #define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos (10UL)
2238 #define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk (0x400UL)
2239 #define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos (9UL)
2240 #define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk (0x200UL)
2241 #define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos (8UL)
2242 #define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk (0x100UL)
2243 #define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos (7UL)
2244 #define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk (0x80UL)
2245 #define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos (6UL)
2246 #define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk (0x40UL)
2247 #define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos (5UL)
2248 #define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk (0x20UL)
2249 #define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos (4UL)
2250 #define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk (0x10UL)
2251 #define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL)
2252 #define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL)
2253 #define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL)
2254 #define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL)
2255 #define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL)
2256 #define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL)
2257 #define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL)
2258 #define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL)
2261 /* =========================================================================================================================== */
2262 /* ================ CRG_XTAL ================ */
2263 /* =========================================================================================================================== */
2264 
2265 /* =================================================== CLKDBLR_CTRL1_REG =================================================== */
2266 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Pos (17UL)
2267 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Msk (0x7e0000UL)
2268 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Pos (12UL)
2269 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Msk (0x1f000UL)
2270 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Pos (8UL)
2271 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Msk (0xf00UL)
2272 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Pos (3UL)
2273 #define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Msk (0xf8UL)
2274 #define CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Pos (2UL)
2275 #define CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Msk (0x4UL)
2276 #define CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Pos (1UL)
2277 #define CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Msk (0x2UL)
2278 #define CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Pos (0UL)
2279 #define CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Msk (0x1UL)
2280 /* =================================================== CLKDBLR_CTRL2_REG =================================================== */
2281 #define CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Pos (14UL)
2282 #define CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Msk (0xc000UL)
2283 #define CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Pos (13UL)
2284 #define CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Msk (0x2000UL)
2285 #define CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Pos (12UL)
2286 #define CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Msk (0x1000UL)
2287 #define CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Pos (8UL)
2288 #define CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Msk (0xf00UL)
2289 #define CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Pos (7UL)
2290 #define CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Msk (0x80UL)
2291 #define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Pos (6UL)
2292 #define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Msk (0x40UL)
2293 #define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Pos (5UL)
2294 #define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Msk (0x20UL)
2295 #define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Pos (4UL)
2296 #define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Msk (0x10UL)
2297 #define CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Pos (3UL)
2298 #define CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Msk (0x8UL)
2299 #define CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Pos (2UL)
2300 #define CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Msk (0x4UL)
2301 #define CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Pos (1UL)
2302 #define CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Msk (0x2UL)
2303 #define CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Pos (0UL)
2304 #define CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Msk (0x1UL)
2305 /* ================================================== CLKDBLR_STATUS_REG =================================================== */
2306 #define CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Pos (31UL)
2307 #define CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Msk (0x80000000UL)
2308 #define CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Pos (26UL)
2309 #define CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Msk (0x7c000000UL)
2310 #define CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Pos (25UL)
2311 #define CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Msk (0x2000000UL)
2312 #define CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Pos (20UL)
2313 #define CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Msk (0x1f00000UL)
2314 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Pos (14UL)
2315 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Msk (0xfc000UL)
2316 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Pos (9UL)
2317 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Msk (0x3e00UL)
2318 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Pos (5UL)
2319 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Msk (0x1e0UL)
2320 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Pos (0UL)
2321 #define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Msk (0x1fUL)
2322 /* ================================================= XTAL32M_CAP_MEAS_REG ================================================== */
2323 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Pos (6UL)
2324 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Msk (0x1c0UL)
2325 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Pos (5UL)
2326 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Msk (0x20UL)
2327 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Pos (3UL)
2328 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Msk (0x18UL)
2329 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Pos (0UL)
2330 #define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Msk (0x7UL)
2331 /* =================================================== XTAL32M_CTRL_REG ==================================================== */
2332 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Pos (8UL)
2333 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Msk (0x100UL)
2334 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Pos (6UL)
2335 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Msk (0xc0UL)
2336 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Pos (4UL)
2337 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Msk (0x30UL)
2338 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Pos (2UL)
2339 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Msk (0xcUL)
2340 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Pos (0UL)
2341 #define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Msk (0x3UL)
2342 /* ==================================================== XTAL32M_FSM_REG ==================================================== */
2343 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Pos (4UL)
2344 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Msk (0x10UL)
2345 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Pos (3UL)
2346 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Msk (0x8UL)
2347 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Pos (2UL)
2348 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Msk (0x4UL)
2349 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Pos (1UL)
2350 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Msk (0x2UL)
2351 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Pos (0UL)
2352 #define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Msk (0x1UL)
2353 /* ================================================= XTAL32M_IRQ_CTRL_REG ================================================== */
2354 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Pos (10UL)
2355 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Msk (0xc00UL)
2356 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Pos (9UL)
2357 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Msk (0x200UL)
2358 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Pos (8UL)
2359 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Msk (0x100UL)
2360 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Pos (0UL)
2361 #define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Msk (0xffUL)
2362 /* ================================================= XTAL32M_IRQ_STAT_REG ================================================== */
2363 #define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Pos (8UL)
2364 #define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Msk (0xff00UL)
2365 #define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Pos (0UL)
2366 #define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Msk (0xffUL)
2367 /* ================================================== XTAL32M_SETTLE_REG =================================================== */
2368 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Pos (20UL)
2369 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Msk (0x7f00000UL)
2370 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Pos (17UL)
2371 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Msk (0xe0000UL)
2372 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Pos (15UL)
2373 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)
2374 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Pos (12UL)
2375 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)
2376 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Pos (8UL)
2377 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Msk (0xf00UL)
2378 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Pos (0UL)
2379 #define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Msk (0xffUL)
2380 /* =================================================== XTAL32M_START_REG =================================================== */
2381 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Pos (20UL)
2382 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Msk (0x7f00000UL)
2383 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Pos (17UL)
2384 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Msk (0xe0000UL)
2385 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Pos (15UL)
2386 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)
2387 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Pos (12UL)
2388 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)
2389 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Pos (8UL)
2390 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Msk (0xf00UL)
2391 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Pos (0UL)
2392 #define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Msk (0xffUL)
2393 /* =================================================== XTAL32M_STAT0_REG =================================================== */
2394 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Pos (11UL)
2395 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Msk (0x7f800UL)
2396 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Pos (7UL)
2397 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Msk (0x780UL)
2398 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Pos (6UL)
2399 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Msk (0x40UL)
2400 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Pos (5UL)
2401 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Msk (0x20UL)
2402 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Pos (1UL)
2403 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Msk (0x1eUL)
2404 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Pos (0UL)
2405 #define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Msk (0x1UL)
2406 /* =================================================== XTAL32M_TRIM_REG ==================================================== */
2407 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Pos (15UL)
2408 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)
2409 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Pos (12UL)
2410 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)
2411 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Pos (8UL)
2412 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Msk (0xf00UL)
2413 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Pos (0UL)
2414 #define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Msk (0xffUL)
2417 /* =========================================================================================================================== */
2418 /* ================ DCDC ================ */
2419 /* =========================================================================================================================== */
2420 
2421 /* ===================================================== DCDC_CTRL_REG ===================================================== */
2422 #define DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Pos (17UL)
2423 #define DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Msk (0x1e0000UL)
2424 #define DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Pos (16UL)
2425 #define DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Msk (0x10000UL)
2426 #define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Pos (12UL)
2427 #define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Msk (0xf000UL)
2428 #define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Pos (8UL)
2429 #define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Msk (0xf00UL)
2430 #define DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Pos (6UL)
2431 #define DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Msk (0xc0UL)
2432 #define DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Pos (3UL)
2433 #define DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Msk (0x38UL)
2434 #define DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Pos (1UL)
2435 #define DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Msk (0x6UL)
2436 #define DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Pos (0UL)
2437 #define DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Msk (0x1UL)
2440 /* =========================================================================================================================== */
2441 /* ================ DMA ================ */
2442 /* =========================================================================================================================== */
2443 
2444 /* =================================================== DMA0_A_START_REG ==================================================== */
2445 #define DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL)
2446 #define DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL)
2447 /* =================================================== DMA0_B_START_REG ==================================================== */
2448 #define DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL)
2449 #define DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL)
2450 /* ===================================================== DMA0_CTRL_REG ===================================================== */
2451 #define DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)
2452 #define DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)
2453 #define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)
2454 #define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)
2455 #define DMA_DMA0_CTRL_REG_BURST_MODE_Pos (13UL)
2456 #define DMA_DMA0_CTRL_REG_BURST_MODE_Msk (0x6000UL)
2457 #define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (12UL)
2458 #define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x1000UL)
2459 #define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (11UL)
2460 #define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x800UL)
2461 #define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (10UL)
2462 #define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x400UL)
2463 #define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (7UL)
2464 #define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x380UL)
2465 #define DMA_DMA0_CTRL_REG_CIRCULAR_Pos (6UL)
2466 #define DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x40UL)
2467 #define DMA_DMA0_CTRL_REG_AINC_Pos (5UL)
2468 #define DMA_DMA0_CTRL_REG_AINC_Msk (0x20UL)
2469 #define DMA_DMA0_CTRL_REG_BINC_Pos (4UL)
2470 #define DMA_DMA0_CTRL_REG_BINC_Msk (0x10UL)
2471 #define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (3UL)
2472 #define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x8UL)
2473 #define DMA_DMA0_CTRL_REG_BW_Pos (1UL)
2474 #define DMA_DMA0_CTRL_REG_BW_Msk (0x6UL)
2475 #define DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL)
2476 #define DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL)
2477 /* ===================================================== DMA0_IDX_REG ====================================================== */
2478 #define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL)
2479 #define DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL)
2480 /* ===================================================== DMA0_INT_REG ====================================================== */
2481 #define DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL)
2482 #define DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL)
2483 /* ===================================================== DMA0_LEN_REG ====================================================== */
2484 #define DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL)
2485 #define DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL)
2486 /* =================================================== DMA1_A_START_REG ==================================================== */
2487 #define DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL)
2488 #define DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL)
2489 /* =================================================== DMA1_B_START_REG ==================================================== */
2490 #define DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL)
2491 #define DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL)
2492 /* ===================================================== DMA1_CTRL_REG ===================================================== */
2493 #define DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)
2494 #define DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)
2495 #define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)
2496 #define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)
2497 #define DMA_DMA1_CTRL_REG_BURST_MODE_Pos (13UL)
2498 #define DMA_DMA1_CTRL_REG_BURST_MODE_Msk (0x6000UL)
2499 #define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (12UL)
2500 #define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x1000UL)
2501 #define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (11UL)
2502 #define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x800UL)
2503 #define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (10UL)
2504 #define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x400UL)
2505 #define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (7UL)
2506 #define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x380UL)
2507 #define DMA_DMA1_CTRL_REG_CIRCULAR_Pos (6UL)
2508 #define DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x40UL)
2509 #define DMA_DMA1_CTRL_REG_AINC_Pos (5UL)
2510 #define DMA_DMA1_CTRL_REG_AINC_Msk (0x20UL)
2511 #define DMA_DMA1_CTRL_REG_BINC_Pos (4UL)
2512 #define DMA_DMA1_CTRL_REG_BINC_Msk (0x10UL)
2513 #define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (3UL)
2514 #define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x8UL)
2515 #define DMA_DMA1_CTRL_REG_BW_Pos (1UL)
2516 #define DMA_DMA1_CTRL_REG_BW_Msk (0x6UL)
2517 #define DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL)
2518 #define DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL)
2519 /* ===================================================== DMA1_IDX_REG ====================================================== */
2520 #define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL)
2521 #define DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL)
2522 /* ===================================================== DMA1_INT_REG ====================================================== */
2523 #define DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL)
2524 #define DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL)
2525 /* ===================================================== DMA1_LEN_REG ====================================================== */
2526 #define DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL)
2527 #define DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL)
2528 /* =================================================== DMA2_A_START_REG ==================================================== */
2529 #define DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL)
2530 #define DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL)
2531 /* =================================================== DMA2_B_START_REG ==================================================== */
2532 #define DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL)
2533 #define DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL)
2534 /* ===================================================== DMA2_CTRL_REG ===================================================== */
2535 #define DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)
2536 #define DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)
2537 #define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)
2538 #define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)
2539 #define DMA_DMA2_CTRL_REG_BURST_MODE_Pos (13UL)
2540 #define DMA_DMA2_CTRL_REG_BURST_MODE_Msk (0x6000UL)
2541 #define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (12UL)
2542 #define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x1000UL)
2543 #define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (11UL)
2544 #define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x800UL)
2545 #define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (10UL)
2546 #define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x400UL)
2547 #define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (7UL)
2548 #define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x380UL)
2549 #define DMA_DMA2_CTRL_REG_CIRCULAR_Pos (6UL)
2550 #define DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x40UL)
2551 #define DMA_DMA2_CTRL_REG_AINC_Pos (5UL)
2552 #define DMA_DMA2_CTRL_REG_AINC_Msk (0x20UL)
2553 #define DMA_DMA2_CTRL_REG_BINC_Pos (4UL)
2554 #define DMA_DMA2_CTRL_REG_BINC_Msk (0x10UL)
2555 #define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (3UL)
2556 #define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x8UL)
2557 #define DMA_DMA2_CTRL_REG_BW_Pos (1UL)
2558 #define DMA_DMA2_CTRL_REG_BW_Msk (0x6UL)
2559 #define DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL)
2560 #define DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL)
2561 /* ===================================================== DMA2_IDX_REG ====================================================== */
2562 #define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL)
2563 #define DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL)
2564 /* ===================================================== DMA2_INT_REG ====================================================== */
2565 #define DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL)
2566 #define DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL)
2567 /* ===================================================== DMA2_LEN_REG ====================================================== */
2568 #define DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL)
2569 #define DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL)
2570 /* =================================================== DMA3_A_START_REG ==================================================== */
2571 #define DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL)
2572 #define DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL)
2573 /* =================================================== DMA3_B_START_REG ==================================================== */
2574 #define DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL)
2575 #define DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL)
2576 /* ===================================================== DMA3_CTRL_REG ===================================================== */
2577 #define DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)
2578 #define DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)
2579 #define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)
2580 #define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)
2581 #define DMA_DMA3_CTRL_REG_BURST_MODE_Pos (13UL)
2582 #define DMA_DMA3_CTRL_REG_BURST_MODE_Msk (0x6000UL)
2583 #define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (12UL)
2584 #define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x1000UL)
2585 #define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (11UL)
2586 #define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x800UL)
2587 #define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (10UL)
2588 #define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x400UL)
2589 #define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (7UL)
2590 #define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x380UL)
2591 #define DMA_DMA3_CTRL_REG_CIRCULAR_Pos (6UL)
2592 #define DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x40UL)
2593 #define DMA_DMA3_CTRL_REG_AINC_Pos (5UL)
2594 #define DMA_DMA3_CTRL_REG_AINC_Msk (0x20UL)
2595 #define DMA_DMA3_CTRL_REG_BINC_Pos (4UL)
2596 #define DMA_DMA3_CTRL_REG_BINC_Msk (0x10UL)
2597 #define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (3UL)
2598 #define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x8UL)
2599 #define DMA_DMA3_CTRL_REG_BW_Pos (1UL)
2600 #define DMA_DMA3_CTRL_REG_BW_Msk (0x6UL)
2601 #define DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL)
2602 #define DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL)
2603 /* ===================================================== DMA3_IDX_REG ====================================================== */
2604 #define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL)
2605 #define DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL)
2606 /* ===================================================== DMA3_INT_REG ====================================================== */
2607 #define DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL)
2608 #define DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL)
2609 /* ===================================================== DMA3_LEN_REG ====================================================== */
2610 #define DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL)
2611 #define DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL)
2612 /* =================================================== DMA4_A_START_REG ==================================================== */
2613 #define DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL)
2614 #define DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL)
2615 /* =================================================== DMA4_B_START_REG ==================================================== */
2616 #define DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL)
2617 #define DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL)
2618 /* ===================================================== DMA4_CTRL_REG ===================================================== */
2619 #define DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)
2620 #define DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)
2621 #define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)
2622 #define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)
2623 #define DMA_DMA4_CTRL_REG_BURST_MODE_Pos (13UL)
2624 #define DMA_DMA4_CTRL_REG_BURST_MODE_Msk (0x6000UL)
2625 #define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (12UL)
2626 #define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x1000UL)
2627 #define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (11UL)
2628 #define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x800UL)
2629 #define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (10UL)
2630 #define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x400UL)
2631 #define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (7UL)
2632 #define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x380UL)
2633 #define DMA_DMA4_CTRL_REG_CIRCULAR_Pos (6UL)
2634 #define DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x40UL)
2635 #define DMA_DMA4_CTRL_REG_AINC_Pos (5UL)
2636 #define DMA_DMA4_CTRL_REG_AINC_Msk (0x20UL)
2637 #define DMA_DMA4_CTRL_REG_BINC_Pos (4UL)
2638 #define DMA_DMA4_CTRL_REG_BINC_Msk (0x10UL)
2639 #define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (3UL)
2640 #define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x8UL)
2641 #define DMA_DMA4_CTRL_REG_BW_Pos (1UL)
2642 #define DMA_DMA4_CTRL_REG_BW_Msk (0x6UL)
2643 #define DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL)
2644 #define DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL)
2645 /* ===================================================== DMA4_IDX_REG ====================================================== */
2646 #define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL)
2647 #define DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL)
2648 /* ===================================================== DMA4_INT_REG ====================================================== */
2649 #define DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL)
2650 #define DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL)
2651 /* ===================================================== DMA4_LEN_REG ====================================================== */
2652 #define DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL)
2653 #define DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL)
2654 /* =================================================== DMA5_A_START_REG ==================================================== */
2655 #define DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL)
2656 #define DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL)
2657 /* =================================================== DMA5_B_START_REG ==================================================== */
2658 #define DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL)
2659 #define DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL)
2660 /* ===================================================== DMA5_CTRL_REG ===================================================== */
2661 #define DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)
2662 #define DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)
2663 #define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)
2664 #define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)
2665 #define DMA_DMA5_CTRL_REG_BURST_MODE_Pos (13UL)
2666 #define DMA_DMA5_CTRL_REG_BURST_MODE_Msk (0x6000UL)
2667 #define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (12UL)
2668 #define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x1000UL)
2669 #define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (11UL)
2670 #define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x800UL)
2671 #define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (10UL)
2672 #define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x400UL)
2673 #define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (7UL)
2674 #define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x380UL)
2675 #define DMA_DMA5_CTRL_REG_CIRCULAR_Pos (6UL)
2676 #define DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x40UL)
2677 #define DMA_DMA5_CTRL_REG_AINC_Pos (5UL)
2678 #define DMA_DMA5_CTRL_REG_AINC_Msk (0x20UL)
2679 #define DMA_DMA5_CTRL_REG_BINC_Pos (4UL)
2680 #define DMA_DMA5_CTRL_REG_BINC_Msk (0x10UL)
2681 #define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (3UL)
2682 #define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x8UL)
2683 #define DMA_DMA5_CTRL_REG_BW_Pos (1UL)
2684 #define DMA_DMA5_CTRL_REG_BW_Msk (0x6UL)
2685 #define DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL)
2686 #define DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL)
2687 /* ===================================================== DMA5_IDX_REG ====================================================== */
2688 #define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL)
2689 #define DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL)
2690 /* ===================================================== DMA5_INT_REG ====================================================== */
2691 #define DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL)
2692 #define DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL)
2693 /* ===================================================== DMA5_LEN_REG ====================================================== */
2694 #define DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL)
2695 #define DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL)
2696 /* =================================================== DMA_CLEAR_INT_REG =================================================== */
2697 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL)
2698 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL)
2699 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL)
2700 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL)
2701 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL)
2702 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL)
2703 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL)
2704 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL)
2705 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL)
2706 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL)
2707 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL)
2708 #define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL)
2709 /* =================================================== DMA_INT_MASK_REG ==================================================== */
2710 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL)
2711 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL)
2712 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL)
2713 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL)
2714 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL)
2715 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL)
2716 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL)
2717 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL)
2718 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL)
2719 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL)
2720 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL)
2721 #define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL)
2722 /* ================================================== DMA_INT_STATUS_REG =================================================== */
2723 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (13UL)
2724 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x2000UL)
2725 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (12UL)
2726 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x1000UL)
2727 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (11UL)
2728 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x800UL)
2729 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (10UL)
2730 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x400UL)
2731 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (9UL)
2732 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x200UL)
2733 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (8UL)
2734 #define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x100UL)
2735 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL)
2736 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL)
2737 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL)
2738 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL)
2739 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL)
2740 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL)
2741 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL)
2742 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL)
2743 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL)
2744 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL)
2745 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL)
2746 #define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL)
2747 /* ==================================================== DMA_REQ_MUX_REG ==================================================== */
2748 #define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL)
2749 #define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL)
2750 #define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL)
2751 #define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL)
2752 #define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL)
2753 #define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL)
2754 /* ================================================ DMA_RESET_INT_MASK_REG ================================================= */
2755 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Pos (5UL)
2756 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Msk (0x20UL)
2757 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Pos (4UL)
2758 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Msk (0x10UL)
2759 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Pos (3UL)
2760 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Msk (0x8UL)
2761 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Pos (2UL)
2762 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Msk (0x4UL)
2763 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Pos (1UL)
2764 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Msk (0x2UL)
2765 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Pos (0UL)
2766 #define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Msk (0x1UL)
2767 /* ================================================= DMA_SET_INT_MASK_REG ================================================== */
2768 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Pos (5UL)
2769 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Msk (0x20UL)
2770 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Pos (4UL)
2771 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Msk (0x10UL)
2772 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Pos (3UL)
2773 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Msk (0x8UL)
2774 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Pos (2UL)
2775 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Msk (0x4UL)
2776 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Pos (1UL)
2777 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Msk (0x2UL)
2778 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Pos (0UL)
2779 #define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Msk (0x1UL)
2782 /* =========================================================================================================================== */
2783 /* ================ DW ================ */
2784 /* =========================================================================================================================== */
2785 
2786 /* =================================================== AHB_DMA_CCLM1_REG =================================================== */
2787 #define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL)
2788 #define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL)
2789 /* =================================================== AHB_DMA_CCLM2_REG =================================================== */
2790 #define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL)
2791 #define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL)
2792 /* =================================================== AHB_DMA_CCLM3_REG =================================================== */
2793 #define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL)
2794 #define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL)
2795 /* =================================================== AHB_DMA_CCLM4_REG =================================================== */
2796 #define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL)
2797 #define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL)
2798 /* ================================================ AHB_DMA_DFLT_MASTER_REG ================================================ */
2799 #define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL)
2800 #define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL)
2801 /* ==================================================== AHB_DMA_PL1_REG ==================================================== */
2802 #define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL)
2803 #define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL)
2804 /* ==================================================== AHB_DMA_PL2_REG ==================================================== */
2805 #define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL)
2806 #define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL)
2807 /* ==================================================== AHB_DMA_PL3_REG ==================================================== */
2808 #define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL)
2809 #define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL)
2810 /* ==================================================== AHB_DMA_PL4_REG ==================================================== */
2811 #define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL)
2812 #define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL)
2813 /* ==================================================== AHB_DMA_TCL_REG ==================================================== */
2814 #define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL)
2815 #define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL)
2816 /* ================================================== AHB_DMA_VERSION_REG ================================================== */
2817 #define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL)
2818 #define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL)
2819 /* =================================================== AHB_DMA_WTEN_REG ==================================================== */
2820 #define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL)
2821 #define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL)
2824 /* =========================================================================================================================== */
2825 /* ================ FCU ================ */
2826 /* =========================================================================================================================== */
2827 
2828 /* ==================================================== FLASH_CTRL_REG ===================================================== */
2829 #define FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Pos (25UL)
2830 #define FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Msk (0x2000000UL)
2831 #define FCU_FLASH_CTRL_REG_DFT_EN_Pos (24UL)
2832 #define FCU_FLASH_CTRL_REG_DFT_EN_Msk (0x1000000UL)
2833 #define FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Pos (23UL)
2834 #define FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Msk (0x800000UL)
2835 #define FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Pos (22UL)
2836 #define FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Msk (0x400000UL)
2837 #define FCU_FLASH_CTRL_REG_ERASE_RESUME_Pos (21UL)
2838 #define FCU_FLASH_CTRL_REG_ERASE_RESUME_Msk (0x200000UL)
2839 #define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Pos (20UL)
2840 #define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Msk (0x100000UL)
2841 #define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Pos (19UL)
2842 #define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Msk (0x80000UL)
2843 #define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Pos (18UL)
2844 #define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Msk (0x40000UL)
2845 #define FCU_FLASH_CTRL_REG_SLEEP_Pos (17UL)
2846 #define FCU_FLASH_CTRL_REG_SLEEP_Msk (0x20000UL)
2847 #define FCU_FLASH_CTRL_REG_DMA_EN_Pos (16UL)
2848 #define FCU_FLASH_CTRL_REG_DMA_EN_Msk (0x10000UL)
2849 #define FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Pos (15UL)
2850 #define FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Msk (0x8000UL)
2851 #define FCU_FLASH_CTRL_REG_BUS_ERROR_Pos (14UL)
2852 #define FCU_FLASH_CTRL_REG_BUS_ERROR_Msk (0x4000UL)
2853 #define FCU_FLASH_CTRL_REG_IRQ_CLEAR_Pos (13UL)
2854 #define FCU_FLASH_CTRL_REG_IRQ_CLEAR_Msk (0x2000UL)
2855 #define FCU_FLASH_CTRL_REG_WAIT_CYCLES_Pos (10UL)
2856 #define FCU_FLASH_CTRL_REG_WAIT_CYCLES_Msk (0x1c00UL)
2857 #define FCU_FLASH_CTRL_REG_FLASH_RPROT_Pos (9UL)
2858 #define FCU_FLASH_CTRL_REG_FLASH_RPROT_Msk (0x200UL)
2859 #define FCU_FLASH_CTRL_REG_FLASH_WPROT_Pos (8UL)
2860 #define FCU_FLASH_CTRL_REG_FLASH_WPROT_Msk (0x100UL)
2861 #define FCU_FLASH_CTRL_REG_FLASH_PROT_Pos (7UL)
2862 #define FCU_FLASH_CTRL_REG_FLASH_PROT_Msk (0x80UL)
2863 #define FCU_FLASH_CTRL_REG_PROG_RMIN_Pos (6UL)
2864 #define FCU_FLASH_CTRL_REG_PROG_RMIN_Msk (0x40UL)
2865 #define FCU_FLASH_CTRL_REG_PROG_ERS_Pos (5UL)
2866 #define FCU_FLASH_CTRL_REG_PROG_ERS_Msk (0x20UL)
2867 #define FCU_FLASH_CTRL_REG_PROG_WRS_Pos (4UL)
2868 #define FCU_FLASH_CTRL_REG_PROG_WRS_Msk (0x10UL)
2869 #define FCU_FLASH_CTRL_REG_PROG_SEL_Pos (3UL)
2870 #define FCU_FLASH_CTRL_REG_PROG_SEL_Msk (0x8UL)
2871 #define FCU_FLASH_CTRL_REG_SLEEP_MODE_Pos (2UL)
2872 #define FCU_FLASH_CTRL_REG_SLEEP_MODE_Msk (0x4UL)
2873 #define FCU_FLASH_CTRL_REG_PROG_MODE_Pos (0UL)
2874 #define FCU_FLASH_CTRL_REG_PROG_MODE_Msk (0x3UL)
2875 /* =================================================== FLASH_PTERASE_REG =================================================== */
2876 #define FCU_FLASH_PTERASE_REG_PTERASE_Pos (0UL)
2877 #define FCU_FLASH_PTERASE_REG_PTERASE_Msk (0xffffffUL)
2878 /* ================================================= FLASH_PTERASE_SEG_REG ================================================= */
2879 #define FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Pos (0UL)
2880 #define FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Msk (0xffffffUL)
2881 /* ==================================================== FLASH_PTME_REG ===================================================== */
2882 #define FCU_FLASH_PTME_REG_PTME_Pos (0UL)
2883 #define FCU_FLASH_PTME_REG_PTME_Msk (0xffffffUL)
2884 /* =================================================== FLASH_PTNVH1_REG ==================================================== */
2885 #define FCU_FLASH_PTNVH1_REG_PTNVH1_Pos (0UL)
2886 #define FCU_FLASH_PTNVH1_REG_PTNVH1_Msk (0xffffUL)
2887 /* =================================================== FLASH_PTPROG_REG ==================================================== */
2888 #define FCU_FLASH_PTPROG_REG_PTPROG_Pos (0UL)
2889 #define FCU_FLASH_PTPROG_REG_PTPROG_Msk (0xffffUL)
2890 /* =================================================== FLASH_PTWK_SP_REG =================================================== */
2891 #define FCU_FLASH_PTWK_SP_REG_PTWK_SP_Pos (0UL)
2892 #define FCU_FLASH_PTWK_SP_REG_PTWK_SP_Msk (0xffUL)
2893 /* =============================================== FLASH_RTERASE_SEG_CNT_REG =============================================== */
2894 #define FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Pos (0UL)
2895 #define FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Msk (0xffffffUL)
2896 /* =============================================== FLASH_RTERASE_TOT_CNT_REG =============================================== */
2897 #define FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Pos (0UL)
2898 #define FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Msk (0xffffffUL)
2901 /* =========================================================================================================================== */
2902 /* ================ GPADC ================ */
2903 /* =========================================================================================================================== */
2904 
2905 /* ================================================= GP_ADC_CLEAR_INT_REG ================================================== */
2906 #define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL)
2907 #define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL)
2908 /* =================================================== GP_ADC_CTRL2_REG ==================================================== */
2909 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (13UL)
2910 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xe000UL)
2911 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (9UL)
2912 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0x1e00UL)
2913 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (6UL)
2914 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0x1c0UL)
2915 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL)
2916 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL)
2917 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Pos (0UL)
2918 #define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Msk (0x3UL)
2919 /* =================================================== GP_ADC_CTRL3_REG ==================================================== */
2920 #define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL)
2921 #define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL)
2922 #define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL)
2923 #define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL)
2924 /* ==================================================== GP_ADC_CTRL_REG ==================================================== */
2925 #define GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Pos (12UL)
2926 #define GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Msk (0x1000UL)
2927 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Pos (10UL)
2928 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Msk (0x400UL)
2929 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (9UL)
2930 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x200UL)
2931 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (8UL)
2932 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x100UL)
2933 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL)
2934 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL)
2935 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL)
2936 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL)
2937 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL)
2938 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL)
2939 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL)
2940 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL)
2941 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Pos (3UL)
2942 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Msk (0x8UL)
2943 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL)
2944 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL)
2945 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL)
2946 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL)
2947 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL)
2948 #define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL)
2949 /* ==================================================== GP_ADC_OFFN_REG ==================================================== */
2950 #define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL)
2951 #define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL)
2952 /* ==================================================== GP_ADC_OFFP_REG ==================================================== */
2953 #define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL)
2954 #define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL)
2955 /* =================================================== GP_ADC_RESULT_REG =================================================== */
2956 #define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL)
2957 #define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL)
2958 /* ==================================================== GP_ADC_SEL_REG ===================================================== */
2959 #define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Pos (4UL)
2960 #define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Msk (0xf0UL)
2961 #define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Pos (0UL)
2962 #define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Msk (0xfUL)
2965 /* =========================================================================================================================== */
2966 /* ================ GPIO ================ */
2967 /* =========================================================================================================================== */
2968 
2969 /* =================================================== GPIO_CLK_SEL_REG ==================================================== */
2970 #define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos (9UL)
2971 #define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk (0x200UL)
2972 #define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos (8UL)
2973 #define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk (0x100UL)
2974 #define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos (7UL)
2975 #define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk (0x80UL)
2976 #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL)
2977 #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL)
2978 #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL)
2979 #define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL)
2980 /* ==================================================== P0_00_MODE_REG ===================================================== */
2981 #define GPIO_P0_00_MODE_REG_PPOD_Pos (10UL)
2982 #define GPIO_P0_00_MODE_REG_PPOD_Msk (0x400UL)
2983 #define GPIO_P0_00_MODE_REG_PUPD_Pos (8UL)
2984 #define GPIO_P0_00_MODE_REG_PUPD_Msk (0x300UL)
2985 #define GPIO_P0_00_MODE_REG_PID_Pos (0UL)
2986 #define GPIO_P0_00_MODE_REG_PID_Msk (0x3fUL)
2987 /* ==================================================== P0_01_MODE_REG ===================================================== */
2988 #define GPIO_P0_01_MODE_REG_PPOD_Pos (10UL)
2989 #define GPIO_P0_01_MODE_REG_PPOD_Msk (0x400UL)
2990 #define GPIO_P0_01_MODE_REG_PUPD_Pos (8UL)
2991 #define GPIO_P0_01_MODE_REG_PUPD_Msk (0x300UL)
2992 #define GPIO_P0_01_MODE_REG_PID_Pos (0UL)
2993 #define GPIO_P0_01_MODE_REG_PID_Msk (0x3fUL)
2994 /* ==================================================== P0_02_MODE_REG ===================================================== */
2995 #define GPIO_P0_02_MODE_REG_PPOD_Pos (10UL)
2996 #define GPIO_P0_02_MODE_REG_PPOD_Msk (0x400UL)
2997 #define GPIO_P0_02_MODE_REG_PUPD_Pos (8UL)
2998 #define GPIO_P0_02_MODE_REG_PUPD_Msk (0x300UL)
2999 #define GPIO_P0_02_MODE_REG_PID_Pos (0UL)
3000 #define GPIO_P0_02_MODE_REG_PID_Msk (0x3fUL)
3001 /* ==================================================== P0_03_MODE_REG ===================================================== */
3002 #define GPIO_P0_03_MODE_REG_PPOD_Pos (10UL)
3003 #define GPIO_P0_03_MODE_REG_PPOD_Msk (0x400UL)
3004 #define GPIO_P0_03_MODE_REG_PUPD_Pos (8UL)
3005 #define GPIO_P0_03_MODE_REG_PUPD_Msk (0x300UL)
3006 #define GPIO_P0_03_MODE_REG_PID_Pos (0UL)
3007 #define GPIO_P0_03_MODE_REG_PID_Msk (0x3fUL)
3008 /* ==================================================== P0_04_MODE_REG ===================================================== */
3009 #define GPIO_P0_04_MODE_REG_PPOD_Pos (10UL)
3010 #define GPIO_P0_04_MODE_REG_PPOD_Msk (0x400UL)
3011 #define GPIO_P0_04_MODE_REG_PUPD_Pos (8UL)
3012 #define GPIO_P0_04_MODE_REG_PUPD_Msk (0x300UL)
3013 #define GPIO_P0_04_MODE_REG_PID_Pos (0UL)
3014 #define GPIO_P0_04_MODE_REG_PID_Msk (0x3fUL)
3015 /* ==================================================== P0_05_MODE_REG ===================================================== */
3016 #define GPIO_P0_05_MODE_REG_PPOD_Pos (10UL)
3017 #define GPIO_P0_05_MODE_REG_PPOD_Msk (0x400UL)
3018 #define GPIO_P0_05_MODE_REG_PUPD_Pos (8UL)
3019 #define GPIO_P0_05_MODE_REG_PUPD_Msk (0x300UL)
3020 #define GPIO_P0_05_MODE_REG_PID_Pos (0UL)
3021 #define GPIO_P0_05_MODE_REG_PID_Msk (0x3fUL)
3022 /* ==================================================== P0_06_MODE_REG ===================================================== */
3023 #define GPIO_P0_06_MODE_REG_PPOD_Pos (10UL)
3024 #define GPIO_P0_06_MODE_REG_PPOD_Msk (0x400UL)
3025 #define GPIO_P0_06_MODE_REG_PUPD_Pos (8UL)
3026 #define GPIO_P0_06_MODE_REG_PUPD_Msk (0x300UL)
3027 #define GPIO_P0_06_MODE_REG_PID_Pos (0UL)
3028 #define GPIO_P0_06_MODE_REG_PID_Msk (0x3fUL)
3029 /* ==================================================== P0_07_MODE_REG ===================================================== */
3030 #define GPIO_P0_07_MODE_REG_PPOD_Pos (10UL)
3031 #define GPIO_P0_07_MODE_REG_PPOD_Msk (0x400UL)
3032 #define GPIO_P0_07_MODE_REG_PUPD_Pos (8UL)
3033 #define GPIO_P0_07_MODE_REG_PUPD_Msk (0x300UL)
3034 #define GPIO_P0_07_MODE_REG_PID_Pos (0UL)
3035 #define GPIO_P0_07_MODE_REG_PID_Msk (0x3fUL)
3036 /* ==================================================== P0_08_MODE_REG ===================================================== */
3037 #define GPIO_P0_08_MODE_REG_PPOD_Pos (10UL)
3038 #define GPIO_P0_08_MODE_REG_PPOD_Msk (0x400UL)
3039 #define GPIO_P0_08_MODE_REG_PUPD_Pos (8UL)
3040 #define GPIO_P0_08_MODE_REG_PUPD_Msk (0x300UL)
3041 #define GPIO_P0_08_MODE_REG_PID_Pos (0UL)
3042 #define GPIO_P0_08_MODE_REG_PID_Msk (0x3fUL)
3043 /* ==================================================== P0_09_MODE_REG ===================================================== */
3044 #define GPIO_P0_09_MODE_REG_PPOD_Pos (10UL)
3045 #define GPIO_P0_09_MODE_REG_PPOD_Msk (0x400UL)
3046 #define GPIO_P0_09_MODE_REG_PUPD_Pos (8UL)
3047 #define GPIO_P0_09_MODE_REG_PUPD_Msk (0x300UL)
3048 #define GPIO_P0_09_MODE_REG_PID_Pos (0UL)
3049 #define GPIO_P0_09_MODE_REG_PID_Msk (0x3fUL)
3050 /* ==================================================== P0_10_MODE_REG ===================================================== */
3051 #define GPIO_P0_10_MODE_REG_PPOD_Pos (10UL)
3052 #define GPIO_P0_10_MODE_REG_PPOD_Msk (0x400UL)
3053 #define GPIO_P0_10_MODE_REG_PUPD_Pos (8UL)
3054 #define GPIO_P0_10_MODE_REG_PUPD_Msk (0x300UL)
3055 #define GPIO_P0_10_MODE_REG_PID_Pos (0UL)
3056 #define GPIO_P0_10_MODE_REG_PID_Msk (0x3fUL)
3057 /* ==================================================== P0_11_MODE_REG ===================================================== */
3058 #define GPIO_P0_11_MODE_REG_PPOD_Pos (10UL)
3059 #define GPIO_P0_11_MODE_REG_PPOD_Msk (0x400UL)
3060 #define GPIO_P0_11_MODE_REG_PUPD_Pos (8UL)
3061 #define GPIO_P0_11_MODE_REG_PUPD_Msk (0x300UL)
3062 #define GPIO_P0_11_MODE_REG_PID_Pos (0UL)
3063 #define GPIO_P0_11_MODE_REG_PID_Msk (0x3fUL)
3064 /* ==================================================== P0_12_MODE_REG ===================================================== */
3065 #define GPIO_P0_12_MODE_REG_PPOD_Pos (10UL)
3066 #define GPIO_P0_12_MODE_REG_PPOD_Msk (0x400UL)
3067 #define GPIO_P0_12_MODE_REG_PUPD_Pos (8UL)
3068 #define GPIO_P0_12_MODE_REG_PUPD_Msk (0x300UL)
3069 #define GPIO_P0_12_MODE_REG_PID_Pos (0UL)
3070 #define GPIO_P0_12_MODE_REG_PID_Msk (0x3fUL)
3071 /* ==================================================== P0_13_MODE_REG ===================================================== */
3072 #define GPIO_P0_13_MODE_REG_PPOD_Pos (10UL)
3073 #define GPIO_P0_13_MODE_REG_PPOD_Msk (0x400UL)
3074 #define GPIO_P0_13_MODE_REG_PUPD_Pos (8UL)
3075 #define GPIO_P0_13_MODE_REG_PUPD_Msk (0x300UL)
3076 #define GPIO_P0_13_MODE_REG_PID_Pos (0UL)
3077 #define GPIO_P0_13_MODE_REG_PID_Msk (0x3fUL)
3078 /* ==================================================== P0_14_MODE_REG ===================================================== */
3079 #define GPIO_P0_14_MODE_REG_PPOD_Pos (10UL)
3080 #define GPIO_P0_14_MODE_REG_PPOD_Msk (0x400UL)
3081 #define GPIO_P0_14_MODE_REG_PUPD_Pos (8UL)
3082 #define GPIO_P0_14_MODE_REG_PUPD_Msk (0x300UL)
3083 #define GPIO_P0_14_MODE_REG_PID_Pos (0UL)
3084 #define GPIO_P0_14_MODE_REG_PID_Msk (0x3fUL)
3085 /* ==================================================== P0_15_MODE_REG ===================================================== */
3086 #define GPIO_P0_15_MODE_REG_PPOD_Pos (10UL)
3087 #define GPIO_P0_15_MODE_REG_PPOD_Msk (0x400UL)
3088 #define GPIO_P0_15_MODE_REG_PUPD_Pos (8UL)
3089 #define GPIO_P0_15_MODE_REG_PUPD_Msk (0x300UL)
3090 #define GPIO_P0_15_MODE_REG_PID_Pos (0UL)
3091 #define GPIO_P0_15_MODE_REG_PID_Msk (0x3fUL)
3092 /* ====================================================== P0_DATA_REG ====================================================== */
3093 #define GPIO_P0_DATA_REG_P0_DATA_Pos (0UL)
3094 #define GPIO_P0_DATA_REG_P0_DATA_Msk (0xffffUL)
3095 /* =================================================== P0_RESET_DATA_REG =================================================== */
3096 #define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL)
3097 #define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffffUL)
3098 /* ==================================================== P0_SET_DATA_REG ==================================================== */
3099 #define GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL)
3100 #define GPIO_P0_SET_DATA_REG_P0_SET_Msk (0xffffUL)
3101 /* =================================================== P0_WEAK_CTRL_REG ==================================================== */
3102 #define GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Pos (6UL)
3103 #define GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Msk (0xffc0UL)
3104 /* ==================================================== P1_00_MODE_REG ===================================================== */
3105 #define GPIO_P1_00_MODE_REG_PPOD_Pos (10UL)
3106 #define GPIO_P1_00_MODE_REG_PPOD_Msk (0x400UL)
3107 #define GPIO_P1_00_MODE_REG_PUPD_Pos (8UL)
3108 #define GPIO_P1_00_MODE_REG_PUPD_Msk (0x300UL)
3109 #define GPIO_P1_00_MODE_REG_PID_Pos (0UL)
3110 #define GPIO_P1_00_MODE_REG_PID_Msk (0x3fUL)
3111 /* ==================================================== P1_01_MODE_REG ===================================================== */
3112 #define GPIO_P1_01_MODE_REG_PPOD_Pos (10UL)
3113 #define GPIO_P1_01_MODE_REG_PPOD_Msk (0x400UL)
3114 #define GPIO_P1_01_MODE_REG_PUPD_Pos (8UL)
3115 #define GPIO_P1_01_MODE_REG_PUPD_Msk (0x300UL)
3116 #define GPIO_P1_01_MODE_REG_PID_Pos (0UL)
3117 #define GPIO_P1_01_MODE_REG_PID_Msk (0x3fUL)
3118 /* ==================================================== P1_02_MODE_REG ===================================================== */
3119 #define GPIO_P1_02_MODE_REG_PPOD_Pos (10UL)
3120 #define GPIO_P1_02_MODE_REG_PPOD_Msk (0x400UL)
3121 #define GPIO_P1_02_MODE_REG_PUPD_Pos (8UL)
3122 #define GPIO_P1_02_MODE_REG_PUPD_Msk (0x300UL)
3123 #define GPIO_P1_02_MODE_REG_PID_Pos (0UL)
3124 #define GPIO_P1_02_MODE_REG_PID_Msk (0x3fUL)
3125 /* ==================================================== P1_03_MODE_REG ===================================================== */
3126 #define GPIO_P1_03_MODE_REG_PPOD_Pos (10UL)
3127 #define GPIO_P1_03_MODE_REG_PPOD_Msk (0x400UL)
3128 #define GPIO_P1_03_MODE_REG_PUPD_Pos (8UL)
3129 #define GPIO_P1_03_MODE_REG_PUPD_Msk (0x300UL)
3130 #define GPIO_P1_03_MODE_REG_PID_Pos (0UL)
3131 #define GPIO_P1_03_MODE_REG_PID_Msk (0x3fUL)
3132 /* ==================================================== P1_04_MODE_REG ===================================================== */
3133 #define GPIO_P1_04_MODE_REG_PPOD_Pos (10UL)
3134 #define GPIO_P1_04_MODE_REG_PPOD_Msk (0x400UL)
3135 #define GPIO_P1_04_MODE_REG_PUPD_Pos (8UL)
3136 #define GPIO_P1_04_MODE_REG_PUPD_Msk (0x300UL)
3137 #define GPIO_P1_04_MODE_REG_PID_Pos (0UL)
3138 #define GPIO_P1_04_MODE_REG_PID_Msk (0x3fUL)
3139 /* ==================================================== P1_05_MODE_REG ===================================================== */
3140 #define GPIO_P1_05_MODE_REG_PPOD_Pos (10UL)
3141 #define GPIO_P1_05_MODE_REG_PPOD_Msk (0x400UL)
3142 #define GPIO_P1_05_MODE_REG_PUPD_Pos (8UL)
3143 #define GPIO_P1_05_MODE_REG_PUPD_Msk (0x300UL)
3144 #define GPIO_P1_05_MODE_REG_PID_Pos (0UL)
3145 #define GPIO_P1_05_MODE_REG_PID_Msk (0x3fUL)
3146 /* ==================================================== P1_06_MODE_REG ===================================================== */
3147 #define GPIO_P1_06_MODE_REG_PPOD_Pos (10UL)
3148 #define GPIO_P1_06_MODE_REG_PPOD_Msk (0x400UL)
3149 #define GPIO_P1_06_MODE_REG_PUPD_Pos (8UL)
3150 #define GPIO_P1_06_MODE_REG_PUPD_Msk (0x300UL)
3151 #define GPIO_P1_06_MODE_REG_PID_Pos (0UL)
3152 #define GPIO_P1_06_MODE_REG_PID_Msk (0x3fUL)
3153 /* ==================================================== P1_07_MODE_REG ===================================================== */
3154 #define GPIO_P1_07_MODE_REG_PPOD_Pos (10UL)
3155 #define GPIO_P1_07_MODE_REG_PPOD_Msk (0x400UL)
3156 #define GPIO_P1_07_MODE_REG_PUPD_Pos (8UL)
3157 #define GPIO_P1_07_MODE_REG_PUPD_Msk (0x300UL)
3158 #define GPIO_P1_07_MODE_REG_PID_Pos (0UL)
3159 #define GPIO_P1_07_MODE_REG_PID_Msk (0x3fUL)
3160 /* ==================================================== P1_08_MODE_REG ===================================================== */
3161 #define GPIO_P1_08_MODE_REG_PPOD_Pos (10UL)
3162 #define GPIO_P1_08_MODE_REG_PPOD_Msk (0x400UL)
3163 #define GPIO_P1_08_MODE_REG_PUPD_Pos (8UL)
3164 #define GPIO_P1_08_MODE_REG_PUPD_Msk (0x300UL)
3165 #define GPIO_P1_08_MODE_REG_PID_Pos (0UL)
3166 #define GPIO_P1_08_MODE_REG_PID_Msk (0x3fUL)
3167 /* ==================================================== P1_09_MODE_REG ===================================================== */
3168 #define GPIO_P1_09_MODE_REG_PPOD_Pos (10UL)
3169 #define GPIO_P1_09_MODE_REG_PPOD_Msk (0x400UL)
3170 #define GPIO_P1_09_MODE_REG_PUPD_Pos (8UL)
3171 #define GPIO_P1_09_MODE_REG_PUPD_Msk (0x300UL)
3172 #define GPIO_P1_09_MODE_REG_PID_Pos (0UL)
3173 #define GPIO_P1_09_MODE_REG_PID_Msk (0x3fUL)
3174 /* ==================================================== P1_10_MODE_REG ===================================================== */
3175 #define GPIO_P1_10_MODE_REG_PPOD_Pos (10UL)
3176 #define GPIO_P1_10_MODE_REG_PPOD_Msk (0x400UL)
3177 #define GPIO_P1_10_MODE_REG_PUPD_Pos (8UL)
3178 #define GPIO_P1_10_MODE_REG_PUPD_Msk (0x300UL)
3179 #define GPIO_P1_10_MODE_REG_PID_Pos (0UL)
3180 #define GPIO_P1_10_MODE_REG_PID_Msk (0x3fUL)
3181 /* ==================================================== P1_11_MODE_REG ===================================================== */
3182 #define GPIO_P1_11_MODE_REG_PPOD_Pos (10UL)
3183 #define GPIO_P1_11_MODE_REG_PPOD_Msk (0x400UL)
3184 #define GPIO_P1_11_MODE_REG_PUPD_Pos (8UL)
3185 #define GPIO_P1_11_MODE_REG_PUPD_Msk (0x300UL)
3186 #define GPIO_P1_11_MODE_REG_PID_Pos (0UL)
3187 #define GPIO_P1_11_MODE_REG_PID_Msk (0x3fUL)
3188 /* ==================================================== P1_12_MODE_REG ===================================================== */
3189 #define GPIO_P1_12_MODE_REG_PPOD_Pos (10UL)
3190 #define GPIO_P1_12_MODE_REG_PPOD_Msk (0x400UL)
3191 #define GPIO_P1_12_MODE_REG_PUPD_Pos (8UL)
3192 #define GPIO_P1_12_MODE_REG_PUPD_Msk (0x300UL)
3193 #define GPIO_P1_12_MODE_REG_PID_Pos (0UL)
3194 #define GPIO_P1_12_MODE_REG_PID_Msk (0x3fUL)
3195 /* ==================================================== P1_13_MODE_REG ===================================================== */
3196 #define GPIO_P1_13_MODE_REG_PPOD_Pos (10UL)
3197 #define GPIO_P1_13_MODE_REG_PPOD_Msk (0x400UL)
3198 #define GPIO_P1_13_MODE_REG_PUPD_Pos (8UL)
3199 #define GPIO_P1_13_MODE_REG_PUPD_Msk (0x300UL)
3200 #define GPIO_P1_13_MODE_REG_PID_Pos (0UL)
3201 #define GPIO_P1_13_MODE_REG_PID_Msk (0x3fUL)
3202 /* ==================================================== P1_14_MODE_REG ===================================================== */
3203 #define GPIO_P1_14_MODE_REG_PPOD_Pos (10UL)
3204 #define GPIO_P1_14_MODE_REG_PPOD_Msk (0x400UL)
3205 #define GPIO_P1_14_MODE_REG_PUPD_Pos (8UL)
3206 #define GPIO_P1_14_MODE_REG_PUPD_Msk (0x300UL)
3207 #define GPIO_P1_14_MODE_REG_PID_Pos (0UL)
3208 #define GPIO_P1_14_MODE_REG_PID_Msk (0x3fUL)
3209 /* ==================================================== P1_15_MODE_REG ===================================================== */
3210 #define GPIO_P1_15_MODE_REG_PPOD_Pos (10UL)
3211 #define GPIO_P1_15_MODE_REG_PPOD_Msk (0x400UL)
3212 #define GPIO_P1_15_MODE_REG_PUPD_Pos (8UL)
3213 #define GPIO_P1_15_MODE_REG_PUPD_Msk (0x300UL)
3214 #define GPIO_P1_15_MODE_REG_PID_Pos (0UL)
3215 #define GPIO_P1_15_MODE_REG_PID_Msk (0x3fUL)
3216 /* ====================================================== P1_DATA_REG ====================================================== */
3217 #define GPIO_P1_DATA_REG_P1_DATA_Pos (0UL)
3218 #define GPIO_P1_DATA_REG_P1_DATA_Msk (0xffffUL)
3219 /* =================================================== P1_RESET_DATA_REG =================================================== */
3220 #define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL)
3221 #define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0xffffUL)
3222 /* ==================================================== P1_SET_DATA_REG ==================================================== */
3223 #define GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL)
3224 #define GPIO_P1_SET_DATA_REG_P1_SET_Msk (0xffffUL)
3225 /* =================================================== P1_WEAK_CTRL_REG ==================================================== */
3226 #define GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Pos (0UL)
3227 #define GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Msk (0xffffUL)
3230 /* =========================================================================================================================== */
3231 /* ================ GPREG ================ */
3232 /* =========================================================================================================================== */
3233 
3234 /* ======================================================= DEBUG_REG ======================================================= */
3235 #define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos (8UL)
3236 #define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk (0x100UL)
3237 #define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (7UL)
3238 #define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x80UL)
3239 #define GPREG_DEBUG_REG_SYS_CPUWAIT_Pos (6UL)
3240 #define GPREG_DEBUG_REG_SYS_CPUWAIT_Msk (0x40UL)
3241 #define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos (5UL)
3242 #define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk (0x20UL)
3243 #define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (4UL)
3244 #define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x10UL)
3245 #define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos (3UL)
3246 #define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk (0x8UL)
3247 #define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos (2UL)
3248 #define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk (0x4UL)
3249 #define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos (1UL)
3250 #define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk (0x2UL)
3251 #define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL)
3252 #define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL)
3253 /* ===================================================== GP_STATUS_REG ===================================================== */
3254 #define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL)
3255 #define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL)
3256 /* =================================================== RESET_FREEZE_REG ==================================================== */
3257 #define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)
3258 #define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)
3259 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)
3260 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)
3261 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)
3262 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)
3263 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)
3264 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)
3265 #define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL)
3266 #define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)
3267 #define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)
3268 #define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)
3269 #define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)
3270 #define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)
3271 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)
3272 #define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)
3273 #define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)
3274 #define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)
3275 /* =================================================== SCPU_FCU_TAG_REG ==================================================== */
3276 #define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Pos (1UL)
3277 #define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Msk (0x2UL)
3278 #define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Pos (0UL)
3279 #define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Msk (0x1UL)
3280 /* ==================================================== SET_FREEZE_REG ===================================================== */
3281 #define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)
3282 #define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)
3283 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)
3284 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)
3285 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)
3286 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)
3287 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)
3288 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)
3289 #define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos (5UL)
3290 #define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)
3291 #define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)
3292 #define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)
3293 #define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)
3294 #define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)
3295 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)
3296 #define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)
3297 #define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)
3298 #define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)
3301 /* =========================================================================================================================== */
3302 /* ================ I2C ================ */
3303 /* =========================================================================================================================== */
3304 
3305 /* =============================================== I2C_ACK_GENERAL_CALL_REG ================================================ */
3306 #define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)
3307 #define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)
3308 /* ================================================= I2C_CLR_ACTIVITY_REG ================================================== */
3309 #define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)
3310 #define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)
3311 /* ================================================= I2C_CLR_GEN_CALL_REG ================================================== */
3312 #define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)
3313 #define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)
3314 /* =================================================== I2C_CLR_INTR_REG ==================================================== */
3315 #define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL)
3316 #define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL)
3317 /* ================================================== I2C_CLR_RD_REQ_REG =================================================== */
3318 #define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)
3319 #define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)
3320 /* ================================================== I2C_CLR_RX_DONE_REG ================================================== */
3321 #define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)
3322 #define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)
3323 /* ================================================== I2C_CLR_RX_OVER_REG ================================================== */
3324 #define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)
3325 #define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)
3326 /* ================================================= I2C_CLR_RX_UNDER_REG ================================================== */
3327 #define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)
3328 #define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)
3329 /* ================================================= I2C_CLR_START_DET_REG ================================================= */
3330 #define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)
3331 #define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)
3332 /* ================================================= I2C_CLR_STOP_DET_REG ================================================== */
3333 #define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL)
3334 #define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL)
3335 /* ================================================== I2C_CLR_TX_ABRT_REG ================================================== */
3336 #define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)
3337 #define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)
3338 /* ================================================== I2C_CLR_TX_OVER_REG ================================================== */
3339 #define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)
3340 #define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)
3341 /* ====================================================== I2C_CON_REG ====================================================== */
3342 #define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL)
3343 #define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL)
3344 #define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL)
3345 #define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL)
3346 #define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL)
3347 #define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL)
3348 #define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL)
3349 #define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL)
3350 #define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)
3351 #define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)
3352 #define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL)
3353 #define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL)
3354 #define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)
3355 #define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)
3356 #define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)
3357 #define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)
3358 #define I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL)
3359 #define I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL)
3360 #define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL)
3361 #define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL)
3362 /* =================================================== I2C_DATA_CMD_REG ==================================================== */
3363 #define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL)
3364 #define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL)
3365 #define I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL)
3366 #define I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL)
3367 #define I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos (8UL)
3368 #define I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk (0x100UL)
3369 #define I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos (0UL)
3370 #define I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk (0xffUL)
3371 /* ==================================================== I2C_DMA_CR_REG ===================================================== */
3372 #define I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL)
3373 #define I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL)
3374 #define I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL)
3375 #define I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL)
3376 /* =================================================== I2C_DMA_RDLR_REG ==================================================== */
3377 #define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL)
3378 #define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL)
3379 /* =================================================== I2C_DMA_TDLR_REG ==================================================== */
3380 #define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL)
3381 #define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL)
3382 /* ==================================================== I2C_ENABLE_REG ===================================================== */
3383 #define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL)
3384 #define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL)
3385 #define I2C_I2C_ENABLE_REG_I2C_ABORT_Pos (1UL)
3386 #define I2C_I2C_ENABLE_REG_I2C_ABORT_Msk (0x2UL)
3387 #define I2C_I2C_ENABLE_REG_I2C_EN_Pos (0UL)
3388 #define I2C_I2C_ENABLE_REG_I2C_EN_Msk (0x1UL)
3389 /* ================================================= I2C_ENABLE_STATUS_REG ================================================= */
3390 #define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)
3391 #define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)
3392 #define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL)
3393 #define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL)
3394 #define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL)
3395 #define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL)
3396 /* ================================================== I2C_FS_SCL_HCNT_REG ================================================== */
3397 #define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)
3398 #define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)
3399 /* ================================================== I2C_FS_SCL_LCNT_REG ================================================== */
3400 #define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)
3401 #define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)
3402 /* =================================================== I2C_HS_MADDR_REG ==================================================== */
3403 #define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL)
3404 #define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL)
3405 /* ================================================== I2C_HS_SCL_HCNT_REG ================================================== */
3406 #define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL)
3407 #define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL)
3408 /* ================================================== I2C_HS_SCL_LCNT_REG ================================================== */
3409 #define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL)
3410 #define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL)
3411 /* ================================================= I2C_IC_FS_SPKLEN_REG ================================================== */
3412 #define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL)
3413 #define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL)
3414 /* ================================================= I2C_IC_HS_SPKLEN_REG ================================================== */
3415 #define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL)
3416 #define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL)
3417 /* =================================================== I2C_INTR_MASK_REG =================================================== */
3418 #define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL)
3419 #define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL)
3420 #define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL)
3421 #define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL)
3422 #define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL)
3423 #define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL)
3424 #define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL)
3425 #define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL)
3426 #define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL)
3427 #define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL)
3428 #define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL)
3429 #define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL)
3430 #define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL)
3431 #define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL)
3432 #define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL)
3433 #define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL)
3434 #define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL)
3435 #define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL)
3436 #define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL)
3437 #define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL)
3438 #define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL)
3439 #define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL)
3440 #define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL)
3441 #define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL)
3442 #define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL)
3443 #define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL)
3444 #define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL)
3445 #define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL)
3446 #define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL)
3447 #define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL)
3448 /* =================================================== I2C_INTR_STAT_REG =================================================== */
3449 #define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL)
3450 #define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL)
3451 #define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL)
3452 #define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL)
3453 #define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL)
3454 #define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL)
3455 #define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL)
3456 #define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL)
3457 #define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL)
3458 #define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL)
3459 #define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL)
3460 #define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL)
3461 #define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL)
3462 #define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL)
3463 #define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL)
3464 #define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL)
3465 #define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL)
3466 #define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL)
3467 #define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL)
3468 #define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL)
3469 #define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL)
3470 #define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL)
3471 #define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL)
3472 #define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL)
3473 #define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL)
3474 #define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL)
3475 #define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL)
3476 #define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL)
3477 #define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL)
3478 #define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL)
3479 /* ================================================= I2C_RAW_INTR_STAT_REG ================================================= */
3480 #define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL)
3481 #define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL)
3482 #define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL)
3483 #define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL)
3484 #define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL)
3485 #define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL)
3486 #define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)
3487 #define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)
3488 #define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL)
3489 #define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)
3490 #define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)
3491 #define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)
3492 #define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)
3493 #define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)
3494 #define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)
3495 #define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)
3496 #define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)
3497 #define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)
3498 #define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL)
3499 #define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL)
3500 #define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)
3501 #define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)
3502 #define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)
3503 #define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)
3504 #define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)
3505 #define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)
3506 #define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)
3507 #define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)
3508 #define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)
3509 #define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)
3510 /* ===================================================== I2C_RXFLR_REG ===================================================== */
3511 #define I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL)
3512 #define I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL)
3513 /* ===================================================== I2C_RX_TL_REG ===================================================== */
3514 #define I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL)
3515 #define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL)
3516 /* ====================================================== I2C_SAR_REG ====================================================== */
3517 #define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL)
3518 #define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL)
3519 /* =================================================== I2C_SDA_HOLD_REG ==================================================== */
3520 #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL)
3521 #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL)
3522 #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL)
3523 #define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL)
3524 /* =================================================== I2C_SDA_SETUP_REG =================================================== */
3525 #define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL)
3526 #define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL)
3527 /* ================================================== I2C_SS_SCL_HCNT_REG ================================================== */
3528 #define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)
3529 #define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)
3530 /* ================================================== I2C_SS_SCL_LCNT_REG ================================================== */
3531 #define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)
3532 #define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)
3533 /* ==================================================== I2C_STATUS_REG ===================================================== */
3534 #define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL)
3535 #define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL)
3536 #define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL)
3537 #define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL)
3538 #define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL)
3539 #define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL)
3540 #define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL)
3541 #define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL)
3542 #define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL)
3543 #define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL)
3544 #define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL)
3545 #define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL)
3546 #define I2C_I2C_STATUS_REG_RFF_Pos (4UL)
3547 #define I2C_I2C_STATUS_REG_RFF_Msk (0x10UL)
3548 #define I2C_I2C_STATUS_REG_RFNE_Pos (3UL)
3549 #define I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL)
3550 #define I2C_I2C_STATUS_REG_TFE_Pos (2UL)
3551 #define I2C_I2C_STATUS_REG_TFE_Msk (0x4UL)
3552 #define I2C_I2C_STATUS_REG_TFNF_Pos (1UL)
3553 #define I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL)
3554 #define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL)
3555 #define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL)
3556 /* ====================================================== I2C_TAR_REG ====================================================== */
3557 #define I2C_I2C_TAR_REG_SPECIAL_Pos (11UL)
3558 #define I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL)
3559 #define I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL)
3560 #define I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL)
3561 #define I2C_I2C_TAR_REG_IC_TAR_Pos (0UL)
3562 #define I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL)
3563 /* ===================================================== I2C_TXFLR_REG ===================================================== */
3564 #define I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL)
3565 #define I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL)
3566 /* ================================================ I2C_TX_ABRT_SOURCE_REG ================================================= */
3567 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL)
3568 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL)
3569 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)
3570 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL)
3571 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)
3572 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL)
3573 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL)
3574 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL)
3575 #define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)
3576 #define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)
3577 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)
3578 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)
3579 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL)
3580 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL)
3581 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)
3582 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL)
3583 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)
3584 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)
3585 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)
3586 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL)
3587 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)
3588 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)
3589 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)
3590 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)
3591 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)
3592 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)
3593 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)
3594 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)
3595 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)
3596 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL)
3597 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)
3598 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL)
3599 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)
3600 #define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL)
3601 /* ===================================================== I2C_TX_TL_REG ===================================================== */
3602 #define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL)
3603 #define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL)
3606 /* =========================================================================================================================== */
3607 /* ================ MDCT ================ */
3608 /* =========================================================================================================================== */
3609 
3610 /* ===================================================== MDCT_CTRL_REG ===================================================== */
3611 #define MDCT_MDCT_CTRL_REG_DONE_Pos (31UL)
3612 #define MDCT_MDCT_CTRL_REG_DONE_Msk (0x80000000UL)
3613 #define MDCT_MDCT_CTRL_REG_USE_CORDIC_Pos (29UL)
3614 #define MDCT_MDCT_CTRL_REG_USE_CORDIC_Msk (0x20000000UL)
3615 #define MDCT_MDCT_CTRL_REG_IRQ_CLR_Pos (28UL)
3616 #define MDCT_MDCT_CTRL_REG_IRQ_CLR_Msk (0x10000000UL)
3617 #define MDCT_MDCT_CTRL_REG_CLK_DIV_Pos (26UL)
3618 #define MDCT_MDCT_CTRL_REG_CLK_DIV_Msk (0xc000000UL)
3619 #define MDCT_MDCT_CTRL_REG_XFORM_SIZE_Pos (16UL)
3620 #define MDCT_MDCT_CTRL_REG_XFORM_SIZE_Msk (0x3ff0000UL)
3621 #define MDCT_MDCT_CTRL_REG_Y_STRIDE_Pos (8UL)
3622 #define MDCT_MDCT_CTRL_REG_Y_STRIDE_Msk (0xff00UL)
3623 #define MDCT_MDCT_CTRL_REG_WORD_SIZE_Pos (7UL)
3624 #define MDCT_MDCT_CTRL_REG_WORD_SIZE_Msk (0x80UL)
3625 #define MDCT_MDCT_CTRL_REG_INVERSE_Pos (6UL)
3626 #define MDCT_MDCT_CTRL_REG_INVERSE_Msk (0x40UL)
3627 #define MDCT_MDCT_CTRL_REG_N_STAGES_Pos (2UL)
3628 #define MDCT_MDCT_CTRL_REG_N_STAGES_Msk (0x3cUL)
3629 #define MDCT_MDCT_CTRL_REG_IRQ_EN_Pos (1UL)
3630 #define MDCT_MDCT_CTRL_REG_IRQ_EN_Msk (0x2UL)
3631 #define MDCT_MDCT_CTRL_REG_EN_Pos (0UL)
3632 #define MDCT_MDCT_CTRL_REG_EN_Msk (0x1UL)
3633 /* ================================================== MDCT_PHASE_INC_REG =================================================== */
3634 #define MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Pos (0UL)
3635 #define MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Msk (0xffffffffUL)
3636 /* ==================================================== MDCT_STAGE0_REG ==================================================== */
3637 #define MDCT_MDCT_STAGE0_REG_STRIDE_Pos (22UL)
3638 #define MDCT_MDCT_STAGE0_REG_STRIDE_Msk (0xffc00000UL)
3639 #define MDCT_MDCT_STAGE0_REG_M_Pos (12UL)
3640 #define MDCT_MDCT_STAGE0_REG_M_Msk (0x3ff000UL)
3641 #define MDCT_MDCT_STAGE0_REG_RADIX_Pos (8UL)
3642 #define MDCT_MDCT_STAGE0_REG_RADIX_Msk (0x700UL)
3643 #define MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Pos (6UL)
3644 #define MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Msk (0x40UL)
3645 #define MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Pos (5UL)
3646 #define MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Msk (0x20UL)
3647 #define MDCT_MDCT_STAGE0_REG_IN_BUFFER_Pos (4UL)
3648 #define MDCT_MDCT_STAGE0_REG_IN_BUFFER_Msk (0x10UL)
3649 #define MDCT_MDCT_STAGE0_REG_MODE_Pos (0UL)
3650 #define MDCT_MDCT_STAGE0_REG_MODE_Msk (0x7UL)
3651 /* ==================================================== MDCT_STAGE1_REG ==================================================== */
3652 #define MDCT_MDCT_STAGE1_REG_STRIDE_Pos (22UL)
3653 #define MDCT_MDCT_STAGE1_REG_STRIDE_Msk (0xffc00000UL)
3654 #define MDCT_MDCT_STAGE1_REG_M_Pos (12UL)
3655 #define MDCT_MDCT_STAGE1_REG_M_Msk (0x3ff000UL)
3656 #define MDCT_MDCT_STAGE1_REG_RADIX_Pos (8UL)
3657 #define MDCT_MDCT_STAGE1_REG_RADIX_Msk (0x700UL)
3658 #define MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Pos (6UL)
3659 #define MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Msk (0x40UL)
3660 #define MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Pos (5UL)
3661 #define MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Msk (0x20UL)
3662 #define MDCT_MDCT_STAGE1_REG_IN_BUFFER_Pos (4UL)
3663 #define MDCT_MDCT_STAGE1_REG_IN_BUFFER_Msk (0x10UL)
3664 #define MDCT_MDCT_STAGE1_REG_MODE_Pos (0UL)
3665 #define MDCT_MDCT_STAGE1_REG_MODE_Msk (0x7UL)
3666 /* ==================================================== MDCT_STAGE2_REG ==================================================== */
3667 #define MDCT_MDCT_STAGE2_REG_STRIDE_Pos (22UL)
3668 #define MDCT_MDCT_STAGE2_REG_STRIDE_Msk (0xffc00000UL)
3669 #define MDCT_MDCT_STAGE2_REG_M_Pos (12UL)
3670 #define MDCT_MDCT_STAGE2_REG_M_Msk (0x3ff000UL)
3671 #define MDCT_MDCT_STAGE2_REG_RADIX_Pos (8UL)
3672 #define MDCT_MDCT_STAGE2_REG_RADIX_Msk (0x700UL)
3673 #define MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Pos (6UL)
3674 #define MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Msk (0x40UL)
3675 #define MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Pos (5UL)
3676 #define MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Msk (0x20UL)
3677 #define MDCT_MDCT_STAGE2_REG_IN_BUFFER_Pos (4UL)
3678 #define MDCT_MDCT_STAGE2_REG_IN_BUFFER_Msk (0x10UL)
3679 #define MDCT_MDCT_STAGE2_REG_MODE_Pos (0UL)
3680 #define MDCT_MDCT_STAGE2_REG_MODE_Msk (0x7UL)
3681 /* ==================================================== MDCT_STAGE3_REG ==================================================== */
3682 #define MDCT_MDCT_STAGE3_REG_STRIDE_Pos (22UL)
3683 #define MDCT_MDCT_STAGE3_REG_STRIDE_Msk (0xffc00000UL)
3684 #define MDCT_MDCT_STAGE3_REG_M_Pos (12UL)
3685 #define MDCT_MDCT_STAGE3_REG_M_Msk (0x3ff000UL)
3686 #define MDCT_MDCT_STAGE3_REG_RADIX_Pos (8UL)
3687 #define MDCT_MDCT_STAGE3_REG_RADIX_Msk (0x700UL)
3688 #define MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Pos (6UL)
3689 #define MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Msk (0x40UL)
3690 #define MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Pos (5UL)
3691 #define MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Msk (0x20UL)
3692 #define MDCT_MDCT_STAGE3_REG_IN_BUFFER_Pos (4UL)
3693 #define MDCT_MDCT_STAGE3_REG_IN_BUFFER_Msk (0x10UL)
3694 #define MDCT_MDCT_STAGE3_REG_MODE_Pos (0UL)
3695 #define MDCT_MDCT_STAGE3_REG_MODE_Msk (0x7UL)
3696 /* ==================================================== MDCT_STAGE4_REG ==================================================== */
3697 #define MDCT_MDCT_STAGE4_REG_STRIDE_Pos (22UL)
3698 #define MDCT_MDCT_STAGE4_REG_STRIDE_Msk (0xffc00000UL)
3699 #define MDCT_MDCT_STAGE4_REG_M_Pos (12UL)
3700 #define MDCT_MDCT_STAGE4_REG_M_Msk (0x3ff000UL)
3701 #define MDCT_MDCT_STAGE4_REG_RADIX_Pos (8UL)
3702 #define MDCT_MDCT_STAGE4_REG_RADIX_Msk (0x700UL)
3703 #define MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Pos (6UL)
3704 #define MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Msk (0x40UL)
3705 #define MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Pos (5UL)
3706 #define MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Msk (0x20UL)
3707 #define MDCT_MDCT_STAGE4_REG_IN_BUFFER_Pos (4UL)
3708 #define MDCT_MDCT_STAGE4_REG_IN_BUFFER_Msk (0x10UL)
3709 #define MDCT_MDCT_STAGE4_REG_MODE_Pos (0UL)
3710 #define MDCT_MDCT_STAGE4_REG_MODE_Msk (0x7UL)
3711 /* ==================================================== MDCT_STAGE5_REG ==================================================== */
3712 #define MDCT_MDCT_STAGE5_REG_STRIDE_Pos (22UL)
3713 #define MDCT_MDCT_STAGE5_REG_STRIDE_Msk (0xffc00000UL)
3714 #define MDCT_MDCT_STAGE5_REG_M_Pos (12UL)
3715 #define MDCT_MDCT_STAGE5_REG_M_Msk (0x3ff000UL)
3716 #define MDCT_MDCT_STAGE5_REG_RADIX_Pos (8UL)
3717 #define MDCT_MDCT_STAGE5_REG_RADIX_Msk (0x700UL)
3718 #define MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Pos (6UL)
3719 #define MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Msk (0x40UL)
3720 #define MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Pos (5UL)
3721 #define MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Msk (0x20UL)
3722 #define MDCT_MDCT_STAGE5_REG_IN_BUFFER_Pos (4UL)
3723 #define MDCT_MDCT_STAGE5_REG_IN_BUFFER_Msk (0x10UL)
3724 #define MDCT_MDCT_STAGE5_REG_MODE_Pos (0UL)
3725 #define MDCT_MDCT_STAGE5_REG_MODE_Msk (0x7UL)
3726 /* ==================================================== MDCT_STAGE6_REG ==================================================== */
3727 #define MDCT_MDCT_STAGE6_REG_STRIDE_Pos (22UL)
3728 #define MDCT_MDCT_STAGE6_REG_STRIDE_Msk (0xffc00000UL)
3729 #define MDCT_MDCT_STAGE6_REG_M_Pos (12UL)
3730 #define MDCT_MDCT_STAGE6_REG_M_Msk (0x3ff000UL)
3731 #define MDCT_MDCT_STAGE6_REG_RADIX_Pos (8UL)
3732 #define MDCT_MDCT_STAGE6_REG_RADIX_Msk (0x700UL)
3733 #define MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Pos (6UL)
3734 #define MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Msk (0x40UL)
3735 #define MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Pos (5UL)
3736 #define MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Msk (0x20UL)
3737 #define MDCT_MDCT_STAGE6_REG_IN_BUFFER_Pos (4UL)
3738 #define MDCT_MDCT_STAGE6_REG_IN_BUFFER_Msk (0x10UL)
3739 #define MDCT_MDCT_STAGE6_REG_MODE_Pos (0UL)
3740 #define MDCT_MDCT_STAGE6_REG_MODE_Msk (0x7UL)
3741 /* ==================================================== MDCT_STAGE7_REG ==================================================== */
3742 #define MDCT_MDCT_STAGE7_REG_STRIDE_Pos (22UL)
3743 #define MDCT_MDCT_STAGE7_REG_STRIDE_Msk (0xffc00000UL)
3744 #define MDCT_MDCT_STAGE7_REG_M_Pos (12UL)
3745 #define MDCT_MDCT_STAGE7_REG_M_Msk (0x3ff000UL)
3746 #define MDCT_MDCT_STAGE7_REG_RADIX_Pos (8UL)
3747 #define MDCT_MDCT_STAGE7_REG_RADIX_Msk (0x700UL)
3748 #define MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Pos (6UL)
3749 #define MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Msk (0x40UL)
3750 #define MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Pos (5UL)
3751 #define MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Msk (0x20UL)
3752 #define MDCT_MDCT_STAGE7_REG_IN_BUFFER_Pos (4UL)
3753 #define MDCT_MDCT_STAGE7_REG_IN_BUFFER_Msk (0x10UL)
3754 #define MDCT_MDCT_STAGE7_REG_MODE_Pos (0UL)
3755 #define MDCT_MDCT_STAGE7_REG_MODE_Msk (0x7UL)
3756 /* ================================================== MDCT_XBASE_ADDR_REG ================================================== */
3757 #define MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Pos (0UL)
3758 #define MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Msk (0xffffffffUL)
3759 /* ================================================== MDCT_YBASE_ADDR_REG ================================================== */
3760 #define MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Pos (0UL)
3761 #define MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Msk (0xffffffffUL)
3762 /* ================================================== MDCT_ZBASE_ADDR_REG ================================================== */
3763 #define MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Pos (0UL)
3764 #define MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Msk (0xffffffffUL)
3767 /* =========================================================================================================================== */
3768 /* ================ MEMCTRL ================ */
3769 /* =========================================================================================================================== */
3770 
3771 /* ==================================================== BUSY_RESET_REG ===================================================== */
3772 #define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos (30UL)
3773 #define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk (0xc0000000UL)
3774 #define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Pos (28UL)
3775 #define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Msk (0x30000000UL)
3776 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Pos (26UL)
3777 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Msk (0xc000000UL)
3778 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Pos (24UL)
3779 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Msk (0x3000000UL)
3780 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos (22UL)
3781 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk (0xc00000UL)
3782 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos (20UL)
3783 #define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk (0x300000UL)
3784 #define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos (18UL)
3785 #define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk (0xc0000UL)
3786 #define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos (16UL)
3787 #define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk (0x30000UL)
3788 #define MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Pos (14UL)
3789 #define MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Msk (0xc000UL)
3790 #define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos (12UL)
3791 #define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk (0x3000UL)
3792 #define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos (10UL)
3793 #define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk (0xc00UL)
3794 #define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos (8UL)
3795 #define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk (0x300UL)
3796 #define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos (6UL)
3797 #define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk (0xc0UL)
3798 #define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos (4UL)
3799 #define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk (0x30UL)
3800 #define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos (2UL)
3801 #define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk (0xcUL)
3802 #define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos (0UL)
3803 #define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk (0x3UL)
3804 /* ===================================================== BUSY_SET_REG ====================================================== */
3805 #define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos (30UL)
3806 #define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk (0xc0000000UL)
3807 #define MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Pos (28UL)
3808 #define MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Msk (0x30000000UL)
3809 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Pos (26UL)
3810 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Msk (0xc000000UL)
3811 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Pos (24UL)
3812 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Msk (0x3000000UL)
3813 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos (22UL)
3814 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk (0xc00000UL)
3815 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos (20UL)
3816 #define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk (0x300000UL)
3817 #define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos (18UL)
3818 #define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk (0xc0000UL)
3819 #define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos (16UL)
3820 #define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk (0x30000UL)
3821 #define MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Pos (14UL)
3822 #define MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Msk (0xc000UL)
3823 #define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos (12UL)
3824 #define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk (0x3000UL)
3825 #define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos (10UL)
3826 #define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk (0xc00UL)
3827 #define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos (8UL)
3828 #define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk (0x300UL)
3829 #define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos (6UL)
3830 #define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk (0xc0UL)
3831 #define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos (4UL)
3832 #define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk (0x30UL)
3833 #define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos (2UL)
3834 #define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk (0xcUL)
3835 #define MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos (0UL)
3836 #define MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk (0x3UL)
3837 /* ===================================================== BUSY_STAT_REG ===================================================== */
3838 #define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos (30UL)
3839 #define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk (0xc0000000UL)
3840 #define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Pos (28UL)
3841 #define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Msk (0x30000000UL)
3842 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Pos (26UL)
3843 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Msk (0xc000000UL)
3844 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Pos (24UL)
3845 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Msk (0x3000000UL)
3846 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos (22UL)
3847 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk (0xc00000UL)
3848 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos (20UL)
3849 #define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk (0x300000UL)
3850 #define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos (18UL)
3851 #define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk (0xc0000UL)
3852 #define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos (16UL)
3853 #define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk (0x30000UL)
3854 #define MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Pos (14UL)
3855 #define MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Msk (0xc000UL)
3856 #define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos (12UL)
3857 #define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk (0x3000UL)
3858 #define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos (10UL)
3859 #define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk (0xc00UL)
3860 #define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos (8UL)
3861 #define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk (0x300UL)
3862 #define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos (6UL)
3863 #define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk (0xc0UL)
3864 #define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos (4UL)
3865 #define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk (0x30UL)
3866 #define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos (2UL)
3867 #define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk (0xcUL)
3868 #define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos (0UL)
3869 #define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk (0x3UL)
3870 /* =================================================== CMI_CODE_BASE_REG =================================================== */
3871 #define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos (8UL)
3872 #define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk (0x7ff00UL)
3873 /* =================================================== CMI_DATA_BASE_REG =================================================== */
3874 #define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos (2UL)
3875 #define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk (0x7fffcUL)
3876 /* ================================================== CMI_SHARED_BASE_REG ================================================== */
3877 #define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos (2UL)
3878 #define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk (0x7fffcUL)
3879 /* ===================================================== MEM_PRIO_REG ====================================================== */
3880 #define MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Pos (6UL)
3881 #define MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Msk (0x1c0UL)
3882 #define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos (3UL)
3883 #define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk (0x38UL)
3884 #define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos (0UL)
3885 #define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk (0x7UL)
3886 /* ===================================================== MEM_STALL_REG ===================================================== */
3887 #define MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Pos (8UL)
3888 #define MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Msk (0xf00UL)
3889 #define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos (4UL)
3890 #define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk (0xf0UL)
3891 #define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos (0UL)
3892 #define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk (0xfUL)
3893 /* ==================================================== MEM_STATUS2_REG ==================================================== */
3894 #define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos (2UL)
3895 #define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk (0x4UL)
3896 #define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos (1UL)
3897 #define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk (0x2UL)
3898 #define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos (0UL)
3899 #define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk (0x1UL)
3900 /* ==================================================== MEM_STATUS_REG ===================================================== */
3901 #define MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Pos (21UL)
3902 #define MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Msk (0x200000UL)
3903 #define MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Pos (20UL)
3904 #define MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Msk (0x100000UL)
3905 #define MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Pos (16UL)
3906 #define MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Msk (0xf0000UL)
3907 #define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos (12UL)
3908 #define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk (0xf000UL)
3909 #define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos (8UL)
3910 #define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk (0xf00UL)
3911 #define MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Pos (6UL)
3912 #define MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Msk (0x40UL)
3913 #define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos (5UL)
3914 #define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk (0x20UL)
3915 #define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos (4UL)
3916 #define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk (0x10UL)
3917 #define MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Pos (2UL)
3918 #define MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Msk (0x4UL)
3919 #define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos (1UL)
3920 #define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk (0x2UL)
3921 #define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos (0UL)
3922 #define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk (0x1UL)
3925 /* =========================================================================================================================== */
3926 /* ================ PCM1 ================ */
3927 /* =========================================================================================================================== */
3928 
3929 /* ===================================================== PCM1_CTRL_REG ===================================================== */
3930 #define PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL)
3931 #define PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL)
3932 #define PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL)
3933 #define PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL)
3934 #define PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Pos (11UL)
3935 #define PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Msk (0xf800UL)
3936 #define PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL)
3937 #define PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL)
3938 #define PCM1_PCM1_CTRL_REG_PCM_FSCINV_Pos (9UL)
3939 #define PCM1_PCM1_CTRL_REG_PCM_FSCINV_Msk (0x200UL)
3940 #define PCM1_PCM1_CTRL_REG_PCM_CLKINV_Pos (8UL)
3941 #define PCM1_PCM1_CTRL_REG_PCM_CLKINV_Msk (0x100UL)
3942 #define PCM1_PCM1_CTRL_REG_PCM_PPOD_Pos (7UL)
3943 #define PCM1_PCM1_CTRL_REG_PCM_PPOD_Msk (0x80UL)
3944 #define PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Pos (6UL)
3945 #define PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Msk (0x40UL)
3946 #define PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Pos (2UL)
3947 #define PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Msk (0x3cUL)
3948 #define PCM1_PCM1_CTRL_REG_PCM_MASTER_Pos (1UL)
3949 #define PCM1_PCM1_CTRL_REG_PCM_MASTER_Msk (0x2UL)
3950 #define PCM1_PCM1_CTRL_REG_PCM_EN_Pos (0UL)
3951 #define PCM1_PCM1_CTRL_REG_PCM_EN_Msk (0x1UL)
3952 /* ===================================================== PCM1_IN1_REG ====================================================== */
3953 #define PCM1_PCM1_IN1_REG_PCM_IN_Pos (0UL)
3954 #define PCM1_PCM1_IN1_REG_PCM_IN_Msk (0xffffffffUL)
3955 /* ===================================================== PCM1_IN2_REG ====================================================== */
3956 #define PCM1_PCM1_IN2_REG_PCM_IN_Pos (0UL)
3957 #define PCM1_PCM1_IN2_REG_PCM_IN_Msk (0xffffffffUL)
3958 /* ===================================================== PCM1_OUT1_REG ===================================================== */
3959 #define PCM1_PCM1_OUT1_REG_PCM_OUT_Pos (0UL)
3960 #define PCM1_PCM1_OUT1_REG_PCM_OUT_Msk (0xffffffffUL)
3961 /* ===================================================== PCM1_OUT2_REG ===================================================== */
3962 #define PCM1_PCM1_OUT2_REG_PCM_OUT_Pos (0UL)
3963 #define PCM1_PCM1_OUT2_REG_PCM_OUT_Msk (0xffffffffUL)
3966 /* =========================================================================================================================== */
3967 /* ================ PDC ================ */
3968 /* =========================================================================================================================== */
3969 
3970 /* ================================================== PDC_ACKNOWLEDGE_REG ================================================== */
3971 #define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos (0UL)
3972 #define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk (0x1fUL)
3973 /* ==================================================== PDC_CONFIG_REG ===================================================== */
3974 #define PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Pos (2UL)
3975 #define PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Msk (0x4UL)
3976 #define PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Pos (1UL)
3977 #define PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Msk (0x2UL)
3978 #define PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Pos (0UL)
3979 #define PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Msk (0x1UL)
3980 /* ===================================================== PDC_CTRL0_REG ===================================================== */
3981 #define PDC_PDC_CTRL0_REG_PDC_MASTER_Pos (11UL)
3982 #define PDC_PDC_CTRL0_REG_PDC_MASTER_Msk (0x1800UL)
3983 #define PDC_PDC_CTRL0_REG_EN_COM_Pos (10UL)
3984 #define PDC_PDC_CTRL0_REG_EN_COM_Msk (0x400UL)
3985 #define PDC_PDC_CTRL0_REG_EN_PER_Pos (9UL)
3986 #define PDC_PDC_CTRL0_REG_EN_PER_Msk (0x200UL)
3987 #define PDC_PDC_CTRL0_REG_EN_TMR_Pos (8UL)
3988 #define PDC_PDC_CTRL0_REG_EN_TMR_Msk (0x100UL)
3989 #define PDC_PDC_CTRL0_REG_EN_XTAL_Pos (7UL)
3990 #define PDC_PDC_CTRL0_REG_EN_XTAL_Msk (0x80UL)
3991 #define PDC_PDC_CTRL0_REG_TRIG_ID_Pos (2UL)
3992 #define PDC_PDC_CTRL0_REG_TRIG_ID_Msk (0x7cUL)
3993 #define PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos (0UL)
3994 #define PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk (0x3UL)
3995 /* ==================================================== PDC_CTRL10_REG ===================================================== */
3996 #define PDC_PDC_CTRL10_REG_PDC_MASTER_Pos (11UL)
3997 #define PDC_PDC_CTRL10_REG_PDC_MASTER_Msk (0x1800UL)
3998 #define PDC_PDC_CTRL10_REG_EN_COM_Pos (10UL)
3999 #define PDC_PDC_CTRL10_REG_EN_COM_Msk (0x400UL)
4000 #define PDC_PDC_CTRL10_REG_EN_PER_Pos (9UL)
4001 #define PDC_PDC_CTRL10_REG_EN_PER_Msk (0x200UL)
4002 #define PDC_PDC_CTRL10_REG_EN_TMR_Pos (8UL)
4003 #define PDC_PDC_CTRL10_REG_EN_TMR_Msk (0x100UL)
4004 #define PDC_PDC_CTRL10_REG_EN_XTAL_Pos (7UL)
4005 #define PDC_PDC_CTRL10_REG_EN_XTAL_Msk (0x80UL)
4006 #define PDC_PDC_CTRL10_REG_TRIG_ID_Pos (2UL)
4007 #define PDC_PDC_CTRL10_REG_TRIG_ID_Msk (0x7cUL)
4008 #define PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos (0UL)
4009 #define PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk (0x3UL)
4010 /* ==================================================== PDC_CTRL11_REG ===================================================== */
4011 #define PDC_PDC_CTRL11_REG_PDC_MASTER_Pos (11UL)
4012 #define PDC_PDC_CTRL11_REG_PDC_MASTER_Msk (0x1800UL)
4013 #define PDC_PDC_CTRL11_REG_EN_COM_Pos (10UL)
4014 #define PDC_PDC_CTRL11_REG_EN_COM_Msk (0x400UL)
4015 #define PDC_PDC_CTRL11_REG_EN_PER_Pos (9UL)
4016 #define PDC_PDC_CTRL11_REG_EN_PER_Msk (0x200UL)
4017 #define PDC_PDC_CTRL11_REG_EN_TMR_Pos (8UL)
4018 #define PDC_PDC_CTRL11_REG_EN_TMR_Msk (0x100UL)
4019 #define PDC_PDC_CTRL11_REG_EN_XTAL_Pos (7UL)
4020 #define PDC_PDC_CTRL11_REG_EN_XTAL_Msk (0x80UL)
4021 #define PDC_PDC_CTRL11_REG_TRIG_ID_Pos (2UL)
4022 #define PDC_PDC_CTRL11_REG_TRIG_ID_Msk (0x7cUL)
4023 #define PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos (0UL)
4024 #define PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk (0x3UL)
4025 /* ===================================================== PDC_CTRL1_REG ===================================================== */
4026 #define PDC_PDC_CTRL1_REG_PDC_MASTER_Pos (11UL)
4027 #define PDC_PDC_CTRL1_REG_PDC_MASTER_Msk (0x1800UL)
4028 #define PDC_PDC_CTRL1_REG_EN_COM_Pos (10UL)
4029 #define PDC_PDC_CTRL1_REG_EN_COM_Msk (0x400UL)
4030 #define PDC_PDC_CTRL1_REG_EN_PER_Pos (9UL)
4031 #define PDC_PDC_CTRL1_REG_EN_PER_Msk (0x200UL)
4032 #define PDC_PDC_CTRL1_REG_EN_TMR_Pos (8UL)
4033 #define PDC_PDC_CTRL1_REG_EN_TMR_Msk (0x100UL)
4034 #define PDC_PDC_CTRL1_REG_EN_XTAL_Pos (7UL)
4035 #define PDC_PDC_CTRL1_REG_EN_XTAL_Msk (0x80UL)
4036 #define PDC_PDC_CTRL1_REG_TRIG_ID_Pos (2UL)
4037 #define PDC_PDC_CTRL1_REG_TRIG_ID_Msk (0x7cUL)
4038 #define PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos (0UL)
4039 #define PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk (0x3UL)
4040 /* ===================================================== PDC_CTRL2_REG ===================================================== */
4041 #define PDC_PDC_CTRL2_REG_PDC_MASTER_Pos (11UL)
4042 #define PDC_PDC_CTRL2_REG_PDC_MASTER_Msk (0x1800UL)
4043 #define PDC_PDC_CTRL2_REG_EN_COM_Pos (10UL)
4044 #define PDC_PDC_CTRL2_REG_EN_COM_Msk (0x400UL)
4045 #define PDC_PDC_CTRL2_REG_EN_PER_Pos (9UL)
4046 #define PDC_PDC_CTRL2_REG_EN_PER_Msk (0x200UL)
4047 #define PDC_PDC_CTRL2_REG_EN_TMR_Pos (8UL)
4048 #define PDC_PDC_CTRL2_REG_EN_TMR_Msk (0x100UL)
4049 #define PDC_PDC_CTRL2_REG_EN_XTAL_Pos (7UL)
4050 #define PDC_PDC_CTRL2_REG_EN_XTAL_Msk (0x80UL)
4051 #define PDC_PDC_CTRL2_REG_TRIG_ID_Pos (2UL)
4052 #define PDC_PDC_CTRL2_REG_TRIG_ID_Msk (0x7cUL)
4053 #define PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos (0UL)
4054 #define PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk (0x3UL)
4055 /* ===================================================== PDC_CTRL3_REG ===================================================== */
4056 #define PDC_PDC_CTRL3_REG_PDC_MASTER_Pos (11UL)
4057 #define PDC_PDC_CTRL3_REG_PDC_MASTER_Msk (0x1800UL)
4058 #define PDC_PDC_CTRL3_REG_EN_COM_Pos (10UL)
4059 #define PDC_PDC_CTRL3_REG_EN_COM_Msk (0x400UL)
4060 #define PDC_PDC_CTRL3_REG_EN_PER_Pos (9UL)
4061 #define PDC_PDC_CTRL3_REG_EN_PER_Msk (0x200UL)
4062 #define PDC_PDC_CTRL3_REG_EN_TMR_Pos (8UL)
4063 #define PDC_PDC_CTRL3_REG_EN_TMR_Msk (0x100UL)
4064 #define PDC_PDC_CTRL3_REG_EN_XTAL_Pos (7UL)
4065 #define PDC_PDC_CTRL3_REG_EN_XTAL_Msk (0x80UL)
4066 #define PDC_PDC_CTRL3_REG_TRIG_ID_Pos (2UL)
4067 #define PDC_PDC_CTRL3_REG_TRIG_ID_Msk (0x7cUL)
4068 #define PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos (0UL)
4069 #define PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk (0x3UL)
4070 /* ===================================================== PDC_CTRL4_REG ===================================================== */
4071 #define PDC_PDC_CTRL4_REG_PDC_MASTER_Pos (11UL)
4072 #define PDC_PDC_CTRL4_REG_PDC_MASTER_Msk (0x1800UL)
4073 #define PDC_PDC_CTRL4_REG_EN_COM_Pos (10UL)
4074 #define PDC_PDC_CTRL4_REG_EN_COM_Msk (0x400UL)
4075 #define PDC_PDC_CTRL4_REG_EN_PER_Pos (9UL)
4076 #define PDC_PDC_CTRL4_REG_EN_PER_Msk (0x200UL)
4077 #define PDC_PDC_CTRL4_REG_EN_TMR_Pos (8UL)
4078 #define PDC_PDC_CTRL4_REG_EN_TMR_Msk (0x100UL)
4079 #define PDC_PDC_CTRL4_REG_EN_XTAL_Pos (7UL)
4080 #define PDC_PDC_CTRL4_REG_EN_XTAL_Msk (0x80UL)
4081 #define PDC_PDC_CTRL4_REG_TRIG_ID_Pos (2UL)
4082 #define PDC_PDC_CTRL4_REG_TRIG_ID_Msk (0x7cUL)
4083 #define PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos (0UL)
4084 #define PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk (0x3UL)
4085 /* ===================================================== PDC_CTRL5_REG ===================================================== */
4086 #define PDC_PDC_CTRL5_REG_PDC_MASTER_Pos (11UL)
4087 #define PDC_PDC_CTRL5_REG_PDC_MASTER_Msk (0x1800UL)
4088 #define PDC_PDC_CTRL5_REG_EN_COM_Pos (10UL)
4089 #define PDC_PDC_CTRL5_REG_EN_COM_Msk (0x400UL)
4090 #define PDC_PDC_CTRL5_REG_EN_PER_Pos (9UL)
4091 #define PDC_PDC_CTRL5_REG_EN_PER_Msk (0x200UL)
4092 #define PDC_PDC_CTRL5_REG_EN_TMR_Pos (8UL)
4093 #define PDC_PDC_CTRL5_REG_EN_TMR_Msk (0x100UL)
4094 #define PDC_PDC_CTRL5_REG_EN_XTAL_Pos (7UL)
4095 #define PDC_PDC_CTRL5_REG_EN_XTAL_Msk (0x80UL)
4096 #define PDC_PDC_CTRL5_REG_TRIG_ID_Pos (2UL)
4097 #define PDC_PDC_CTRL5_REG_TRIG_ID_Msk (0x7cUL)
4098 #define PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos (0UL)
4099 #define PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk (0x3UL)
4100 /* ===================================================== PDC_CTRL6_REG ===================================================== */
4101 #define PDC_PDC_CTRL6_REG_PDC_MASTER_Pos (11UL)
4102 #define PDC_PDC_CTRL6_REG_PDC_MASTER_Msk (0x1800UL)
4103 #define PDC_PDC_CTRL6_REG_EN_COM_Pos (10UL)
4104 #define PDC_PDC_CTRL6_REG_EN_COM_Msk (0x400UL)
4105 #define PDC_PDC_CTRL6_REG_EN_PER_Pos (9UL)
4106 #define PDC_PDC_CTRL6_REG_EN_PER_Msk (0x200UL)
4107 #define PDC_PDC_CTRL6_REG_EN_TMR_Pos (8UL)
4108 #define PDC_PDC_CTRL6_REG_EN_TMR_Msk (0x100UL)
4109 #define PDC_PDC_CTRL6_REG_EN_XTAL_Pos (7UL)
4110 #define PDC_PDC_CTRL6_REG_EN_XTAL_Msk (0x80UL)
4111 #define PDC_PDC_CTRL6_REG_TRIG_ID_Pos (2UL)
4112 #define PDC_PDC_CTRL6_REG_TRIG_ID_Msk (0x7cUL)
4113 #define PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos (0UL)
4114 #define PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk (0x3UL)
4115 /* ===================================================== PDC_CTRL7_REG ===================================================== */
4116 #define PDC_PDC_CTRL7_REG_PDC_MASTER_Pos (11UL)
4117 #define PDC_PDC_CTRL7_REG_PDC_MASTER_Msk (0x1800UL)
4118 #define PDC_PDC_CTRL7_REG_EN_COM_Pos (10UL)
4119 #define PDC_PDC_CTRL7_REG_EN_COM_Msk (0x400UL)
4120 #define PDC_PDC_CTRL7_REG_EN_PER_Pos (9UL)
4121 #define PDC_PDC_CTRL7_REG_EN_PER_Msk (0x200UL)
4122 #define PDC_PDC_CTRL7_REG_EN_TMR_Pos (8UL)
4123 #define PDC_PDC_CTRL7_REG_EN_TMR_Msk (0x100UL)
4124 #define PDC_PDC_CTRL7_REG_EN_XTAL_Pos (7UL)
4125 #define PDC_PDC_CTRL7_REG_EN_XTAL_Msk (0x80UL)
4126 #define PDC_PDC_CTRL7_REG_TRIG_ID_Pos (2UL)
4127 #define PDC_PDC_CTRL7_REG_TRIG_ID_Msk (0x7cUL)
4128 #define PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos (0UL)
4129 #define PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk (0x3UL)
4130 /* ===================================================== PDC_CTRL8_REG ===================================================== */
4131 #define PDC_PDC_CTRL8_REG_PDC_MASTER_Pos (11UL)
4132 #define PDC_PDC_CTRL8_REG_PDC_MASTER_Msk (0x1800UL)
4133 #define PDC_PDC_CTRL8_REG_EN_COM_Pos (10UL)
4134 #define PDC_PDC_CTRL8_REG_EN_COM_Msk (0x400UL)
4135 #define PDC_PDC_CTRL8_REG_EN_PER_Pos (9UL)
4136 #define PDC_PDC_CTRL8_REG_EN_PER_Msk (0x200UL)
4137 #define PDC_PDC_CTRL8_REG_EN_TMR_Pos (8UL)
4138 #define PDC_PDC_CTRL8_REG_EN_TMR_Msk (0x100UL)
4139 #define PDC_PDC_CTRL8_REG_EN_XTAL_Pos (7UL)
4140 #define PDC_PDC_CTRL8_REG_EN_XTAL_Msk (0x80UL)
4141 #define PDC_PDC_CTRL8_REG_TRIG_ID_Pos (2UL)
4142 #define PDC_PDC_CTRL8_REG_TRIG_ID_Msk (0x7cUL)
4143 #define PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos (0UL)
4144 #define PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk (0x3UL)
4145 /* ===================================================== PDC_CTRL9_REG ===================================================== */
4146 #define PDC_PDC_CTRL9_REG_PDC_MASTER_Pos (11UL)
4147 #define PDC_PDC_CTRL9_REG_PDC_MASTER_Msk (0x1800UL)
4148 #define PDC_PDC_CTRL9_REG_EN_COM_Pos (10UL)
4149 #define PDC_PDC_CTRL9_REG_EN_COM_Msk (0x400UL)
4150 #define PDC_PDC_CTRL9_REG_EN_PER_Pos (9UL)
4151 #define PDC_PDC_CTRL9_REG_EN_PER_Msk (0x200UL)
4152 #define PDC_PDC_CTRL9_REG_EN_TMR_Pos (8UL)
4153 #define PDC_PDC_CTRL9_REG_EN_TMR_Msk (0x100UL)
4154 #define PDC_PDC_CTRL9_REG_EN_XTAL_Pos (7UL)
4155 #define PDC_PDC_CTRL9_REG_EN_XTAL_Msk (0x80UL)
4156 #define PDC_PDC_CTRL9_REG_TRIG_ID_Pos (2UL)
4157 #define PDC_PDC_CTRL9_REG_TRIG_ID_Msk (0x7cUL)
4158 #define PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos (0UL)
4159 #define PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk (0x3UL)
4160 /* ================================================= PDC_PENDING_CM33_REG ================================================== */
4161 #define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos (0UL)
4162 #define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk (0xfffUL)
4163 /* ================================================= PDC_PENDING_CMAC_REG ================================================== */
4164 #define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos (0UL)
4165 #define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk (0xfffUL)
4166 /* ==================================================== PDC_PENDING_REG ==================================================== */
4167 #define PDC_PDC_PENDING_REG_PDC_PENDING_Pos (0UL)
4168 #define PDC_PDC_PENDING_REG_PDC_PENDING_Msk (0xfffUL)
4169 /* ================================================== PDC_SET_PENDING_REG ================================================== */
4170 #define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos (0UL)
4171 #define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk (0x1fUL)
4174 /* =========================================================================================================================== */
4175 /* ================ QSPIC ================ */
4176 /* =========================================================================================================================== */
4177 
4178 /* ================================================== QSPIC_AWRITECMD_REG ================================================== */
4179 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL)
4180 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL)
4181 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL)
4182 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL)
4183 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL)
4184 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL)
4185 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL)
4186 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL)
4187 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL)
4188 #define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL)
4189 /* ================================================== QSPIC_BURSTBRK_REG =================================================== */
4190 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL)
4191 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL)
4192 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL)
4193 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL)
4194 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL)
4195 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL)
4196 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL)
4197 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL)
4198 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL)
4199 #define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL)
4200 /* ================================================== QSPIC_BURSTCMDA_REG ================================================== */
4201 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL)
4202 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL)
4203 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL)
4204 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL)
4205 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL)
4206 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL)
4207 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL)
4208 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL)
4209 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL)
4210 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL)
4211 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL)
4212 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL)
4213 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL)
4214 #define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL)
4215 /* ================================================== QSPIC_BURSTCMDB_REG ================================================== */
4216 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL)
4217 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL)
4218 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL)
4219 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL)
4220 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL)
4221 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL)
4222 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL)
4223 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL)
4224 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL)
4225 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL)
4226 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL)
4227 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL)
4228 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL)
4229 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL)
4230 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL)
4231 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL)
4232 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL)
4233 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL)
4234 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL)
4235 #define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL)
4236 /* ================================================== QSPIC_CHCKERASE_REG ================================================== */
4237 #define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL)
4238 #define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL)
4239 /* =================================================== QSPIC_CTRLBUS_REG =================================================== */
4240 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL)
4241 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL)
4242 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL)
4243 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL)
4244 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL)
4245 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL)
4246 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL)
4247 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL)
4248 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL)
4249 #define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL)
4250 /* ================================================== QSPIC_CTRLMODE_REG =================================================== */
4251 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL)
4252 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL)
4253 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL)
4254 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL)
4255 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL)
4256 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL)
4257 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL)
4258 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL)
4259 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL)
4260 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL)
4261 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL)
4262 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL)
4263 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL)
4264 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL)
4265 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL)
4266 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL)
4267 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL)
4268 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL)
4269 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL)
4270 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL)
4271 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL)
4272 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL)
4273 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL)
4274 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL)
4275 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL)
4276 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL)
4277 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL)
4278 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL)
4279 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL)
4280 #define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL)
4281 /* ================================================== QSPIC_DUMMYDATA_REG ================================================== */
4282 #define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL)
4283 #define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL)
4284 /* ================================================== QSPIC_ERASECMDA_REG ================================================== */
4285 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL)
4286 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL)
4287 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL)
4288 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL)
4289 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL)
4290 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL)
4291 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL)
4292 #define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL)
4293 /* ================================================== QSPIC_ERASECMDB_REG ================================================== */
4294 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL)
4295 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL)
4296 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL)
4297 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL)
4298 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL)
4299 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL)
4300 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL)
4301 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL)
4302 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL)
4303 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL)
4304 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL)
4305 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL)
4306 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL)
4307 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL)
4308 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL)
4309 #define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL)
4310 /* ================================================== QSPIC_ERASECTRL_REG ================================================== */
4311 #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL)
4312 #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL)
4313 #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL)
4314 #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL)
4315 #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL)
4316 #define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL)
4317 /* ===================================================== QSPIC_GP_REG ====================================================== */
4318 #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL)
4319 #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL)
4320 #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL)
4321 #define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL)
4322 /* =================================================== QSPIC_MEMBLEN_REG =================================================== */
4323 #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL)
4324 #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL)
4325 #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL)
4326 #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL)
4327 #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL)
4328 #define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL)
4329 /* ================================================== QSPIC_READDATA_REG =================================================== */
4330 #define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL)
4331 #define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL)
4332 /* ================================================== QSPIC_RECVDATA_REG =================================================== */
4333 #define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL)
4334 #define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL)
4335 /* ================================================== QSPIC_STATUSCMD_REG ================================================== */
4336 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL)
4337 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL)
4338 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL)
4339 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL)
4340 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL)
4341 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL)
4342 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL)
4343 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL)
4344 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL)
4345 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL)
4346 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL)
4347 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL)
4348 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL)
4349 #define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL)
4350 /* =================================================== QSPIC_STATUS_REG ==================================================== */
4351 #define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL)
4352 #define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL)
4353 /* ================================================== QSPIC_WRITEDATA_REG ================================================== */
4354 #define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL)
4355 #define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL)
4358 /* =========================================================================================================================== */
4359 /* ================ QUADEC ================ */
4360 /* =========================================================================================================================== */
4361 
4362 /* =================================================== QDEC_CLOCKDIV_REG =================================================== */
4363 #define QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Pos (10UL)
4364 #define QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Msk (0x400UL)
4365 #define QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Pos (0UL)
4366 #define QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Msk (0x3ffUL)
4367 /* ==================================================== QDEC_CTRL2_REG ===================================================== */
4368 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Pos (14UL)
4369 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Msk (0x4000UL)
4370 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Pos (13UL)
4371 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Msk (0x2000UL)
4372 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Pos (12UL)
4373 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Msk (0x1000UL)
4374 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Pos (8UL)
4375 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Msk (0xf00UL)
4376 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Pos (4UL)
4377 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Msk (0xf0UL)
4378 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Pos (0UL)
4379 #define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Msk (0xfUL)
4380 /* ===================================================== QDEC_CTRL_REG ===================================================== */
4381 #define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Pos (3UL)
4382 #define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Msk (0x7f8UL)
4383 #define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Pos (2UL)
4384 #define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Msk (0x4UL)
4385 #define QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Pos (1UL)
4386 #define QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Msk (0x2UL)
4387 #define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Pos (0UL)
4388 #define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Msk (0x1UL)
4389 /* ================================================== QDEC_EVENT_CNT_REG =================================================== */
4390 #define QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Pos (0UL)
4391 #define QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Msk (0xffUL)
4392 /* ===================================================== QDEC_XCNT_REG ===================================================== */
4393 #define QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Pos (0UL)
4394 #define QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Msk (0xffffUL)
4395 /* ===================================================== QDEC_YCNT_REG ===================================================== */
4396 #define QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Pos (0UL)
4397 #define QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Msk (0xffffUL)
4398 /* ===================================================== QDEC_ZCNT_REG ===================================================== */
4399 #define QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Pos (0UL)
4400 #define QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Msk (0xffffUL)
4403 /* =========================================================================================================================== */
4404 /* ================ RTC ================ */
4405 /* =========================================================================================================================== */
4406 
4407 /* ================================================= RTC_ALARM_ENABLE_REG ================================================== */
4408 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos (5UL)
4409 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk (0x20UL)
4410 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos (4UL)
4411 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk (0x10UL)
4412 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos (3UL)
4413 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk (0x8UL)
4414 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos (2UL)
4415 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk (0x4UL)
4416 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos (1UL)
4417 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk (0x2UL)
4418 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos (0UL)
4419 #define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk (0x1UL)
4420 /* ================================================ RTC_CALENDAR_ALARM_REG ================================================= */
4421 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos (12UL)
4422 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk (0x3000UL)
4423 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos (8UL)
4424 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk (0xf00UL)
4425 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos (7UL)
4426 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk (0x80UL)
4427 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos (3UL)
4428 #define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk (0x78UL)
4429 /* =================================================== RTC_CALENDAR_REG ==================================================== */
4430 #define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos (31UL)
4431 #define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk (0x80000000UL)
4432 #define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos (28UL)
4433 #define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk (0x30000000UL)
4434 #define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos (24UL)
4435 #define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk (0xf000000UL)
4436 #define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos (20UL)
4437 #define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk (0xf00000UL)
4438 #define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos (16UL)
4439 #define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk (0xf0000UL)
4440 #define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos (12UL)
4441 #define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk (0x3000UL)
4442 #define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos (8UL)
4443 #define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk (0xf00UL)
4444 #define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos (7UL)
4445 #define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk (0x80UL)
4446 #define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos (3UL)
4447 #define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk (0x78UL)
4448 #define RTC_RTC_CALENDAR_REG_RTC_DAY_Pos (0UL)
4449 #define RTC_RTC_CALENDAR_REG_RTC_DAY_Msk (0x7UL)
4450 /* ==================================================== RTC_CONTROL_REG ==================================================== */
4451 #define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos (1UL)
4452 #define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk (0x2UL)
4453 #define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos (0UL)
4454 #define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk (0x1UL)
4455 /* ================================================== RTC_EVENT_CTRL_REG =================================================== */
4456 #define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos (1UL)
4457 #define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk (0x2UL)
4458 /* ================================================== RTC_EVENT_FLAGS_REG ================================================== */
4459 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos (6UL)
4460 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk (0x40UL)
4461 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos (5UL)
4462 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk (0x20UL)
4463 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos (4UL)
4464 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk (0x10UL)
4465 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos (3UL)
4466 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk (0x8UL)
4467 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos (2UL)
4468 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk (0x4UL)
4469 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos (1UL)
4470 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk (0x2UL)
4471 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos (0UL)
4472 #define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk (0x1UL)
4473 /* =================================================== RTC_HOUR_MODE_REG =================================================== */
4474 #define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos (0UL)
4475 #define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk (0x1UL)
4476 /* =============================================== RTC_INTERRUPT_DISABLE_REG =============================================== */
4477 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos (6UL)
4478 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk (0x40UL)
4479 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos (5UL)
4480 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk (0x20UL)
4481 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos (4UL)
4482 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk (0x10UL)
4483 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos (3UL)
4484 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk (0x8UL)
4485 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos (2UL)
4486 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk (0x4UL)
4487 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos (1UL)
4488 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk (0x2UL)
4489 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos (0UL)
4490 #define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk (0x1UL)
4491 /* =============================================== RTC_INTERRUPT_ENABLE_REG ================================================ */
4492 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos (6UL)
4493 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk (0x40UL)
4494 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos (5UL)
4495 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk (0x20UL)
4496 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos (4UL)
4497 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk (0x10UL)
4498 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos (3UL)
4499 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk (0x8UL)
4500 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos (2UL)
4501 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk (0x4UL)
4502 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos (1UL)
4503 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk (0x2UL)
4504 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos (0UL)
4505 #define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk (0x1UL)
4506 /* ================================================ RTC_INTERRUPT_MASK_REG ================================================= */
4507 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos (6UL)
4508 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk (0x40UL)
4509 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos (5UL)
4510 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk (0x20UL)
4511 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos (4UL)
4512 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk (0x10UL)
4513 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos (3UL)
4514 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk (0x8UL)
4515 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos (2UL)
4516 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk (0x4UL)
4517 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos (1UL)
4518 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk (0x2UL)
4519 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos (0UL)
4520 #define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk (0x1UL)
4521 /* =================================================== RTC_KEEP_RTC_REG ==================================================== */
4522 #define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos (0UL)
4523 #define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk (0x1UL)
4524 /* ================================================ RTC_PDC_EVENT_CLEAR_REG ================================================ */
4525 #define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos (0UL)
4526 #define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk (0x1UL)
4527 /* ================================================= RTC_PDC_EVENT_CNT_REG ================================================= */
4528 #define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos (0UL)
4529 #define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk (0x1fffUL)
4530 /* =============================================== RTC_PDC_EVENT_PERIOD_REG ================================================ */
4531 #define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos (0UL)
4532 #define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk (0x1fffUL)
4533 /* ==================================================== RTC_STATUS_REG ===================================================== */
4534 #define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos (3UL)
4535 #define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk (0x8UL)
4536 #define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos (2UL)
4537 #define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk (0x4UL)
4538 #define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos (1UL)
4539 #define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk (0x2UL)
4540 #define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos (0UL)
4541 #define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk (0x1UL)
4542 /* ================================================== RTC_TIME_ALARM_REG =================================================== */
4543 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos (30UL)
4544 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk (0x40000000UL)
4545 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos (28UL)
4546 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk (0x30000000UL)
4547 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos (24UL)
4548 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk (0xf000000UL)
4549 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos (20UL)
4550 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk (0x700000UL)
4551 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos (16UL)
4552 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk (0xf0000UL)
4553 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos (12UL)
4554 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk (0x7000UL)
4555 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos (8UL)
4556 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk (0xf00UL)
4557 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos (4UL)
4558 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk (0xf0UL)
4559 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos (0UL)
4560 #define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk (0xfUL)
4561 /* ===================================================== RTC_TIME_REG ====================================================== */
4562 #define RTC_RTC_TIME_REG_RTC_TIME_CH_Pos (31UL)
4563 #define RTC_RTC_TIME_REG_RTC_TIME_CH_Msk (0x80000000UL)
4564 #define RTC_RTC_TIME_REG_RTC_TIME_PM_Pos (30UL)
4565 #define RTC_RTC_TIME_REG_RTC_TIME_PM_Msk (0x40000000UL)
4566 #define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos (28UL)
4567 #define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk (0x30000000UL)
4568 #define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos (24UL)
4569 #define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk (0xf000000UL)
4570 #define RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos (20UL)
4571 #define RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk (0x700000UL)
4572 #define RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos (16UL)
4573 #define RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk (0xf0000UL)
4574 #define RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos (12UL)
4575 #define RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk (0x7000UL)
4576 #define RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos (8UL)
4577 #define RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk (0xf00UL)
4578 #define RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos (4UL)
4579 #define RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk (0xf0UL)
4580 #define RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos (0UL)
4581 #define RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk (0xfUL)
4584 /* =========================================================================================================================== */
4585 /* ================ SDADC ================ */
4586 /* =========================================================================================================================== */
4587 
4588 /* ================================================= SDADC_AUDIO_FILT_REG ================================================== */
4589 #define SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Pos (0UL)
4590 #define SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Msk (0x1fffffUL)
4591 /* ================================================== SDADC_CLEAR_INT_REG ================================================== */
4592 #define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos (0UL)
4593 #define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk (0xffffffffUL)
4594 /* ==================================================== SDADC_CTRL_REG ===================================================== */
4595 #define SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Pos (20UL)
4596 #define SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Msk (0x100000UL)
4597 #define SDADC_SDADC_CTRL_REG_SDADC_MODE_Pos (19UL)
4598 #define SDADC_SDADC_CTRL_REG_SDADC_MODE_Msk (0x80000UL)
4599 #define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos (18UL)
4600 #define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk (0x40000UL)
4601 #define SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos (17UL)
4602 #define SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk (0x20000UL)
4603 #define SDADC_SDADC_CTRL_REG_SDADC_INT_Pos (16UL)
4604 #define SDADC_SDADC_CTRL_REG_SDADC_INT_Msk (0x10000UL)
4605 #define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos (15UL)
4606 #define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk (0x8000UL)
4607 #define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos (13UL)
4608 #define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk (0x6000UL)
4609 #define SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos (12UL)
4610 #define SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk (0x1000UL)
4611 #define SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos (10UL)
4612 #define SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk (0xc00UL)
4613 #define SDADC_SDADC_CTRL_REG_SDADC_SE_Pos (9UL)
4614 #define SDADC_SDADC_CTRL_REG_SDADC_SE_Msk (0x200UL)
4615 #define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos (6UL)
4616 #define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk (0x1c0UL)
4617 #define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos (2UL)
4618 #define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk (0x3cUL)
4619 #define SDADC_SDADC_CTRL_REG_SDADC_START_Pos (1UL)
4620 #define SDADC_SDADC_CTRL_REG_SDADC_START_Msk (0x2UL)
4621 #define SDADC_SDADC_CTRL_REG_SDADC_EN_Pos (0UL)
4622 #define SDADC_SDADC_CTRL_REG_SDADC_EN_Msk (0x1UL)
4623 /* ================================================== SDADC_GAIN_CORR_REG ================================================== */
4624 #define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos (0UL)
4625 #define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk (0x3ffUL)
4626 /* ================================================== SDADC_OFFS_CORR_REG ================================================== */
4627 #define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos (0UL)
4628 #define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk (0x3ffUL)
4629 /* ================================================== SDADC_PGA_CTRL_REG =================================================== */
4630 #define SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Pos (9UL)
4631 #define SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Msk (0xe00UL)
4632 #define SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Pos (7UL)
4633 #define SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Msk (0x180UL)
4634 #define SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Pos (6UL)
4635 #define SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Msk (0x40UL)
4636 #define SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Pos (3UL)
4637 #define SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Msk (0x38UL)
4638 #define SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Pos (2UL)
4639 #define SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Msk (0x4UL)
4640 #define SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Pos (0UL)
4641 #define SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Msk (0x3UL)
4642 /* =================================================== SDADC_RESULT_REG ==================================================== */
4643 #define SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos (0UL)
4644 #define SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk (0xffffUL)
4647 /* =========================================================================================================================== */
4648 /* ================ SPI ================ */
4649 /* =========================================================================================================================== */
4650 
4651 /* ===================================================== SPI_CLOCK_REG ===================================================== */
4652 #define SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Pos (0UL)
4653 #define SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Msk (0x7fUL)
4654 /* ==================================================== SPI_CONFIG_REG ===================================================== */
4655 #define SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Pos (7UL)
4656 #define SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Msk (0x80UL)
4657 #define SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Pos (2UL)
4658 #define SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Msk (0x7cUL)
4659 #define SPI_SPI_CONFIG_REG_SPI_MODE_Pos (0UL)
4660 #define SPI_SPI_CONFIG_REG_SPI_MODE_Msk (0x3UL)
4661 /* =================================================== SPI_CS_CONFIG_REG =================================================== */
4662 #define SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Pos (0UL)
4663 #define SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Msk (0x7UL)
4664 /* ===================================================== SPI_CTRL_REG ====================================================== */
4665 #define SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Pos (7UL)
4666 #define SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Msk (0x80UL)
4667 #define SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos (6UL)
4668 #define SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Msk (0x40UL)
4669 #define SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Pos (5UL)
4670 #define SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Msk (0x20UL)
4671 #define SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Pos (4UL)
4672 #define SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Msk (0x10UL)
4673 #define SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Pos (3UL)
4674 #define SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Msk (0x8UL)
4675 #define SPI_SPI_CTRL_REG_SPI_RX_EN_Pos (2UL)
4676 #define SPI_SPI_CTRL_REG_SPI_RX_EN_Msk (0x4UL)
4677 #define SPI_SPI_CTRL_REG_SPI_TX_EN_Pos (1UL)
4678 #define SPI_SPI_CTRL_REG_SPI_TX_EN_Msk (0x2UL)
4679 #define SPI_SPI_CTRL_REG_SPI_EN_Pos (0UL)
4680 #define SPI_SPI_CTRL_REG_SPI_EN_Msk (0x1UL)
4681 /* ================================================== SPI_FIFO_CONFIG_REG ================================================== */
4682 #define SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Pos (4UL)
4683 #define SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Msk (0xf0UL)
4684 #define SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Pos (0UL)
4685 #define SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Msk (0xfUL)
4686 /* =================================================== SPI_FIFO_READ_REG =================================================== */
4687 #define SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Pos (0UL)
4688 #define SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Msk (0xffffffffUL)
4689 /* ================================================== SPI_FIFO_STATUS_REG ================================================== */
4690 #define SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Pos (15UL)
4691 #define SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Msk (0x8000UL)
4692 #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Pos (14UL)
4693 #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Msk (0x4000UL)
4694 #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Pos (13UL)
4695 #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Msk (0x2000UL)
4696 #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Pos (12UL)
4697 #define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Msk (0x1000UL)
4698 #define SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Pos (6UL)
4699 #define SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Msk (0xfc0UL)
4700 #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Pos (0UL)
4701 #define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Msk (0x3fUL)
4702 /* ================================================== SPI_FIFO_WRITE_REG =================================================== */
4703 #define SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Pos (0UL)
4704 #define SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Msk (0xffffffffUL)
4705 /* =================================================== SPI_IRQ_MASK_REG ==================================================== */
4706 #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Pos (1UL)
4707 #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk (0x2UL)
4708 #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Pos (0UL)
4709 #define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk (0x1UL)
4710 /* ==================================================== SPI_STATUS_REG ===================================================== */
4711 #define SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Pos (1UL)
4712 #define SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Msk (0x2UL)
4713 #define SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Pos (0UL)
4714 #define SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk (0x1UL)
4715 /* ================================================ SPI_TXBUFFER_FORCE_REG ================================================= */
4716 #define SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Pos (0UL)
4717 #define SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Msk (0xffffffffUL)
4720 /* =========================================================================================================================== */
4721 /* ================ SRC1 ================ */
4722 /* =========================================================================================================================== */
4723 
4724 /* ================================================= SRC1_COEF0A_SET1_REG ================================================== */
4725 #define SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)
4726 #define SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)
4727 /* ================================================= SRC1_COEF10_SET1_REG ================================================== */
4728 #define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)
4729 #define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)
4730 #define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)
4731 #define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)
4732 /* ================================================= SRC1_COEF32_SET1_REG ================================================== */
4733 #define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)
4734 #define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)
4735 #define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)
4736 #define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)
4737 /* ================================================= SRC1_COEF54_SET1_REG ================================================== */
4738 #define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)
4739 #define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)
4740 #define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)
4741 #define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)
4742 /* ================================================= SRC1_COEF76_SET1_REG ================================================== */
4743 #define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)
4744 #define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)
4745 #define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)
4746 #define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)
4747 /* ================================================= SRC1_COEF98_SET1_REG ================================================== */
4748 #define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)
4749 #define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)
4750 #define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)
4751 #define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)
4752 /* ===================================================== SRC1_CTRL_REG ===================================================== */
4753 #define SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL)
4754 #define SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL)
4755 #define SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL)
4756 #define SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)
4757 #define SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL)
4758 #define SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL)
4759 #define SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)
4760 #define SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)
4761 #define SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)
4762 #define SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)
4763 #define SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)
4764 #define SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)
4765 #define SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)
4766 #define SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)
4767 #define SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)
4768 #define SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)
4769 #define SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)
4770 #define SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)
4771 #define SRC1_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL)
4772 #define SRC1_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL)
4773 #define SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL)
4774 #define SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL)
4775 #define SRC1_SRC1_CTRL_REG_SRC_OUT_US_Pos (16UL)
4776 #define SRC1_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL)
4777 #define SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)
4778 #define SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)
4779 #define SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)
4780 #define SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)
4781 #define SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)
4782 #define SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)
4783 #define SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)
4784 #define SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)
4785 #define SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)
4786 #define SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)
4787 #define SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)
4788 #define SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)
4789 #define SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)
4790 #define SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)
4791 #define SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)
4792 #define SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)
4793 #define SRC1_SRC1_CTRL_REG_SRC_IN_OK_Pos (6UL)
4794 #define SRC1_SRC1_CTRL_REG_SRC_IN_OK_Msk (0x40UL)
4795 #define SRC1_SRC1_CTRL_REG_SRC_IN_DS_Pos (4UL)
4796 #define SRC1_SRC1_CTRL_REG_SRC_IN_DS_Msk (0x30UL)
4797 #define SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)
4798 #define SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)
4799 #define SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)
4800 #define SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)
4801 #define SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL)
4802 #define SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)
4803 #define SRC1_SRC1_CTRL_REG_SRC_EN_Pos (0UL)
4804 #define SRC1_SRC1_CTRL_REG_SRC_EN_Msk (0x1UL)
4805 /* ===================================================== SRC1_IN1_REG ====================================================== */
4806 #define SRC1_SRC1_IN1_REG_SRC_IN_Pos (0UL)
4807 #define SRC1_SRC1_IN1_REG_SRC_IN_Msk (0xffffffffUL)
4808 /* ===================================================== SRC1_IN2_REG ====================================================== */
4809 #define SRC1_SRC1_IN2_REG_SRC_IN_Pos (0UL)
4810 #define SRC1_SRC1_IN2_REG_SRC_IN_Msk (0xffffffffUL)
4811 /* ==================================================== SRC1_IN_FS_REG ===================================================== */
4812 #define SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL)
4813 #define SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL)
4814 /* ===================================================== SRC1_MUX_REG ====================================================== */
4815 #define SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Pos (6UL)
4816 #define SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Msk (0x40UL)
4817 #define SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Pos (3UL)
4818 #define SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Msk (0x38UL)
4819 #define SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Pos (0UL)
4820 #define SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Msk (0x7UL)
4821 /* ===================================================== SRC1_OUT1_REG ===================================================== */
4822 #define SRC1_SRC1_OUT1_REG_SRC_OUT_Pos (0UL)
4823 #define SRC1_SRC1_OUT1_REG_SRC_OUT_Msk (0xffffffffUL)
4824 /* ===================================================== SRC1_OUT2_REG ===================================================== */
4825 #define SRC1_SRC1_OUT2_REG_SRC_OUT_Pos (0UL)
4826 #define SRC1_SRC1_OUT2_REG_SRC_OUT_Msk (0xffffffffUL)
4827 /* ==================================================== SRC1_OUT_FS_REG ==================================================== */
4828 #define SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)
4829 #define SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)
4832 /* =========================================================================================================================== */
4833 /* ================ SRC2 ================ */
4834 /* =========================================================================================================================== */
4835 
4836 /* ================================================= SRC2_COEF0A_SET1_REG ================================================== */
4837 #define SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)
4838 #define SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)
4839 /* ================================================= SRC2_COEF10_SET1_REG ================================================== */
4840 #define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)
4841 #define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)
4842 #define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)
4843 #define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)
4844 /* ================================================= SRC2_COEF32_SET1_REG ================================================== */
4845 #define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)
4846 #define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)
4847 #define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)
4848 #define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)
4849 /* ================================================= SRC2_COEF54_SET1_REG ================================================== */
4850 #define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)
4851 #define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)
4852 #define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)
4853 #define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)
4854 /* ================================================= SRC2_COEF76_SET1_REG ================================================== */
4855 #define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)
4856 #define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)
4857 #define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)
4858 #define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)
4859 /* ================================================= SRC2_COEF98_SET1_REG ================================================== */
4860 #define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)
4861 #define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)
4862 #define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)
4863 #define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)
4864 /* ===================================================== SRC2_CTRL_REG ===================================================== */
4865 #define SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Pos (28UL)
4866 #define SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)
4867 #define SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)
4868 #define SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)
4869 #define SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)
4870 #define SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)
4871 #define SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)
4872 #define SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)
4873 #define SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)
4874 #define SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)
4875 #define SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)
4876 #define SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)
4877 #define SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)
4878 #define SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)
4879 #define SRC2_SRC2_CTRL_REG_SRC_RESYNC_Pos (19UL)
4880 #define SRC2_SRC2_CTRL_REG_SRC_RESYNC_Msk (0x80000UL)
4881 #define SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Pos (18UL)
4882 #define SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL)
4883 #define SRC2_SRC2_CTRL_REG_SRC_OUT_US_Pos (16UL)
4884 #define SRC2_SRC2_CTRL_REG_SRC_OUT_US_Msk (0x30000UL)
4885 #define SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)
4886 #define SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)
4887 #define SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)
4888 #define SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)
4889 #define SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)
4890 #define SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)
4891 #define SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)
4892 #define SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)
4893 #define SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)
4894 #define SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)
4895 #define SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)
4896 #define SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)
4897 #define SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)
4898 #define SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)
4899 #define SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)
4900 #define SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)
4901 #define SRC2_SRC2_CTRL_REG_SRC_IN_OK_Pos (6UL)
4902 #define SRC2_SRC2_CTRL_REG_SRC_IN_OK_Msk (0x40UL)
4903 #define SRC2_SRC2_CTRL_REG_SRC_IN_DS_Pos (4UL)
4904 #define SRC2_SRC2_CTRL_REG_SRC_IN_DS_Msk (0x30UL)
4905 #define SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)
4906 #define SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)
4907 #define SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)
4908 #define SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)
4909 #define SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Pos (1UL)
4910 #define SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)
4911 #define SRC2_SRC2_CTRL_REG_SRC_EN_Pos (0UL)
4912 #define SRC2_SRC2_CTRL_REG_SRC_EN_Msk (0x1UL)
4913 /* ===================================================== SRC2_IN1_REG ====================================================== */
4914 #define SRC2_SRC2_IN1_REG_SRC_IN_Pos (0UL)
4915 #define SRC2_SRC2_IN1_REG_SRC_IN_Msk (0xffffffffUL)
4916 /* ===================================================== SRC2_IN2_REG ====================================================== */
4917 #define SRC2_SRC2_IN2_REG_SRC_IN_Pos (0UL)
4918 #define SRC2_SRC2_IN2_REG_SRC_IN_Msk (0xffffffffUL)
4919 /* ==================================================== SRC2_IN_FS_REG ===================================================== */
4920 #define SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Pos (0UL)
4921 #define SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL)
4922 /* ===================================================== SRC2_MUX_REG ====================================================== */
4923 #define SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Pos (6UL)
4924 #define SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Msk (0x40UL)
4925 #define SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Pos (3UL)
4926 #define SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Msk (0x38UL)
4927 #define SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Pos (0UL)
4928 #define SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Msk (0x7UL)
4929 /* ===================================================== SRC2_OUT1_REG ===================================================== */
4930 #define SRC2_SRC2_OUT1_REG_SRC_OUT_Pos (0UL)
4931 #define SRC2_SRC2_OUT1_REG_SRC_OUT_Msk (0xffffffffUL)
4932 /* ===================================================== SRC2_OUT2_REG ===================================================== */
4933 #define SRC2_SRC2_OUT2_REG_SRC_OUT_Pos (0UL)
4934 #define SRC2_SRC2_OUT2_REG_SRC_OUT_Msk (0xffffffffUL)
4935 /* ==================================================== SRC2_OUT_FS_REG ==================================================== */
4936 #define SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)
4937 #define SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)
4940 /* =========================================================================================================================== */
4941 /* ================ SYS_WDOG ================ */
4942 /* =========================================================================================================================== */
4943 
4944 /* =================================================== WATCHDOG_CTRL_REG =================================================== */
4945 #define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL)
4946 #define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL)
4947 #define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL)
4948 #define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL)
4949 #define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL)
4950 #define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL)
4951 /* ===================================================== WATCHDOG_REG ====================================================== */
4952 #define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL)
4953 #define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL)
4954 #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL)
4955 #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL)
4956 #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL)
4957 #define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL)
4960 /* =========================================================================================================================== */
4961 /* ================ SYSB ================ */
4962 /* =========================================================================================================================== */
4963 
4964 /* ====================================================== BRIDGE_REG ======================================================= */
4965 #define SYSB_BRIDGE_REG_SYNC_BYPASS_Pos (1UL)
4966 #define SYSB_BRIDGE_REG_SYNC_BYPASS_Msk (0x2UL)
4967 #define SYSB_BRIDGE_REG_BRIDGE_BYPASS_Pos (0UL)
4968 #define SYSB_BRIDGE_REG_BRIDGE_BYPASS_Msk (0x1UL)
4969 /* ===================================================== FLASH_ARB_REG ===================================================== */
4970 #define SYSB_FLASH_ARB_REG_ENABLE_SEQ_Pos (0UL)
4971 #define SYSB_FLASH_ARB_REG_ENABLE_SEQ_Msk (0x1UL)
4972 /* ===================================================== QSPI_ARB_REG ====================================================== */
4973 #define SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Pos (6UL)
4974 #define SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Msk (0xc0UL)
4975 #define SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Pos (4UL)
4976 #define SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Msk (0x30UL)
4977 #define SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Pos (2UL)
4978 #define SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Msk (0xcUL)
4979 #define SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Pos (0UL)
4980 #define SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Msk (0x3UL)
4983 /* =========================================================================================================================== */
4984 /* ================ TIMER ================ */
4985 /* =========================================================================================================================== */
4986 
4987 /* ================================================ TIMER_CAPTURE_GPIO1_REG ================================================ */
4988 #define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)
4989 #define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)
4990 /* ================================================ TIMER_CAPTURE_GPIO2_REG ================================================ */
4991 #define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)
4992 #define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)
4993 /* ================================================ TIMER_CAPTURE_GPIO3_REG ================================================ */
4994 #define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos (0UL)
4995 #define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk (0xffffffUL)
4996 /* ================================================ TIMER_CAPTURE_GPIO4_REG ================================================ */
4997 #define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos (0UL)
4998 #define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk (0xffffffUL)
4999 /* ============================================== TIMER_CLEAR_GPIO_EVENT_REG =============================================== */
5000 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL)
5001 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL)
5002 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL)
5003 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL)
5004 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL)
5005 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL)
5006 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL)
5007 #define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL)
5008 /* ================================================== TIMER_CLEAR_IRQ_REG ================================================== */
5009 #define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)
5010 #define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)
5011 /* ==================================================== TIMER_CTRL_REG ===================================================== */
5012 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL)
5013 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL)
5014 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL)
5015 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL)
5016 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL)
5017 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL)
5018 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL)
5019 #define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL)
5020 #define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL)
5021 #define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL)
5022 #define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL)
5023 #define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL)
5024 #define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL)
5025 #define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)
5026 #define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)
5027 #define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)
5028 #define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)
5029 #define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)
5030 #define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL)
5031 #define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)
5032 #define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)
5033 #define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)
5034 #define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)
5035 #define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)
5036 #define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)
5037 #define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)
5038 #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)
5039 #define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)
5040 #define TIMER_TIMER_CTRL_REG_TIM_EN_Pos (0UL)
5041 #define TIMER_TIMER_CTRL_REG_TIM_EN_Msk (0x1UL)
5042 /* ================================================= TIMER_GPIO1_CONF_REG ================================================== */
5043 #define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)
5044 #define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)
5045 /* ================================================= TIMER_GPIO2_CONF_REG ================================================== */
5046 #define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)
5047 #define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)
5048 /* ================================================= TIMER_GPIO3_CONF_REG ================================================== */
5049 #define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL)
5050 #define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL)
5051 /* ================================================= TIMER_GPIO4_CONF_REG ================================================== */
5052 #define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL)
5053 #define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL)
5054 /* ================================================ TIMER_PRESCALER_VAL_REG ================================================ */
5055 #define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)
5056 #define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)
5057 /* ================================================== TIMER_PWM_CTRL_REG =================================================== */
5058 #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)
5059 #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)
5060 #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)
5061 #define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)
5062 /* ================================================== TIMER_SETTINGS_REG =================================================== */
5063 #define TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)
5064 #define TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)
5065 #define TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Pos (0UL)
5066 #define TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)
5067 /* ================================================== TIMER_SHOTWIDTH_REG ================================================== */
5068 #define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)
5069 #define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)
5070 /* =================================================== TIMER_STATUS_REG ==================================================== */
5071 #define TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Pos (13UL)
5072 #define TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Msk (0x2000UL)
5073 #define TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Pos (12UL)
5074 #define TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Msk (0x1000UL)
5075 #define TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)
5076 #define TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)
5077 #define TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)
5078 #define TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)
5079 #define TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)
5080 #define TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)
5081 #define TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)
5082 #define TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)
5083 #define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL)
5084 #define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL)
5085 #define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL)
5086 #define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL)
5087 #define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL)
5088 #define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL)
5089 #define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL)
5090 #define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL)
5091 #define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)
5092 #define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)
5093 #define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL)
5094 #define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)
5095 #define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL)
5096 #define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)
5097 /* ================================================== TIMER_TIMER_VAL_REG ================================================== */
5098 #define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)
5099 #define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)
5102 /* =========================================================================================================================== */
5103 /* ================ TIMER2 ================ */
5104 /* =========================================================================================================================== */
5105 
5106 /* =============================================== TIMER2_CAPTURE_GPIO1_REG ================================================ */
5107 #define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)
5108 #define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)
5109 /* =============================================== TIMER2_CAPTURE_GPIO2_REG ================================================ */
5110 #define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)
5111 #define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)
5112 /* ================================================= TIMER2_CLEAR_IRQ_REG ================================================== */
5113 #define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)
5114 #define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)
5115 /* ==================================================== TIMER2_CTRL_REG ==================================================== */
5116 #define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL)
5117 #define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)
5118 #define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)
5119 #define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)
5120 #define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)
5121 #define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)
5122 #define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL)
5123 #define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)
5124 #define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)
5125 #define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)
5126 #define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)
5127 #define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)
5128 #define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)
5129 #define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)
5130 #define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)
5131 #define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)
5132 #define TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL)
5133 #define TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL)
5134 /* ================================================= TIMER2_GPIO1_CONF_REG ================================================= */
5135 #define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)
5136 #define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)
5137 /* ================================================= TIMER2_GPIO2_CONF_REG ================================================= */
5138 #define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)
5139 #define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)
5140 /* =============================================== TIMER2_PRESCALER_VAL_REG ================================================ */
5141 #define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)
5142 #define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)
5143 /* ================================================== TIMER2_PWM_CTRL_REG ================================================== */
5144 #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)
5145 #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)
5146 #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)
5147 #define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)
5148 /* ================================================== TIMER2_SETTINGS_REG ================================================== */
5149 #define TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)
5150 #define TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)
5151 #define TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Pos (0UL)
5152 #define TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)
5153 /* ================================================= TIMER2_SHOTWIDTH_REG ================================================== */
5154 #define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)
5155 #define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)
5156 /* =================================================== TIMER2_STATUS_REG =================================================== */
5157 #define TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)
5158 #define TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)
5159 #define TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)
5160 #define TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)
5161 #define TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)
5162 #define TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)
5163 #define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)
5164 #define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)
5165 #define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)
5166 #define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)
5167 #define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL)
5168 #define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)
5169 #define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL)
5170 #define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)
5171 /* ================================================= TIMER2_TIMER_VAL_REG ================================================== */
5172 #define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)
5173 #define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)
5176 /* =========================================================================================================================== */
5177 /* ================ TIMER3 ================ */
5178 /* =========================================================================================================================== */
5179 
5180 /* =============================================== TIMER3_CAPTURE_GPIO1_REG ================================================ */
5181 #define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)
5182 #define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)
5183 /* =============================================== TIMER3_CAPTURE_GPIO2_REG ================================================ */
5184 #define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)
5185 #define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)
5186 /* ================================================= TIMER3_CLEAR_IRQ_REG ================================================== */
5187 #define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)
5188 #define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)
5189 /* ==================================================== TIMER3_CTRL_REG ==================================================== */
5190 #define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL)
5191 #define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)
5192 #define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)
5193 #define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)
5194 #define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)
5195 #define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)
5196 #define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL)
5197 #define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)
5198 #define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)
5199 #define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)
5200 #define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)
5201 #define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)
5202 #define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)
5203 #define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)
5204 #define TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL)
5205 #define TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL)
5206 /* ================================================= TIMER3_GPIO1_CONF_REG ================================================= */
5207 #define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)
5208 #define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)
5209 /* ================================================= TIMER3_GPIO2_CONF_REG ================================================= */
5210 #define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)
5211 #define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)
5212 /* =============================================== TIMER3_PRESCALER_VAL_REG ================================================ */
5213 #define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)
5214 #define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)
5215 /* ================================================== TIMER3_PWM_CTRL_REG ================================================== */
5216 #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)
5217 #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)
5218 #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)
5219 #define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)
5220 /* ================================================== TIMER3_SETTINGS_REG ================================================== */
5221 #define TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)
5222 #define TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)
5223 #define TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Pos (0UL)
5224 #define TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)
5225 /* =================================================== TIMER3_STATUS_REG =================================================== */
5226 #define TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)
5227 #define TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)
5228 #define TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)
5229 #define TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)
5230 #define TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)
5231 #define TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)
5232 #define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)
5233 #define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)
5234 #define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)
5235 #define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)
5236 #define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL)
5237 #define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)
5238 #define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL)
5239 #define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)
5240 /* ================================================= TIMER3_TIMER_VAL_REG ================================================== */
5241 #define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)
5242 #define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)
5245 /* =========================================================================================================================== */
5246 /* ================ TIMER4 ================ */
5247 /* =========================================================================================================================== */
5248 
5249 /* =============================================== TIMER4_CAPTURE_GPIO1_REG ================================================ */
5250 #define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)
5251 #define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)
5252 /* =============================================== TIMER4_CAPTURE_GPIO2_REG ================================================ */
5253 #define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)
5254 #define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)
5255 /* ================================================= TIMER4_CLEAR_IRQ_REG ================================================== */
5256 #define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)
5257 #define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)
5258 /* ==================================================== TIMER4_CTRL_REG ==================================================== */
5259 #define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL)
5260 #define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)
5261 #define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)
5262 #define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)
5263 #define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)
5264 #define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)
5265 #define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL)
5266 #define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)
5267 #define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)
5268 #define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)
5269 #define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)
5270 #define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)
5271 #define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)
5272 #define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)
5273 #define TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL)
5274 #define TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL)
5275 /* ================================================= TIMER4_GPIO1_CONF_REG ================================================= */
5276 #define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)
5277 #define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)
5278 /* ================================================= TIMER4_GPIO2_CONF_REG ================================================= */
5279 #define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)
5280 #define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)
5281 /* =============================================== TIMER4_PRESCALER_VAL_REG ================================================ */
5282 #define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)
5283 #define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)
5284 /* ================================================== TIMER4_PWM_CTRL_REG ================================================== */
5285 #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)
5286 #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)
5287 #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)
5288 #define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)
5289 /* ================================================== TIMER4_SETTINGS_REG ================================================== */
5290 #define TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)
5291 #define TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)
5292 #define TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Pos (0UL)
5293 #define TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)
5294 /* =================================================== TIMER4_STATUS_REG =================================================== */
5295 #define TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)
5296 #define TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)
5297 #define TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)
5298 #define TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)
5299 #define TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)
5300 #define TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)
5301 #define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)
5302 #define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)
5303 #define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)
5304 #define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)
5305 #define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL)
5306 #define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)
5307 #define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL)
5308 #define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)
5309 /* ================================================= TIMER4_TIMER_VAL_REG ================================================== */
5310 #define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)
5311 #define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)
5314 /* =========================================================================================================================== */
5315 /* ================ UART ================ */
5316 /* =========================================================================================================================== */
5317 
5318 /* ===================================================== UART_CTR_REG ====================================================== */
5319 #define UART_UART_CTR_REG_UART_CTR_Pos (0UL)
5320 #define UART_UART_CTR_REG_UART_CTR_Msk (0xffffffffUL)
5321 /* ===================================================== UART_DLF_REG ====================================================== */
5322 #define UART_UART_DLF_REG_UART_DLF_Pos (0UL)
5323 #define UART_UART_DLF_REG_UART_DLF_Msk (0xfUL)
5324 /* ==================================================== UART_DMASA_REG ===================================================== */
5325 #define UART_UART_DMASA_REG_UART_DMASA_Pos (0UL)
5326 #define UART_UART_DMASA_REG_UART_DMASA_Msk (0x1UL)
5327 /* ===================================================== UART_HTX_REG ====================================================== */
5328 #define UART_UART_HTX_REG_UART_HALT_TX_Pos (0UL)
5329 #define UART_UART_HTX_REG_UART_HALT_TX_Msk (0x1UL)
5330 /* =================================================== UART_IER_DLH_REG ==================================================== */
5331 #define UART_UART_IER_DLH_REG_PTIME_DLH7_Pos (7UL)
5332 #define UART_UART_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)
5333 #define UART_UART_IER_DLH_REG_DLH6_5_Pos (5UL)
5334 #define UART_UART_IER_DLH_REG_DLH6_5_Msk (0x60UL)
5335 #define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)
5336 #define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)
5337 #define UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)
5338 #define UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)
5339 #define UART_UART_IER_DLH_REG_ELSI_DLH2_Pos (2UL)
5340 #define UART_UART_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)
5341 #define UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)
5342 #define UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)
5343 #define UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)
5344 #define UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)
5345 /* =================================================== UART_IIR_FCR_REG ==================================================== */
5346 #define UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL)
5347 #define UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)
5348 /* ===================================================== UART_LCR_REG ====================================================== */
5349 #define UART_UART_LCR_REG_UART_DLAB_Pos (7UL)
5350 #define UART_UART_LCR_REG_UART_DLAB_Msk (0x80UL)
5351 #define UART_UART_LCR_REG_UART_BC_Pos (6UL)
5352 #define UART_UART_LCR_REG_UART_BC_Msk (0x40UL)
5353 #define UART_UART_LCR_REG_UART_EPS_Pos (4UL)
5354 #define UART_UART_LCR_REG_UART_EPS_Msk (0x10UL)
5355 #define UART_UART_LCR_REG_UART_PEN_Pos (3UL)
5356 #define UART_UART_LCR_REG_UART_PEN_Msk (0x8UL)
5357 #define UART_UART_LCR_REG_UART_STOP_Pos (2UL)
5358 #define UART_UART_LCR_REG_UART_STOP_Msk (0x4UL)
5359 #define UART_UART_LCR_REG_UART_DLS_Pos (0UL)
5360 #define UART_UART_LCR_REG_UART_DLS_Msk (0x3UL)
5361 /* ===================================================== UART_LSR_REG ====================================================== */
5362 #define UART_UART_LSR_REG_UART_RFE_Pos (7UL)
5363 #define UART_UART_LSR_REG_UART_RFE_Msk (0x80UL)
5364 #define UART_UART_LSR_REG_UART_TEMT_Pos (6UL)
5365 #define UART_UART_LSR_REG_UART_TEMT_Msk (0x40UL)
5366 #define UART_UART_LSR_REG_UART_THRE_Pos (5UL)
5367 #define UART_UART_LSR_REG_UART_THRE_Msk (0x20UL)
5368 #define UART_UART_LSR_REG_UART_BI_Pos (4UL)
5369 #define UART_UART_LSR_REG_UART_BI_Msk (0x10UL)
5370 #define UART_UART_LSR_REG_UART_FE_Pos (3UL)
5371 #define UART_UART_LSR_REG_UART_FE_Msk (0x8UL)
5372 #define UART_UART_LSR_REG_UART_PE_Pos (2UL)
5373 #define UART_UART_LSR_REG_UART_PE_Msk (0x4UL)
5374 #define UART_UART_LSR_REG_UART_OE_Pos (1UL)
5375 #define UART_UART_LSR_REG_UART_OE_Msk (0x2UL)
5376 #define UART_UART_LSR_REG_UART_DR_Pos (0UL)
5377 #define UART_UART_LSR_REG_UART_DR_Msk (0x1UL)
5378 /* ===================================================== UART_MCR_REG ====================================================== */
5379 #define UART_UART_MCR_REG_UART_LB_Pos (4UL)
5380 #define UART_UART_MCR_REG_UART_LB_Msk (0x10UL)
5381 /* ================================================= UART_RBR_THR_DLL_REG ================================================== */
5382 #define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)
5383 #define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)
5384 /* ===================================================== UART_RFL_REG ====================================================== */
5385 #define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)
5386 #define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)
5387 /* ===================================================== UART_SBCR_REG ===================================================== */
5388 #define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)
5389 #define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)
5390 /* ===================================================== UART_SCR_REG ====================================================== */
5391 #define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)
5392 #define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)
5393 /* ==================================================== UART_SDMAM_REG ===================================================== */
5394 #define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)
5395 #define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)
5396 /* ===================================================== UART_SFE_REG ====================================================== */
5397 #define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)
5398 #define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)
5399 /* ================================================== UART_SRBR_STHR0_REG ================================================== */
5400 #define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)
5401 #define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)
5402 /* ================================================= UART_SRBR_STHR10_REG ================================================== */
5403 #define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)
5404 #define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)
5405 /* ================================================= UART_SRBR_STHR11_REG ================================================== */
5406 #define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)
5407 #define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)
5408 /* ================================================= UART_SRBR_STHR12_REG ================================================== */
5409 #define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)
5410 #define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)
5411 /* ================================================= UART_SRBR_STHR13_REG ================================================== */
5412 #define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)
5413 #define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)
5414 /* ================================================= UART_SRBR_STHR14_REG ================================================== */
5415 #define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)
5416 #define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)
5417 /* ================================================= UART_SRBR_STHR15_REG ================================================== */
5418 #define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)
5419 #define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)
5420 /* ================================================== UART_SRBR_STHR1_REG ================================================== */
5421 #define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)
5422 #define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)
5423 /* ================================================== UART_SRBR_STHR2_REG ================================================== */
5424 #define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)
5425 #define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)
5426 /* ================================================== UART_SRBR_STHR3_REG ================================================== */
5427 #define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)
5428 #define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)
5429 /* ================================================== UART_SRBR_STHR4_REG ================================================== */
5430 #define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)
5431 #define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)
5432 /* ================================================== UART_SRBR_STHR5_REG ================================================== */
5433 #define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)
5434 #define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)
5435 /* ================================================== UART_SRBR_STHR6_REG ================================================== */
5436 #define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)
5437 #define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)
5438 /* ================================================== UART_SRBR_STHR7_REG ================================================== */
5439 #define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)
5440 #define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)
5441 /* ================================================== UART_SRBR_STHR8_REG ================================================== */
5442 #define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)
5443 #define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)
5444 /* ================================================== UART_SRBR_STHR9_REG ================================================== */
5445 #define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)
5446 #define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)
5447 /* ===================================================== UART_SRR_REG ====================================================== */
5448 #define UART_UART_SRR_REG_UART_XFR_Pos (2UL)
5449 #define UART_UART_SRR_REG_UART_XFR_Msk (0x4UL)
5450 #define UART_UART_SRR_REG_UART_RFR_Pos (1UL)
5451 #define UART_UART_SRR_REG_UART_RFR_Msk (0x2UL)
5452 #define UART_UART_SRR_REG_UART_UR_Pos (0UL)
5453 #define UART_UART_SRR_REG_UART_UR_Msk (0x1UL)
5454 /* ===================================================== UART_SRT_REG ====================================================== */
5455 #define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)
5456 #define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)
5457 /* ===================================================== UART_STET_REG ===================================================== */
5458 #define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)
5459 #define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)
5460 /* ===================================================== UART_TFL_REG ====================================================== */
5461 #define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)
5462 #define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)
5463 /* ===================================================== UART_UCV_REG ====================================================== */
5464 #define UART_UART_UCV_REG_UART_UCV_Pos (0UL)
5465 #define UART_UART_UCV_REG_UART_UCV_Msk (0xffffffffUL)
5466 /* ===================================================== UART_USR_REG ====================================================== */
5467 #define UART_UART_USR_REG_UART_RFF_Pos (4UL)
5468 #define UART_UART_USR_REG_UART_RFF_Msk (0x10UL)
5469 #define UART_UART_USR_REG_UART_RFNE_Pos (3UL)
5470 #define UART_UART_USR_REG_UART_RFNE_Msk (0x8UL)
5471 #define UART_UART_USR_REG_UART_TFE_Pos (2UL)
5472 #define UART_UART_USR_REG_UART_TFE_Msk (0x4UL)
5473 #define UART_UART_USR_REG_UART_TFNF_Pos (1UL)
5474 #define UART_UART_USR_REG_UART_TFNF_Msk (0x2UL)
5475 #define UART_UART_USR_REG_UART_BUSY_Pos (0UL)
5476 #define UART_UART_USR_REG_UART_BUSY_Msk (0x1UL)
5479 /* =========================================================================================================================== */
5480 /* ================ UART2 ================ */
5481 /* =========================================================================================================================== */
5482 
5483 /* =================================================== UART2_CONFIG_REG ==================================================== */
5484 #define UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos (3UL)
5485 #define UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk (0xf8UL)
5486 #define UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Pos (2UL)
5487 #define UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Msk (0x4UL)
5488 #define UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos (1UL)
5489 #define UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk (0x2UL)
5490 #define UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Pos (0UL)
5491 #define UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Msk (0x1UL)
5492 /* ==================================================== UART2_CTRL_REG ===================================================== */
5493 #define UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Pos (11UL)
5494 #define UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Msk (0x800UL)
5495 #define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos (10UL)
5496 #define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk (0x400UL)
5497 #define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos (9UL)
5498 #define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk (0x200UL)
5499 #define UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos (8UL)
5500 #define UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk (0x100UL)
5501 #define UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Pos (7UL)
5502 #define UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Msk (0x80UL)
5503 #define UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Pos (6UL)
5504 #define UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Msk (0x40UL)
5505 #define UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Pos (5UL)
5506 #define UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Msk (0x20UL)
5507 #define UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Pos (0UL)
5508 #define UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Msk (0x1fUL)
5509 /* ===================================================== UART2_CTR_REG ===================================================== */
5510 #define UART2_UART2_CTR_REG_UART_CTR_Pos (0UL)
5511 #define UART2_UART2_CTR_REG_UART_CTR_Msk (0xffffffffUL)
5512 /* ===================================================== UART2_DLF_REG ===================================================== */
5513 #define UART2_UART2_DLF_REG_UART_DLF_Pos (0UL)
5514 #define UART2_UART2_DLF_REG_UART_DLF_Msk (0xfUL)
5515 /* ==================================================== UART2_DMASA_REG ==================================================== */
5516 #define UART2_UART2_DMASA_REG_UART_DMASA_Pos (0UL)
5517 #define UART2_UART2_DMASA_REG_UART_DMASA_Msk (0x1UL)
5518 /* ================================================== UART2_ERR_CTRL_REG =================================================== */
5519 #define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos (4UL)
5520 #define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk (0x1f0UL)
5521 #define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos (0UL)
5522 #define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk (0xfUL)
5523 /* ===================================================== UART2_HTX_REG ===================================================== */
5524 #define UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL)
5525 #define UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL)
5526 /* =================================================== UART2_IER_DLH_REG =================================================== */
5527 #define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos (7UL)
5528 #define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)
5529 #define UART2_UART2_IER_DLH_REG_DLH6_5_Pos (5UL)
5530 #define UART2_UART2_IER_DLH_REG_DLH6_5_Msk (0x60UL)
5531 #define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)
5532 #define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)
5533 #define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)
5534 #define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)
5535 #define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos (2UL)
5536 #define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)
5537 #define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)
5538 #define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)
5539 #define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)
5540 #define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)
5541 /* =================================================== UART2_IIR_FCR_REG =================================================== */
5542 #define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL)
5543 #define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)
5544 /* ================================================= UART2_IRQ_STATUS_REG ================================================== */
5545 #define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos (2UL)
5546 #define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk (0x4UL)
5547 #define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos (1UL)
5548 #define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk (0x2UL)
5549 #define UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos (0UL)
5550 #define UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk (0x1UL)
5551 /* ===================================================== UART2_LCR_EXT ===================================================== */
5552 #define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL)
5553 #define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL)
5554 #define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos (2UL)
5555 #define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL)
5556 #define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos (1UL)
5557 #define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL)
5558 #define UART2_UART2_LCR_EXT_UART_DLS_E_Pos (0UL)
5559 #define UART2_UART2_LCR_EXT_UART_DLS_E_Msk (0x1UL)
5560 /* ===================================================== UART2_LCR_REG ===================================================== */
5561 #define UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL)
5562 #define UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL)
5563 #define UART2_UART2_LCR_REG_UART_BC_Pos (6UL)
5564 #define UART2_UART2_LCR_REG_UART_BC_Msk (0x40UL)
5565 #define UART2_UART2_LCR_REG_UART_SP_Pos (5UL)
5566 #define UART2_UART2_LCR_REG_UART_SP_Msk (0x20UL)
5567 #define UART2_UART2_LCR_REG_UART_EPS_Pos (4UL)
5568 #define UART2_UART2_LCR_REG_UART_EPS_Msk (0x10UL)
5569 #define UART2_UART2_LCR_REG_UART_PEN_Pos (3UL)
5570 #define UART2_UART2_LCR_REG_UART_PEN_Msk (0x8UL)
5571 #define UART2_UART2_LCR_REG_UART_STOP_Pos (2UL)
5572 #define UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL)
5573 #define UART2_UART2_LCR_REG_UART_DLS_Pos (0UL)
5574 #define UART2_UART2_LCR_REG_UART_DLS_Msk (0x3UL)
5575 /* ===================================================== UART2_LSR_REG ===================================================== */
5576 #define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos (8UL)
5577 #define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL)
5578 #define UART2_UART2_LSR_REG_UART_RFE_Pos (7UL)
5579 #define UART2_UART2_LSR_REG_UART_RFE_Msk (0x80UL)
5580 #define UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL)
5581 #define UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL)
5582 #define UART2_UART2_LSR_REG_UART_THRE_Pos (5UL)
5583 #define UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL)
5584 #define UART2_UART2_LSR_REG_UART_BI_Pos (4UL)
5585 #define UART2_UART2_LSR_REG_UART_BI_Msk (0x10UL)
5586 #define UART2_UART2_LSR_REG_UART_FE_Pos (3UL)
5587 #define UART2_UART2_LSR_REG_UART_FE_Msk (0x8UL)
5588 #define UART2_UART2_LSR_REG_UART_PE_Pos (2UL)
5589 #define UART2_UART2_LSR_REG_UART_PE_Msk (0x4UL)
5590 #define UART2_UART2_LSR_REG_UART_OE_Pos (1UL)
5591 #define UART2_UART2_LSR_REG_UART_OE_Msk (0x2UL)
5592 #define UART2_UART2_LSR_REG_UART_DR_Pos (0UL)
5593 #define UART2_UART2_LSR_REG_UART_DR_Msk (0x1UL)
5594 /* ===================================================== UART2_MCR_REG ===================================================== */
5595 #define UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL)
5596 #define UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL)
5597 #define UART2_UART2_MCR_REG_UART_LB_Pos (4UL)
5598 #define UART2_UART2_MCR_REG_UART_LB_Msk (0x10UL)
5599 #define UART2_UART2_MCR_REG_UART_RTS_Pos (1UL)
5600 #define UART2_UART2_MCR_REG_UART_RTS_Msk (0x2UL)
5601 /* ===================================================== UART2_MSR_REG ===================================================== */
5602 #define UART2_UART2_MSR_REG_UART_CTS_Pos (4UL)
5603 #define UART2_UART2_MSR_REG_UART_CTS_Msk (0x10UL)
5604 #define UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL)
5605 #define UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL)
5606 /* ===================================================== UART2_RAR_REG ===================================================== */
5607 #define UART2_UART2_RAR_REG_UART_RAR_Pos (0UL)
5608 #define UART2_UART2_RAR_REG_UART_RAR_Msk (0xffUL)
5609 /* ================================================= UART2_RBR_THR_DLL_REG ================================================= */
5610 #define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL)
5611 #define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL)
5612 #define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)
5613 #define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)
5614 /* ===================================================== UART2_RFL_REG ===================================================== */
5615 #define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)
5616 #define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)
5617 /* ==================================================== UART2_SBCR_REG ===================================================== */
5618 #define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)
5619 #define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)
5620 /* ==================================================== UART2_SDMAM_REG ==================================================== */
5621 #define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)
5622 #define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)
5623 /* ===================================================== UART2_SFE_REG ===================================================== */
5624 #define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)
5625 #define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)
5626 /* ================================================= UART2_SRBR_STHR0_REG ================================================== */
5627 #define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)
5628 #define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)
5629 /* ================================================= UART2_SRBR_STHR10_REG ================================================= */
5630 #define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)
5631 #define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)
5632 /* ================================================= UART2_SRBR_STHR11_REG ================================================= */
5633 #define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)
5634 #define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)
5635 /* ================================================= UART2_SRBR_STHR12_REG ================================================= */
5636 #define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)
5637 #define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)
5638 /* ================================================= UART2_SRBR_STHR13_REG ================================================= */
5639 #define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)
5640 #define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)
5641 /* ================================================= UART2_SRBR_STHR14_REG ================================================= */
5642 #define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)
5643 #define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)
5644 /* ================================================= UART2_SRBR_STHR15_REG ================================================= */
5645 #define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)
5646 #define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)
5647 /* ================================================= UART2_SRBR_STHR1_REG ================================================== */
5648 #define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)
5649 #define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)
5650 /* ================================================= UART2_SRBR_STHR2_REG ================================================== */
5651 #define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)
5652 #define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)
5653 /* ================================================= UART2_SRBR_STHR3_REG ================================================== */
5654 #define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)
5655 #define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)
5656 /* ================================================= UART2_SRBR_STHR4_REG ================================================== */
5657 #define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)
5658 #define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)
5659 /* ================================================= UART2_SRBR_STHR5_REG ================================================== */
5660 #define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)
5661 #define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)
5662 /* ================================================= UART2_SRBR_STHR6_REG ================================================== */
5663 #define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)
5664 #define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)
5665 /* ================================================= UART2_SRBR_STHR7_REG ================================================== */
5666 #define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)
5667 #define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)
5668 /* ================================================= UART2_SRBR_STHR8_REG ================================================== */
5669 #define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)
5670 #define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)
5671 /* ================================================= UART2_SRBR_STHR9_REG ================================================== */
5672 #define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)
5673 #define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)
5674 /* ===================================================== UART2_SRR_REG ===================================================== */
5675 #define UART2_UART2_SRR_REG_UART_XFR_Pos (2UL)
5676 #define UART2_UART2_SRR_REG_UART_XFR_Msk (0x4UL)
5677 #define UART2_UART2_SRR_REG_UART_RFR_Pos (1UL)
5678 #define UART2_UART2_SRR_REG_UART_RFR_Msk (0x2UL)
5679 #define UART2_UART2_SRR_REG_UART_UR_Pos (0UL)
5680 #define UART2_UART2_SRR_REG_UART_UR_Msk (0x1UL)
5681 /* ==================================================== UART2_SRTS_REG ===================================================== */
5682 #define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL)
5683 #define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL)
5684 /* ===================================================== UART2_SRT_REG ===================================================== */
5685 #define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)
5686 #define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)
5687 /* ==================================================== UART2_STET_REG ===================================================== */
5688 #define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)
5689 #define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)
5690 /* ===================================================== UART2_TAR_REG ===================================================== */
5691 #define UART2_UART2_TAR_REG_UART_TAR_Pos (0UL)
5692 #define UART2_UART2_TAR_REG_UART_TAR_Msk (0xffUL)
5693 /* ===================================================== UART2_TFL_REG ===================================================== */
5694 #define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)
5695 #define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)
5696 /* ==================================================== UART2_TIMER_REG ==================================================== */
5697 #define UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Pos (17UL)
5698 #define UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Msk (0x20000UL)
5699 #define UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Pos (16UL)
5700 #define UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Msk (0x10000UL)
5701 #define UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Pos (0UL)
5702 #define UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Msk (0xffffUL)
5703 /* ===================================================== UART2_UCV_REG ===================================================== */
5704 #define UART2_UART2_UCV_REG_UART_UCV_Pos (0UL)
5705 #define UART2_UART2_UCV_REG_UART_UCV_Msk (0xffffffffUL)
5706 /* ===================================================== UART2_USR_REG ===================================================== */
5707 #define UART2_UART2_USR_REG_UART_RFF_Pos (4UL)
5708 #define UART2_UART2_USR_REG_UART_RFF_Msk (0x10UL)
5709 #define UART2_UART2_USR_REG_UART_RFNE_Pos (3UL)
5710 #define UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL)
5711 #define UART2_UART2_USR_REG_UART_TFE_Pos (2UL)
5712 #define UART2_UART2_USR_REG_UART_TFE_Msk (0x4UL)
5713 #define UART2_UART2_USR_REG_UART_TFNF_Pos (1UL)
5714 #define UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL)
5715 #define UART2_UART2_USR_REG_UART_BUSY_Pos (0UL)
5716 #define UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL)
5719 /* =========================================================================================================================== */
5720 /* ================ WAKEUP ================ */
5721 /* =========================================================================================================================== */
5722 
5723 /* =================================================== WKUP_CLEAR_P0_REG =================================================== */
5724 #define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos (0UL)
5725 #define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk (0xffffUL)
5726 /* =================================================== WKUP_CLEAR_P1_REG =================================================== */
5727 #define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos (0UL)
5728 #define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk (0xffffUL)
5729 /* ===================================================== WKUP_CTRL_REG ===================================================== */
5730 #define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL)
5731 #define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL)
5732 #define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL)
5733 #define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL)
5734 #define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL)
5735 #define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL)
5736 /* ==================================================== WKUP_POL_P0_REG ==================================================== */
5737 #define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL)
5738 #define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffffUL)
5739 /* ==================================================== WKUP_POL_P1_REG ==================================================== */
5740 #define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL)
5741 #define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0xffffUL)
5742 /* ================================================== WKUP_RESET_IRQ_REG =================================================== */
5743 #define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL)
5744 #define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL)
5745 /* ================================================= WKUP_SEL1_GPIO_P0_REG ================================================= */
5746 #define WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Pos (0UL)
5747 #define WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Msk (0xffffUL)
5748 /* ================================================= WKUP_SEL1_GPIO_P1_REG ================================================= */
5749 #define WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Pos (0UL)
5750 #define WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Msk (0xffffUL)
5751 /* ================================================== WKUP_SELECT_P0_REG =================================================== */
5752 #define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL)
5753 #define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffffUL)
5754 /* ================================================== WKUP_SELECT_P1_REG =================================================== */
5755 #define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL)
5756 #define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0xffffUL)
5757 /* ================================================= WKUP_SEL_GPIO_P0_REG ================================================== */
5758 #define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL)
5759 #define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffffUL)
5760 /* ================================================= WKUP_SEL_GPIO_P1_REG ================================================== */
5761 #define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL)
5762 #define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0xffffUL)
5763 /* ================================================== WKUP_STATUS_P0_REG =================================================== */
5764 #define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos (0UL)
5765 #define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk (0xffffUL)
5766 /* ================================================== WKUP_STATUS_P1_REG =================================================== */
5767 #define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos (0UL)
5768 #define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk (0xffffUL) /* End of group PosMask_peripherals */
5771 
5772 
5773 #ifdef __cplusplus
5774 }
5775 #endif
5776 
5777 #endif /* DA1459X_H */
5778 
5779  /* End of group DA1459x */
5781  /* End of group PLA_BSP_REGISTERS */
SRC2_Type::SRC2_CTRL_REG
__IOM uint32_t SRC2_CTRL_REG
Definition: DA1459x-00.h:1066
GPIO_Type::P1_05_MODE_REG
__IOM uint32_t P1_05_MODE_REG
Definition: DA1459x-00.h:683
TIMER4_Type::TIMER4_TIMER_VAL_REG
__IOM uint32_t TIMER4_TIMER_VAL_REG
Definition: DA1459x-00.h:1216
QUADEC_Type::QDEC_ZCNT_REG
__IOM uint32_t QDEC_ZCNT_REG
Definition: DA1459x-00.h:940
MEMCTRL_Type::MEM_STATUS2_REG
__IOM uint32_t MEM_STATUS2_REG
Definition: DA1459x-00.h:821
GPIO_P0_IRQn
Definition: DA1459x-00.h:117
CRG_PER_Type::CLK_PER_REG
__IOM uint32_t CLK_PER_REG
Definition: DA1459x-00.h:374
DMA_Type::DMA2_A_START_REG
__IOM uint32_t DMA2_A_START_REG
Definition: DA1459x-00.h:528
WAKEUP_Type
WAKEUP registers (WAKEUP)
Definition: DA1459x-00.h:1365
SDADC_Type::SDADC_CLEAR_INT_REG
__IOM uint32_t SDADC_CLEAR_INT_REG
Definition: DA1459x-00.h:995
CACHE_Type::CACHE_EFLASH_REG
__IOM uint32_t CACHE_EFLASH_REG
Definition: DA1459x-00.h:243
QSPIC_Type::QSPIC_BURSTCMDA_REG
__IOM uint32_t QSPIC_BURSTCMDA_REG
Definition: DA1459x-00.h:900
TIMER2_Type::TIMER2_PRESCALER_VAL_REG
__IOM uint32_t TIMER2_PRESCALER_VAL_REG
Definition: DA1459x-00.h:1170
DW_Type::AHB_DMA_CCLM4_REG
__IOM uint32_t AHB_DMA_CCLM4_REG
Definition: DA1459x-00.h:593
CRG_TOP_Type::POWER_CTRL_REG
__IOM uint32_t POWER_CTRL_REG
Definition: DA1459x-00.h:448
TIMER3_Type::TIMER3_PRESCALER_VAL_REG
__IOM uint32_t TIMER3_PRESCALER_VAL_REG
Definition: DA1459x-00.h:1197
__IOM
#define __IOM
Definition: core_cm0.h:174
QSPIC_Type::QSPIC_ERASECMDA_REG
__IOM uint32_t QSPIC_ERASECMDA_REG
Definition: DA1459x-00.h:909
CACHE_Type::SWD_RESET_REG
__IOM uint32_t SWD_RESET_REG
Definition: DA1459x-00.h:251
RTC_EVENT_IRQn
Definition: DA1459x-00.h:116
MEMCTRL_Type::BUSY_SET_REG
__IOM uint32_t BUSY_SET_REG
Definition: DA1459x-00.h:827
PDC_Type::PDC_CTRL3_REG
__IOM uint32_t PDC_CTRL3_REG
Definition: DA1459x-00.h:866
GPIO_Type::P0_08_MODE_REG
__IOM uint32_t P0_08_MODE_REG
Definition: DA1459x-00.h:670
GPIO_Type::P0_02_MODE_REG
__IOM uint32_t P0_02_MODE_REG
Definition: DA1459x-00.h:664
DW_Type::AHB_DMA_CCLM2_REG
__IOM uint32_t AHB_DMA_CCLM2_REG
Definition: DA1459x-00.h:590
UART_Type::UART_MCR_REG
__IOM uint32_t UART_MCR_REG
Definition: DA1459x-00.h:1247
FCU_Type::FLASH_RTERASE_SEG_CNT_REG
__IOM uint32_t FLASH_RTERASE_SEG_CNT_REG
Definition: DA1459x-00.h:618
SRC1_Type::SRC1_COEF10_SET1_REG
__IOM uint32_t SRC1_COEF10_SET1_REG
Definition: DA1459x-00.h:1046
UART_Type::UART_SRBR_STHR15_REG
__IOM uint32_t UART_SRBR_STHR15_REG
Definition: DA1459x-00.h:1267
UART_Type::UART_IER_DLH_REG
__IOM uint32_t UART_IER_DLH_REG
Definition: DA1459x-00.h:1243
HardFault_IRQn
Definition: DA1459x-00.h:71
UART2_Type::UART2_SRBR_STHR12_REG
__IOM uint32_t UART2_SRBR_STHR12_REG
Definition: DA1459x-00.h:1322
system_DA1459x.h
CMSIS Device System Header File for DA1459x Device.
I2C_Type::I2C_CLR_RX_OVER_REG
__IOM uint32_t I2C_CLR_RX_OVER_REG
Definition: DA1459x-00.h:752
UART_Type::UART_SRBR_STHR11_REG
__IOM uint32_t UART_SRBR_STHR11_REG
Definition: DA1459x-00.h:1263
QSPIC_Type::QSPIC_CHCKERASE_REG
__IOM uint32_t QSPIC_CHCKERASE_REG
Definition: DA1459x-00.h:916
CACHE_Type::CACHE_CTRL2_REG
__IOM uint32_t CACHE_CTRL2_REG
Definition: DA1459x-00.h:224
CRG_XTAL_Type::XTAL32M_IRQ_STAT_REG
__IOM uint32_t XTAL32M_IRQ_STAT_REG
Definition: DA1459x-00.h:478
RTC_Type
RTC registers (RTC)
Definition: DA1459x-00.h:955
UART2_Type::UART2_SRBR_STHR15_REG
__IOM uint32_t UART2_SRBR_STHR15_REG
Definition: DA1459x-00.h:1325
CRG_TOP_Type::P1_RESET_PAD_LATCH_REG
__IOM uint32_t P1_RESET_PAD_LATCH_REG
Definition: DA1459x-00.h:431
I2C_Type::I2C_CLR_TX_OVER_REG
__IOM uint32_t I2C_CLR_TX_OVER_REG
Definition: DA1459x-00.h:753
TIMER2_Type
TIMER2 registers (TIMER2)
Definition: DA1459x-00.h:1159
AES_HASH_Type::CRYPTO_START_REG
__IOM uint32_t CRYPTO_START_REG
Definition: DA1459x-00.h:177
GPIO_Type::P1_04_MODE_REG
__IOM uint32_t P1_04_MODE_REG
Definition: DA1459x-00.h:682
TIMER2_Type::TIMER2_SHOTWIDTH_REG
__IOM uint32_t TIMER2_SHOTWIDTH_REG
Definition: DA1459x-00.h:1166
GPIO_Type::P1_SET_DATA_REG
__IOM uint32_t P1_SET_DATA_REG
Definition: DA1459x-00.h:659
UART2_Type::UART2_RBR_THR_DLL_REG
__IOM uint32_t UART2_RBR_THR_DLL_REG
Definition: DA1459x-00.h:1300
SYS_WDOG_Type
SYS_WDOG registers (SYS_WDOG)
Definition: DA1459x-00.h:1093
DW_Type::AHB_DMA_VERSION_REG
__IOM uint32_t AHB_DMA_VERSION_REG
Definition: DA1459x-00.h:595
CRG_SYS_Type::CLK_SYS_REG
__IOM uint32_t CLK_SYS_REG
Definition: DA1459x-00.h:393
TIMER_Type::TIMER_GPIO1_CONF_REG
__IOM uint32_t TIMER_GPIO1_CONF_REG
Definition: DA1459x-00.h:1130
SPI_Type::SPI_IRQ_MASK_REG
__IOM uint32_t SPI_IRQ_MASK_REG
Definition: DA1459x-00.h:1016
GPREG_Type::RESET_FREEZE_REG
__IOM uint32_t RESET_FREEZE_REG
Definition: DA1459x-00.h:714
GPIO_Type::P0_01_MODE_REG
__IOM uint32_t P0_01_MODE_REG
Definition: DA1459x-00.h:663
GPADC_Type::GP_ADC_SEL_REG
__IOM uint32_t GP_ADC_SEL_REG
Definition: DA1459x-00.h:636
SRC2_Type::SRC2_IN_FS_REG
__IOM uint32_t SRC2_IN_FS_REG
Definition: DA1459x-00.h:1067
FCU_Type::FLASH_PTNVH1_REG
__IOM uint32_t FLASH_PTNVH1_REG
Definition: DA1459x-00.h:611
UART2_Type::UART2_CTRL_REG
__IOM uint32_t UART2_CTRL_REG
Definition: DA1459x-00.h:1345
DMA_Type::DMA5_A_START_REG
__IOM uint32_t DMA5_A_START_REG
Definition: DA1459x-00.h:549
UART_Type::UART_SRBR_STHR4_REG
__IOM uint32_t UART_SRBR_STHR4_REG
Definition: DA1459x-00.h:1256
CRG_TOP_Type::ANA_STATUS_REG
__IOM uint32_t ANA_STATUS_REG
Definition: DA1459x-00.h:447
CRG_AUD_Type
CRG_AUD registers (CRG_AUD)
Definition: DA1459x-00.h:333
TIMER2_Type::TIMER2_CAPTURE_GPIO2_REG
__IOM uint32_t TIMER2_CAPTURE_GPIO2_REG
Definition: DA1459x-00.h:1169
MDCT_Type::MDCT_STAGE4_REG
__IOM uint32_t MDCT_STAGE4_REG
Definition: DA1459x-00.h:798
RTC_Type::RTC_ALARM_ENABLE_REG
__IOM uint32_t RTC_ALARM_ENABLE_REG
Definition: DA1459x-00.h:962
CRG_TOP_Type::HIBERN_CTRL_REG
__IOM uint32_t HIBERN_CTRL_REG
Definition: DA1459x-00.h:451
I2C_Type::I2C_CLR_TX_ABRT_REG
__IOM uint32_t I2C_CLR_TX_ABRT_REG
Definition: DA1459x-00.h:755
UART2_Type::UART2_SRBR_STHR2_REG
__IOM uint32_t UART2_SRBR_STHR2_REG
Definition: DA1459x-00.h:1312
RTC_Type::RTC_INTERRUPT_DISABLE_REG
__IOM uint32_t RTC_INTERRUPT_DISABLE_REG
Definition: DA1459x-00.h:965
CMAC2SYS_IRQn
Definition: DA1459x-00.h:85
CRG_TOP_Type::P0_PAD_LATCH_REG
__IOM uint32_t P0_PAD_LATCH_REG
Definition: DA1459x-00.h:426
CRG_TOP_Type::CLK_AMBA_REG
__IOM uint32_t CLK_AMBA_REG
Definition: DA1459x-00.h:408
CRG_XTAL_Type::XTAL32M_CAP_MEAS_REG
__IOM uint32_t XTAL32M_CAP_MEAS_REG
Definition: DA1459x-00.h:472
CACHE_Type::CACHE_FLASH_REG
__IOM uint32_t CACHE_FLASH_REG
Definition: DA1459x-00.h:239
I2C_Type::I2C_TXFLR_REG
__IOM uint32_t I2C_TXFLR_REG
Definition: DA1459x-00.h:763
UART2_Type::UART2_IIR_FCR_REG
__IOM uint32_t UART2_IIR_FCR_REG
Definition: DA1459x-00.h:1302
GPREG_Type::SET_FREEZE_REG
__IOM uint32_t SET_FREEZE_REG
Definition: DA1459x-00.h:712
CRG_TOP_Type
CRG_TOP registers (CRG_TOP)
Definition: DA1459x-00.h:407
SDADC_Type::SDADC_RESULT_REG
__IOM uint32_t SDADC_RESULT_REG
Definition: DA1459x-00.h:996
UART2_Type::UART2_ERR_CTRL_REG
__IOM uint32_t UART2_ERR_CTRL_REG
Definition: DA1459x-00.h:1347
TIMER_Type::TIMER_PRESCALER_VAL_REG
__IOM uint32_t TIMER_PRESCALER_VAL_REG
Definition: DA1459x-00.h:1137
TIMER_Type::TIMER_CAPTURE_GPIO2_REG
__IOM uint32_t TIMER_CAPTURE_GPIO2_REG
Definition: DA1459x-00.h:1136
UART2_Type::UART2_SRBR_STHR10_REG
__IOM uint32_t UART2_SRBR_STHR10_REG
Definition: DA1459x-00.h:1320
SRC1_Type::SRC1_COEF98_SET1_REG
__IOM uint32_t SRC1_COEF98_SET1_REG
Definition: DA1459x-00.h:1050
DMA_Type::DMA2_CTRL_REG
__IOM uint32_t DMA2_CTRL_REG
Definition: DA1459x-00.h:532
SYSB_Type::BRIDGE_REG
__IOM uint32_t BRIDGE_REG
Definition: DA1459x-00.h:1111
WAKEUP_Type::WKUP_STATUS_P0_REG
__IOM uint32_t WKUP_STATUS_P0_REG
Definition: DA1459x-00.h:1378
I2C_Type::I2C_HS_SCL_HCNT_REG
__IOM uint32_t I2C_HS_SCL_HCNT_REG
Definition: DA1459x-00.h:743
DMA_Type
DMA registers (DMA)
Definition: DA1459x-00.h:513
I2C_Type::I2C_SAR_REG
__IOM uint32_t I2C_SAR_REG
Definition: DA1459x-00.h:736
GPIO_Type::P1_WEAK_CTRL_REG
__IOM uint32_t P1_WEAK_CTRL_REG
Definition: DA1459x-00.h:697
I2C_Type::I2C_RX_TL_REG
__IOM uint32_t I2C_RX_TL_REG
Definition: DA1459x-00.h:748
UART_Type::UART_SRBR_STHR6_REG
__IOM uint32_t UART_SRBR_STHR6_REG
Definition: DA1459x-00.h:1258
TIMER3_IRQn
Definition: DA1459x-00.h:114
TIMER_Type::TIMER_CLEAR_IRQ_REG
__IOM uint32_t TIMER_CLEAR_IRQ_REG
Definition: DA1459x-00.h:1145
DMA_Type::DMA1_B_START_REG
__IOM uint32_t DMA1_B_START_REG
Definition: DA1459x-00.h:522
TIMER2_Type::TIMER2_STATUS_REG
__IOM uint32_t TIMER2_STATUS_REG
Definition: DA1459x-00.h:1162
TIMER4_Type::TIMER4_STATUS_REG
__IOM uint32_t TIMER4_STATUS_REG
Definition: DA1459x-00.h:1217
CRG_TOP_Type::RST_CTRL_REG
__IOM uint32_t RST_CTRL_REG
Definition: DA1459x-00.h:410
TIMER4_Type::TIMER4_CAPTURE_GPIO1_REG
__IOM uint32_t TIMER4_CAPTURE_GPIO1_REG
Definition: DA1459x-00.h:1222
UART2_Type::UART2_SRBR_STHR5_REG
__IOM uint32_t UART2_SRBR_STHR5_REG
Definition: DA1459x-00.h:1315
I2C_Type::I2C_HS_SCL_LCNT_REG
__IOM uint32_t I2C_HS_SCL_LCNT_REG
Definition: DA1459x-00.h:744
GPADC_Type::GP_ADC_CLEAR_INT_REG
__IOM uint32_t GP_ADC_CLEAR_INT_REG
Definition: DA1459x-00.h:640
CRG_XTAL_Type::XTAL32M_TRIM_REG
__IOM uint32_t XTAL32M_TRIM_REG
Definition: DA1459x-00.h:471
DMA_Type::DMA2_B_START_REG
__IOM uint32_t DMA2_B_START_REG
Definition: DA1459x-00.h:529
TIMER3_Type::TIMER3_CLEAR_IRQ_REG
__IOM uint32_t TIMER3_CLEAR_IRQ_REG
Definition: DA1459x-00.h:1200
I2C_IRQn
Definition: DA1459x-00.h:88
UART2_Type::UART2_STET_REG
__IOM uint32_t UART2_STET_REG
Definition: DA1459x-00.h:1336
CRG_TOP_Type::CLK_RCLP_REG
__IOM uint32_t CLK_RCLP_REG
Definition: DA1459x-00.h:419
SPI_Type::SPI_FIFO_STATUS_REG
__IOM uint32_t SPI_FIFO_STATUS_REG
Definition: DA1459x-00.h:1018
QSPIC_Type
QSPIC registers (QSPIC)
Definition: DA1459x-00.h:896
RESERVED22_IRQn
Definition: DA1459x-00.h:105
AES_HASH_Type::CRYPTO_FETCH_ADDR_REG
__IOM uint32_t CRYPTO_FETCH_ADDR_REG
Definition: DA1459x-00.h:178
SRC2_Type::SRC2_COEF98_SET1_REG
__IOM uint32_t SRC2_COEF98_SET1_REG
Definition: DA1459x-00.h:1078
QSPIC_Type::QSPIC_BURSTCMDB_REG
__IOM uint32_t QSPIC_BURSTCMDB_REG
Definition: DA1459x-00.h:902
KEY_WKUP_GPIO_IRQn
Definition: DA1459x-00.h:100
GPIO_Type::P1_03_MODE_REG
__IOM uint32_t P1_03_MODE_REG
Definition: DA1459x-00.h:681
QUADEC_Type
QUADEC registers (QUADEC)
Definition: DA1459x-00.h:934
TIMER_Type::TIMER_SETTINGS_REG
__IOM uint32_t TIMER_SETTINGS_REG
Definition: DA1459x-00.h:1132
NonMaskableInt_IRQn
Definition: DA1459x-00.h:70
QSPIC_Type::QSPIC_DUMMYDATA_REG
__IOM uint32_t QSPIC_DUMMYDATA_REG
Definition: DA1459x-00.h:907
MEMCTRL_Type
MEMCTRL registers (MEMCTRL)
Definition: DA1459x-00.h:816
SDADC_Type::SDADC_GAIN_CORR_REG
__IOM uint32_t SDADC_GAIN_CORR_REG
Definition: DA1459x-00.h:993
RTC_IRQn
Definition: DA1459x-00.h:99
UART2_Type::UART2_SRBR_STHR3_REG
__IOM uint32_t UART2_SRBR_STHR3_REG
Definition: DA1459x-00.h:1313
CRG_XTAL_Type::XTAL32M_SETTLE_REG
__IOM uint32_t XTAL32M_SETTLE_REG
Definition: DA1459x-00.h:470
WAKEUP_Type::WKUP_POL_P1_REG
__IOM uint32_t WKUP_POL_P1_REG
Definition: DA1459x-00.h:1376
WAKEUP_Type::WKUP_CLEAR_P1_REG
__IOM uint32_t WKUP_CLEAR_P1_REG
Definition: DA1459x-00.h:1382
TIMER4_Type::TIMER4_PWM_CTRL_REG
__IOM uint32_t TIMER4_PWM_CTRL_REG
Definition: DA1459x-00.h:1225
MDCT_Type::MDCT_STAGE5_REG
__IOM uint32_t MDCT_STAGE5_REG
Definition: DA1459x-00.h:799
GPIO_Type::GPIO_CLK_SEL_REG
__IOM uint32_t GPIO_CLK_SEL_REG
Definition: DA1459x-00.h:695
SRC1_Type::SRC1_IN_FS_REG
__IOM uint32_t SRC1_IN_FS_REG
Definition: DA1459x-00.h:1039
TIMER_IRQn
Definition: DA1459x-00.h:97
UART_Type::UART_IIR_FCR_REG
__IOM uint32_t UART_IIR_FCR_REG
Definition: DA1459x-00.h:1244
DMA_Type::DMA3_INT_REG
__IOM uint32_t DMA3_INT_REG
Definition: DA1459x-00.h:537
RTC_Type::RTC_INTERRUPT_MASK_REG
__IOM uint32_t RTC_INTERRUPT_MASK_REG
Definition: DA1459x-00.h:966
UART2_Type::UART2_TFL_REG
__IOM uint32_t UART2_TFL_REG
Definition: DA1459x-00.h:1328
I2C_Type::I2C_CLR_RD_REQ_REG
__IOM uint32_t I2C_CLR_RD_REQ_REG
Definition: DA1459x-00.h:754
DMA_Type::DMA_REQ_MUX_REG
__IOM uint32_t DMA_REQ_MUX_REG
Definition: DA1459x-00.h:556
SPI_Type
SPI registers (SPI)
Definition: DA1459x-00.h:1011
UART2_Type::UART2_RFL_REG
__IOM uint32_t UART2_RFL_REG
Definition: DA1459x-00.h:1329
CRG_TOP_Type::POR_PIN_REG
__IOM uint32_t POR_PIN_REG
Definition: DA1459x-00.h:433
SRC1_Type::SRC1_CTRL_REG
__IOM uint32_t SRC1_CTRL_REG
Definition: DA1459x-00.h:1038
CRG_TOP_Type::POWER_LEVEL_REG
__IOM uint32_t POWER_LEVEL_REG
Definition: DA1459x-00.h:449
DMA_Type::DMA0_B_START_REG
__IOM uint32_t DMA0_B_START_REG
Definition: DA1459x-00.h:515
CRG_AUD_Type::PCM_FDIV_REG
__IOM uint32_t PCM_FDIV_REG
Definition: DA1459x-00.h:336
CHIP_VERSION_Type::CHIP_TEST2_REG
__IOM uint32_t CHIP_TEST2_REG
Definition: DA1459x-00.h:275
UART_Type::UART_SRBR_STHR10_REG
__IOM uint32_t UART_SRBR_STHR10_REG
Definition: DA1459x-00.h:1262
DMA_Type::DMA3_CTRL_REG
__IOM uint32_t DMA3_CTRL_REG
Definition: DA1459x-00.h:539
Reset_IRQn
Definition: DA1459x-00.h:69
XTAL32M_RDY_IRQn
Definition: DA1459x-00.h:106
DMA_Type::DMA1_INT_REG
__IOM uint32_t DMA1_INT_REG
Definition: DA1459x-00.h:523
PDC_Type::PDC_CTRL1_REG
__IOM uint32_t PDC_CTRL1_REG
Definition: DA1459x-00.h:864
CHIP_VERSION_Type
CHIP_VERSION registers (CHIP_VERSION)
Definition: DA1459x-00.h:266
DMA_Type::DMA1_A_START_REG
__IOM uint32_t DMA1_A_START_REG
Definition: DA1459x-00.h:521
CRYPTO_IRQn
Definition: DA1459x-00.h:111
MDCT_Type::MDCT_STAGE1_REG
__IOM uint32_t MDCT_STAGE1_REG
Definition: DA1459x-00.h:795
DMA_Type::DMA3_LEN_REG
__IOM uint32_t DMA3_LEN_REG
Definition: DA1459x-00.h:538
RTC_Type::RTC_CALENDAR_ALARM_REG
__IOM uint32_t RTC_CALENDAR_ALARM_REG
Definition: DA1459x-00.h:961
QSPIC_Type::QSPIC_AWRITECMD_REG
__IOM uint32_t QSPIC_AWRITECMD_REG
Definition: DA1459x-00.h:918
I2C_Type::I2C_STATUS_REG
__IOM uint32_t I2C_STATUS_REG
Definition: DA1459x-00.h:762
QUADEC_Type::QDEC_EVENT_CNT_REG
__IOM uint32_t QDEC_EVENT_CNT_REG
Definition: DA1459x-00.h:941
DMA_Type::DMA_RESET_INT_MASK_REG
__IOM uint32_t DMA_RESET_INT_MASK_REG
Definition: DA1459x-00.h:561
GPREG_Type::DEBUG_REG
__IOM uint32_t DEBUG_REG
Definition: DA1459x-00.h:716
DMA_Type::DMA0_A_START_REG
__IOM uint32_t DMA0_A_START_REG
Definition: DA1459x-00.h:514
CRG_XTAL_Type
CRG_XTAL registers (CRG_XTAL)
Definition: DA1459x-00.h:468
RTC_Type::RTC_HOUR_MODE_REG
__IOM uint32_t RTC_HOUR_MODE_REG
Definition: DA1459x-00.h:957
GPREG_Type::SCPU_FCU_TAG_REG
__IOM uint32_t SCPU_FCU_TAG_REG
Definition: DA1459x-00.h:719
CRG_SYS_Type
CRG_SYS registers (CRG_SYS)
Definition: DA1459x-00.h:392
GPIO_Type::P1_09_MODE_REG
__IOM uint32_t P1_09_MODE_REG
Definition: DA1459x-00.h:687
WAKEUP_Type::WKUP_SEL_GPIO_P0_REG
__IOM uint32_t WKUP_SEL_GPIO_P0_REG
Definition: DA1459x-00.h:1384
UART_Type::UART_LSR_REG
__IOM uint32_t UART_LSR_REG
Definition: DA1459x-00.h:1248
FCU_Type
FCU registers (FCU)
Definition: DA1459x-00.h:609
UART_Type::UART_DLF_REG
__IOM uint32_t UART_DLF_REG
Definition: DA1459x-00.h:1282
I2C_Type::I2C_SDA_HOLD_REG
__IOM uint32_t I2C_SDA_HOLD_REG
Definition: DA1459x-00.h:765
RTC_Type::RTC_EVENT_CTRL_REG
__IOM uint32_t RTC_EVENT_CTRL_REG
Definition: DA1459x-00.h:970
RESERVED20_IRQn
Definition: DA1459x-00.h:103
TIMER4_Type::TIMER4_CTRL_REG
__IOM uint32_t TIMER4_CTRL_REG
Definition: DA1459x-00.h:1215
UsageFault_IRQn
Definition: DA1459x-00.h:76
SRC1_Type::SRC1_OUT1_REG
__IOM uint32_t SRC1_OUT1_REG
Definition: DA1459x-00.h:1043
UART_Type::UART_DMASA_REG
__IOM uint32_t UART_DMASA_REG
Definition: DA1459x-00.h:1280
WAKEUP_Type::WKUP_SEL_GPIO_P1_REG
__IOM uint32_t WKUP_SEL_GPIO_P1_REG
Definition: DA1459x-00.h:1385
UART2_Type::UART2_SRBR_STHR6_REG
__IOM uint32_t UART2_SRBR_STHR6_REG
Definition: DA1459x-00.h:1316
WAKEUP_Type::WKUP_CTRL_REG
__IOM uint32_t WKUP_CTRL_REG
Definition: DA1459x-00.h:1366
IRQn_Type
IRQn_Type
Interrupt Number Definition.
Definition: DA1459x-00.h:67
SRC2_Type::SRC2_COEF54_SET1_REG
__IOM uint32_t SRC2_COEF54_SET1_REG
Definition: DA1459x-00.h:1076
GPIO_Type::P0_09_MODE_REG
__IOM uint32_t P0_09_MODE_REG
Definition: DA1459x-00.h:671
PDC_Type::PDC_CTRL2_REG
__IOM uint32_t PDC_CTRL2_REG
Definition: DA1459x-00.h:865
CMAC_CACHE_Type::CM_CACHE_MRM_MISSES_THRES_REG
__IOM uint32_t CM_CACHE_MRM_MISSES_THRES_REG
Definition: DA1459x-00.h:302
RTC_Type::RTC_PDC_EVENT_CNT_REG
__IOM uint32_t RTC_PDC_EVENT_CNT_REG
Definition: DA1459x-00.h:975
QUADDEC_IRQn
Definition: DA1459x-00.h:104
SRC1_Type::SRC1_IN2_REG
__IOM uint32_t SRC1_IN2_REG
Definition: DA1459x-00.h:1042
SRC2_Type::SRC2_COEF0A_SET1_REG
__IOM uint32_t SRC2_COEF0A_SET1_REG
Definition: DA1459x-00.h:1079
SYS_WDOG_Type::WATCHDOG_REG
__IOM uint32_t WATCHDOG_REG
Definition: DA1459x-00.h:1094
I2C_Type::I2C_CLR_ACTIVITY_REG
__IOM uint32_t I2C_CLR_ACTIVITY_REG
Definition: DA1459x-00.h:757
SRC2_Type::SRC2_IN1_REG
__IOM uint32_t SRC2_IN1_REG
Definition: DA1459x-00.h:1069
UART_Type::UART_SRBR_STHR3_REG
__IOM uint32_t UART_SRBR_STHR3_REG
Definition: DA1459x-00.h:1255
TIMER3_Type::TIMER3_GPIO1_CONF_REG
__IOM uint32_t TIMER3_GPIO1_CONF_REG
Definition: DA1459x-00.h:1191
CHIP_VERSION_Type::CHIP_SWC_REG
__IOM uint32_t CHIP_SWC_REG
Definition: DA1459x-00.h:271
SRC2_Type::SRC2_OUT_FS_REG
__IOM uint32_t SRC2_OUT_FS_REG
Definition: DA1459x-00.h:1068
UART_Type::UART_UCV_REG
__IOM uint32_t UART_UCV_REG
Definition: DA1459x-00.h:1284
GPIO_Type::P1_01_MODE_REG
__IOM uint32_t P1_01_MODE_REG
Definition: DA1459x-00.h:679
DW_Type::AHB_DMA_CCLM3_REG
__IOM uint32_t AHB_DMA_CCLM3_REG
Definition: DA1459x-00.h:591
CRG_COM_Type::RESET_CLK_COM_REG
__IOM uint32_t RESET_CLK_COM_REG
Definition: DA1459x-00.h:357
DMA_Type::DMA5_IDX_REG
__IOM uint32_t DMA5_IDX_REG
Definition: DA1459x-00.h:554
RESERVED0_IRQn
Definition: DA1459x-00.h:83
PDC_Type::PDC_CTRL0_REG
__IOM uint32_t PDC_CTRL0_REG
Definition: DA1459x-00.h:863
DW_Type::AHB_DMA_PL2_REG
__IOM uint32_t AHB_DMA_PL2_REG
Definition: DA1459x-00.h:578
ANAMISC_BIF_Type::CLK_REF_VAL_REG
__IOM uint32_t CLK_REF_VAL_REG
Definition: DA1459x-00.h:207
TIMER3_Type::TIMER3_PWM_CTRL_REG
__IOM uint32_t TIMER3_PWM_CTRL_REG
Definition: DA1459x-00.h:1198
GPIO_Type::P0_DATA_REG
__IOM uint32_t P0_DATA_REG
Definition: DA1459x-00.h:656
FCU_Type::FLASH_PTERASE_SEG_REG
__IOM uint32_t FLASH_PTERASE_SEG_REG
Definition: DA1459x-00.h:616
DMA_Type::DMA4_LEN_REG
__IOM uint32_t DMA4_LEN_REG
Definition: DA1459x-00.h:545
UART_Type::UART_SRR_REG
__IOM uint32_t UART_SRR_REG
Definition: DA1459x-00.h:1272
DMA_Type::DMA4_IDX_REG
__IOM uint32_t DMA4_IDX_REG
Definition: DA1459x-00.h:547
DMA_Type::DMA1_LEN_REG
__IOM uint32_t DMA1_LEN_REG
Definition: DA1459x-00.h:524
AES_HASH_Type::CRYPTO_KEYS_START
__IOM uint32_t CRYPTO_KEYS_START
Definition: DA1459x-00.h:188
SPI_Type::SPI_STATUS_REG
__IOM uint32_t SPI_STATUS_REG
Definition: DA1459x-00.h:1017
RTC_Type::RTC_PDC_EVENT_PERIOD_REG
__IOM uint32_t RTC_PDC_EVENT_PERIOD_REG
Definition: DA1459x-00.h:972
CRG_TOP_Type::CLK_RTCDIV_REG
__IOM uint32_t CLK_RTCDIV_REG
Definition: DA1459x-00.h:423
PDC_Type
PDC registers (PDC)
Definition: DA1459x-00.h:862
UART2_Type::UART2_IER_DLH_REG
__IOM uint32_t UART2_IER_DLH_REG
Definition: DA1459x-00.h:1301
WAKEUP_Type::WKUP_SEL1_GPIO_P1_REG
__IOM uint32_t WKUP_SEL1_GPIO_P1_REG
Definition: DA1459x-00.h:1388
FCU_Type::FLASH_RTERASE_TOT_CNT_REG
__IOM uint32_t FLASH_RTERASE_TOT_CNT_REG
Definition: DA1459x-00.h:617
I2C_Type::I2C_ENABLE_REG
__IOM uint32_t I2C_ENABLE_REG
Definition: DA1459x-00.h:761
DMA_Type::DMA3_A_START_REG
__IOM uint32_t DMA3_A_START_REG
Definition: DA1459x-00.h:535
CACHE_Type::CACHE_MRM_CTRL_REG
__IOM uint32_t CACHE_MRM_CTRL_REG
Definition: DA1459x-00.h:231
I2C_Type::I2C_CLR_INTR_REG
__IOM uint32_t I2C_CLR_INTR_REG
Definition: DA1459x-00.h:750
MDCT_Type::MDCT_CTRL_REG
__IOM uint32_t MDCT_CTRL_REG
Definition: DA1459x-00.h:790
UART_Type::UART_SBCR_REG
__IOM uint32_t UART_SBCR_REG
Definition: DA1459x-00.h:1274
SPI_Type::SPI_CS_CONFIG_REG
__IOM uint32_t SPI_CS_CONFIG_REG
Definition: DA1459x-00.h:1021
CRG_PER_Type::RESERVED
__IM uint32_t RESERVED
Definition: DA1459x-00.h:373
SRC1_Type
SRC1 registers (SRC1)
Definition: DA1459x-00.h:1037
CAPTIMER_IRQn
Definition: DA1459x-00.h:112
SPI_IRQn
Definition: DA1459x-00.h:89
DMA_Type::DMA_SET_INT_MASK_REG
__IOM uint32_t DMA_SET_INT_MASK_REG
Definition: DA1459x-00.h:560
PDC_Type::PDC_CTRL6_REG
__IOM uint32_t PDC_CTRL6_REG
Definition: DA1459x-00.h:869
CRG_AUD_Type::SRC_DIV_REG
__IOM uint32_t SRC_DIV_REG
Definition: DA1459x-00.h:338
DMA_Type::DMA5_INT_REG
__IOM uint32_t DMA5_INT_REG
Definition: DA1459x-00.h:551
CRG_TOP_Type::P0_RESET_PAD_LATCH_REG
__IOM uint32_t P0_RESET_PAD_LATCH_REG
Definition: DA1459x-00.h:428
PDC_Type::PDC_CTRL7_REG
__IOM uint32_t PDC_CTRL7_REG
Definition: DA1459x-00.h:870
UART2_Type::UART2_SBCR_REG
__IOM uint32_t UART2_SBCR_REG
Definition: DA1459x-00.h:1332
TIMER3_Type::TIMER3_TIMER_VAL_REG
__IOM uint32_t TIMER3_TIMER_VAL_REG
Definition: DA1459x-00.h:1189
I2C_Type::I2C_DMA_CR_REG
__IOM uint32_t I2C_DMA_CR_REG
Definition: DA1459x-00.h:768
TIMER2_Type::TIMER2_CAPTURE_GPIO1_REG
__IOM uint32_t TIMER2_CAPTURE_GPIO1_REG
Definition: DA1459x-00.h:1168
MemoryManagement_IRQn
Definition: DA1459x-00.h:72
AES_HASH_Type::CRYPTO_MREG1_REG
__IOM uint32_t CRYPTO_MREG1_REG
Definition: DA1459x-00.h:184
ANAMISC_BIF_Type::CLK_REF_CNT_REG
__IOM uint32_t CLK_REF_CNT_REG
Definition: DA1459x-00.h:206
GPREG_Type::GP_STATUS_REG
__IOM uint32_t GP_STATUS_REG
Definition: DA1459x-00.h:717
SRC1_Type::SRC1_OUT2_REG
__IOM uint32_t SRC1_OUT2_REG
Definition: DA1459x-00.h:1044
FCU_Type::FLASH_CTRL_REG
__IOM uint32_t FLASH_CTRL_REG
Definition: DA1459x-00.h:610
RTC_Type::RTC_KEEP_RTC_REG
__IOM uint32_t RTC_KEEP_RTC_REG
Definition: DA1459x-00.h:968
SDADC_Type::SDADC_CTRL_REG
__IOM uint32_t SDADC_CTRL_REG
Definition: DA1459x-00.h:990
SecureFault_IRQn
Definition: DA1459x-00.h:77
AES_HASH_Type::CRYPTO_CLRIRQ_REG
__IOM uint32_t CRYPTO_CLRIRQ_REG
Definition: DA1459x-00.h:182
CMAC_CACHE_Type::CM_CACHE_MRM_HITS_THRES_REG
__IOM uint32_t CM_CACHE_MRM_HITS_THRES_REG
Definition: DA1459x-00.h:304
UART2_Type::UART2_MSR_REG
__IOM uint32_t UART2_MSR_REG
Definition: DA1459x-00.h:1307
I2C_Type::I2C_CON_REG
__IOM uint32_t I2C_CON_REG
Definition: DA1459x-00.h:734
MEMCTRL_Type::BUSY_RESET_REG
__IOM uint32_t BUSY_RESET_REG
Definition: DA1459x-00.h:828
GPIO_Type::P0_06_MODE_REG
__IOM uint32_t P0_06_MODE_REG
Definition: DA1459x-00.h:668
MDCT_Type::MDCT_STAGE3_REG
__IOM uint32_t MDCT_STAGE3_REG
Definition: DA1459x-00.h:797
DW_Type::AHB_DMA_TCL_REG
__IOM uint32_t AHB_DMA_TCL_REG
Definition: DA1459x-00.h:588
CRG_TOP_Type::CLK_XTAL32K_REG
__IOM uint32_t CLK_XTAL32K_REG
Definition: DA1459x-00.h:420
SYSB_Type
SYSB registers (SYSB)
Definition: DA1459x-00.h:1109
CHIP_VERSION_Type::CHIP_TEST1_REG
__IOM uint32_t CHIP_TEST1_REG
Definition: DA1459x-00.h:274
TIMER3_Type
TIMER3 registers (TIMER3)
Definition: DA1459x-00.h:1187
CMAC_CACHE_Type::CM_CACHE_RESET_REG
__IOM uint32_t CM_CACHE_RESET_REG
Definition: DA1459x-00.h:318
CRG_XTAL_Type::CLKDBLR_CTRL2_REG
__IOM uint32_t CLKDBLR_CTRL2_REG
Definition: DA1459x-00.h:482
I2C_Type::I2C_CLR_RX_DONE_REG
__IOM uint32_t I2C_CLR_RX_DONE_REG
Definition: DA1459x-00.h:756
UART2_Type::UART2_SRBR_STHR1_REG
__IOM uint32_t UART2_SRBR_STHR1_REG
Definition: DA1459x-00.h:1311
GPREG_Type
GPREG registers (GPREG)
Definition: DA1459x-00.h:711
CRG_XTAL_Type::CLKDBLR_CTRL1_REG
__IOM uint32_t CLKDBLR_CTRL1_REG
Definition: DA1459x-00.h:480
DMA_Type::DMA0_INT_REG
__IOM uint32_t DMA0_INT_REG
Definition: DA1459x-00.h:516
TIMER_Type::TIMER_CAPTURE_GPIO1_REG
__IOM uint32_t TIMER_CAPTURE_GPIO1_REG
Definition: DA1459x-00.h:1135
UART2_Type::UART2_LCR_REG
__IOM uint32_t UART2_LCR_REG
Definition: DA1459x-00.h:1304
GPIO_Type::P0_15_MODE_REG
__IOM uint32_t P0_15_MODE_REG
Definition: DA1459x-00.h:677
I2C_Type::I2C_HS_MADDR_REG
__IOM uint32_t I2C_HS_MADDR_REG
Definition: DA1459x-00.h:737
RTC_Type::RTC_INTERRUPT_ENABLE_REG
__IOM uint32_t RTC_INTERRUPT_ENABLE_REG
Definition: DA1459x-00.h:964
UART_Type::UART_SRBR_STHR2_REG
__IOM uint32_t UART_SRBR_STHR2_REG
Definition: DA1459x-00.h:1254
SDADC_Type::SDADC_AUDIO_FILT_REG
__IOM uint32_t SDADC_AUDIO_FILT_REG
Definition: DA1459x-00.h:997
CRG_TOP_Type::CLK_RC32M_REG
__IOM uint32_t CLK_RC32M_REG
Definition: DA1459x-00.h:421
UART_Type::UART_SCR_REG
__IOM uint32_t UART_SCR_REG
Definition: DA1459x-00.h:1250
PDC_Type::PDC_CONFIG_REG
__IOM uint32_t PDC_CONFIG_REG
Definition: DA1459x-00.h:882
DMA_IRQn
Definition: DA1459x-00.h:84
MDCT_Type
MDCT registers (MDCT)
Definition: DA1459x-00.h:789
I2C_Type::I2C_IC_FS_SPKLEN_REG
__IOM uint32_t I2C_IC_FS_SPKLEN_REG
Definition: DA1459x-00.h:774
I2C_Type::I2C_IC_HS_SPKLEN_REG
__IOM uint32_t I2C_IC_HS_SPKLEN_REG
Definition: DA1459x-00.h:775
TIMER2_Type::TIMER2_GPIO2_CONF_REG
__IOM uint32_t TIMER2_GPIO2_CONF_REG
Definition: DA1459x-00.h:1164
SRC2_IN_IRQn
Definition: DA1459x-00.h:94
DW_Type::AHB_DMA_PL3_REG
__IOM uint32_t AHB_DMA_PL3_REG
Definition: DA1459x-00.h:580
I2C_Type::I2C_SS_SCL_HCNT_REG
__IOM uint32_t I2C_SS_SCL_HCNT_REG
Definition: DA1459x-00.h:739
GPADC_Type::GP_ADC_CTRL3_REG
__IOM uint32_t GP_ADC_CTRL3_REG
Definition: DA1459x-00.h:635
UART2_Type::UART2_SRBR_STHR7_REG
__IOM uint32_t UART2_SRBR_STHR7_REG
Definition: DA1459x-00.h:1317
CMAC_CACHE_Type::CM_CACHE_MRM_CTRL_REG
__IOM uint32_t CM_CACHE_MRM_CTRL_REG
Definition: DA1459x-00.h:298
PDC_Type::PDC_ACKNOWLEDGE_REG
__IOM uint32_t PDC_ACKNOWLEDGE_REG
Definition: DA1459x-00.h:876
TIMER3_Type::TIMER3_SETTINGS_REG
__IOM uint32_t TIMER3_SETTINGS_REG
Definition: DA1459x-00.h:1193
TIMER2_Type::TIMER2_TIMER_VAL_REG
__IOM uint32_t TIMER2_TIMER_VAL_REG
Definition: DA1459x-00.h:1161
DMA_Type::DMA1_IDX_REG
__IOM uint32_t DMA1_IDX_REG
Definition: DA1459x-00.h:526
FCU_Type::FLASH_PTPROG_REG
__IOM uint32_t FLASH_PTPROG_REG
Definition: DA1459x-00.h:612
DW_Type
DW registers (DW)
Definition: DA1459x-00.h:575
UART2_Type::UART2_SRBR_STHR9_REG
__IOM uint32_t UART2_SRBR_STHR9_REG
Definition: DA1459x-00.h:1319
UART2_Type::UART2_TAR_REG
__IOM uint32_t UART2_TAR_REG
Definition: DA1459x-00.h:1342
TIMER_Type::TIMER_GPIO3_CONF_REG
__IOM uint32_t TIMER_GPIO3_CONF_REG
Definition: DA1459x-00.h:1140
CACHE_Type::CACHE_MRM_HITS_THRES_REG
__IOM uint32_t CACHE_MRM_HITS_THRES_REG
Definition: DA1459x-00.h:237
DMA_Type::DMA2_IDX_REG
__IOM uint32_t DMA2_IDX_REG
Definition: DA1459x-00.h:533
SRC2_Type::SRC2_MUX_REG
__IOM uint32_t SRC2_MUX_REG
Definition: DA1459x-00.h:1073
TIMER2_IRQn
Definition: DA1459x-00.h:98
SDADC_Type::SDADC_OFFS_CORR_REG
__IOM uint32_t SDADC_OFFS_CORR_REG
Definition: DA1459x-00.h:994
WAKEUP_Type::WKUP_SEL1_GPIO_P0_REG
__IOM uint32_t WKUP_SEL1_GPIO_P0_REG
Definition: DA1459x-00.h:1386
CMAC_CACHE_Type::CM_CACHE_CTRL2_REG
__IOM uint32_t CM_CACHE_CTRL2_REG
Definition: DA1459x-00.h:291
TIMER_Type::TIMER_GPIO4_CONF_REG
__IOM uint32_t TIMER_GPIO4_CONF_REG
Definition: DA1459x-00.h:1141
CACHE_Type::CACHE_MRM_MISSES_REG
__IOM uint32_t CACHE_MRM_MISSES_REG
Definition: DA1459x-00.h:229
TIMER4_IRQn
Definition: DA1459x-00.h:115
CMAC_CACHE_Type::CM_CACHE_MRM_TINT_REG
__IOM uint32_t CM_CACHE_MRM_TINT_REG
Definition: DA1459x-00.h:300
CRG_XTAL_Type::XTAL32M_STAT0_REG
__IOM uint32_t XTAL32M_STAT0_REG
Definition: DA1459x-00.h:477
UART_Type::UART_SRBR_STHR5_REG
__IOM uint32_t UART_SRBR_STHR5_REG
Definition: DA1459x-00.h:1257
QSPIC_Type::QSPIC_MEMBLEN_REG
__IOM uint32_t QSPIC_MEMBLEN_REG
Definition: DA1459x-00.h:920
CMAC_CACHE_Type
CMAC_CACHE registers (CMAC_CACHE)
Definition: DA1459x-00.h:289
RTC_Type::RTC_TIME_REG
__IOM uint32_t RTC_TIME_REG
Definition: DA1459x-00.h:958
GPADC_Type::GP_ADC_OFFN_REG
__IOM uint32_t GP_ADC_OFFN_REG
Definition: DA1459x-00.h:638
TIMER_Type::TIMER_TIMER_VAL_REG
__IOM uint32_t TIMER_TIMER_VAL_REG
Definition: DA1459x-00.h:1128
GPIO_Type::P0_13_MODE_REG
__IOM uint32_t P0_13_MODE_REG
Definition: DA1459x-00.h:675
MDCT_Type::MDCT_STAGE7_REG
__IOM uint32_t MDCT_STAGE7_REG
Definition: DA1459x-00.h:801
PDC_Type::PDC_PENDING_REG
__IOM uint32_t PDC_PENDING_REG
Definition: DA1459x-00.h:877
SYSB_Type::QSPI_ARB_REG
__IOM uint32_t QSPI_ARB_REG
Definition: DA1459x-00.h:1110
QSPIC_Type::QSPIC_ERASECTRL_REG
__IOM uint32_t QSPIC_ERASECTRL_REG
Definition: DA1459x-00.h:908
CACHE_Type::CACHE_MRM_HITS1WS_REG
__IOM uint32_t CACHE_MRM_HITS1WS_REG
Definition: DA1459x-00.h:247
ANAMISC_BIF_Type::CLK_CAL_IRQ_REG
__IOM uint32_t CLK_CAL_IRQ_REG
Definition: DA1459x-00.h:208
PCM1_Type::PCM1_IN1_REG
__IOM uint32_t PCM1_IN1_REG
Definition: DA1459x-00.h:845
QSPIC_Type::QSPIC_GP_REG
__IOM uint32_t QSPIC_GP_REG
Definition: DA1459x-00.h:917
I2C_Type::I2C_ACK_GENERAL_CALL_REG
__IOM uint32_t I2C_ACK_GENERAL_CALL_REG
Definition: DA1459x-00.h:772
GPIO_Type::P1_08_MODE_REG
__IOM uint32_t P1_08_MODE_REG
Definition: DA1459x-00.h:686
UART_Type::UART_STET_REG
__IOM uint32_t UART_STET_REG
Definition: DA1459x-00.h:1278
MDCT_IRQn
Definition: DA1459x-00.h:96
PDC_Type::PDC_PENDING_CM33_REG
__IOM uint32_t PDC_PENDING_CM33_REG
Definition: DA1459x-00.h:879
QUADEC_Type::QDEC_CLOCKDIV_REG
__IOM uint32_t QDEC_CLOCKDIV_REG
Definition: DA1459x-00.h:938
SRC1_Type::SRC1_OUT_FS_REG
__IOM uint32_t SRC1_OUT_FS_REG
Definition: DA1459x-00.h:1040
MEMCTRL_Type::CMI_SHARED_BASE_REG
__IOM uint32_t CMI_SHARED_BASE_REG
Definition: DA1459x-00.h:825
SRC1_Type::SRC1_COEF0A_SET1_REG
__IOM uint32_t SRC1_COEF0A_SET1_REG
Definition: DA1459x-00.h:1051
GPIO_Type::P0_RESET_DATA_REG
__IOM uint32_t P0_RESET_DATA_REG
Definition: DA1459x-00.h:660
GPIO_Type::P0_04_MODE_REG
__IOM uint32_t P0_04_MODE_REG
Definition: DA1459x-00.h:666
I2C_Type::I2C_SDA_SETUP_REG
__IOM uint32_t I2C_SDA_SETUP_REG
Definition: DA1459x-00.h:771
SRC2_Type::SRC2_COEF10_SET1_REG
__IOM uint32_t SRC2_COEF10_SET1_REG
Definition: DA1459x-00.h:1074
AES_HASH_Type::CRYPTO_MREG3_REG
__IOM uint32_t CRYPTO_MREG3_REG
Definition: DA1459x-00.h:186
SPI_Type::SPI_FIFO_CONFIG_REG
__IOM uint32_t SPI_FIFO_CONFIG_REG
Definition: DA1459x-00.h:1015
CLK_CALIBRATION_IRQn
Definition: DA1459x-00.h:107
GPADC_Type::GP_ADC_RESULT_REG
__IOM uint32_t GP_ADC_RESULT_REG
Definition: DA1459x-00.h:641
GPIO_Type::P1_RESET_DATA_REG
__IOM uint32_t P1_RESET_DATA_REG
Definition: DA1459x-00.h:661
UART2_Type::UART2_HTX_REG
__IOM uint32_t UART2_HTX_REG
Definition: DA1459x-00.h:1337
GPIO_Type::P1_00_MODE_REG
__IOM uint32_t P1_00_MODE_REG
Definition: DA1459x-00.h:678
GPIO_Type::P0_12_MODE_REG
__IOM uint32_t P0_12_MODE_REG
Definition: DA1459x-00.h:674
UART2_Type::UART2_SRBR_STHR13_REG
__IOM uint32_t UART2_SRBR_STHR13_REG
Definition: DA1459x-00.h:1323
CRG_XTAL_Type::XTAL32M_CTRL_REG
__IOM uint32_t XTAL32M_CTRL_REG
Definition: DA1459x-00.h:474
UART2_Type::UART2_LCR_EXT
__IOM uint32_t UART2_LCR_EXT
Definition: DA1459x-00.h:1343
MEMCTRL_Type::RESERVED
__IM uint32_t RESERVED
Definition: DA1459x-00.h:817
DMA_Type::DMA1_CTRL_REG
__IOM uint32_t DMA1_CTRL_REG
Definition: DA1459x-00.h:525
UART2_Type::UART2_SRBR_STHR11_REG
__IOM uint32_t UART2_SRBR_STHR11_REG
Definition: DA1459x-00.h:1321
GPIO_Type::P0_SET_DATA_REG
__IOM uint32_t P0_SET_DATA_REG
Definition: DA1459x-00.h:658
CACHE_Type::CACHE_MRM_MISSES_THRES_REG
__IOM uint32_t CACHE_MRM_MISSES_THRES_REG
Definition: DA1459x-00.h:235
UART2_Type::UART2_SRT_REG
__IOM uint32_t UART2_SRT_REG
Definition: DA1459x-00.h:1335
CACHE_Type
CACHE registers (CACHE)
Definition: DA1459x-00.h:222
CHIP_VERSION_Type::CHIP_ID1_REG
__IOM uint32_t CHIP_ID1_REG
Definition: DA1459x-00.h:267
FCU_Type::FLASH_PTME_REG
__IOM uint32_t FLASH_PTME_REG
Definition: DA1459x-00.h:614
GPIO_Type::P1_DATA_REG
__IOM uint32_t P1_DATA_REG
Definition: DA1459x-00.h:657
TIMER3_Type::TIMER3_GPIO2_CONF_REG
__IOM uint32_t TIMER3_GPIO2_CONF_REG
Definition: DA1459x-00.h:1192
UART_Type::UART_SRBR_STHR7_REG
__IOM uint32_t UART_SRBR_STHR7_REG
Definition: DA1459x-00.h:1259
DMA_Type::DMA4_CTRL_REG
__IOM uint32_t DMA4_CTRL_REG
Definition: DA1459x-00.h:546
GPADC_IRQn
Definition: DA1459x-00.h:108
PDC_Type::PDC_CTRL8_REG
__IOM uint32_t PDC_CTRL8_REG
Definition: DA1459x-00.h:871
TIMER_Type::TIMER_CAPTURE_GPIO3_REG
__IOM uint32_t TIMER_CAPTURE_GPIO3_REG
Definition: DA1459x-00.h:1142
UART_Type::UART_SRT_REG
__IOM uint32_t UART_SRT_REG
Definition: DA1459x-00.h:1277
MDCT_Type::MDCT_ZBASE_ADDR_REG
__IOM uint32_t MDCT_ZBASE_ADDR_REG
Definition: DA1459x-00.h:793
CHIP_VERSION_Type::CHIP_ID4_REG
__IOM uint32_t CHIP_ID4_REG
Definition: DA1459x-00.h:270
TIMER4_Type::TIMER4_PRESCALER_VAL_REG
__IOM uint32_t TIMER4_PRESCALER_VAL_REG
Definition: DA1459x-00.h:1224
DW_Type::AHB_DMA_PL4_REG
__IOM uint32_t AHB_DMA_PL4_REG
Definition: DA1459x-00.h:582
SDADC_Type
SDADC registers (SDADC)
Definition: DA1459x-00.h:989
UART2_Type::UART2_SRBR_STHR8_REG
__IOM uint32_t UART2_SRBR_STHR8_REG
Definition: DA1459x-00.h:1318
SRC1_Type::SRC1_IN1_REG
__IOM uint32_t SRC1_IN1_REG
Definition: DA1459x-00.h:1041
AES_HASH_Type::CRYPTO_LEN_REG
__IOM uint32_t CRYPTO_LEN_REG
Definition: DA1459x-00.h:179
PDC_Type::PDC_CTRL10_REG
__IOM uint32_t PDC_CTRL10_REG
Definition: DA1459x-00.h:873
CRG_XTAL_Type::XTAL32M_FSM_REG
__IOM uint32_t XTAL32M_FSM_REG
Definition: DA1459x-00.h:473
I2C_Type::I2C_DATA_CMD_REG
__IOM uint32_t I2C_DATA_CMD_REG
Definition: DA1459x-00.h:738
TIMER_Type::TIMER_SHOTWIDTH_REG
__IOM uint32_t TIMER_SHOTWIDTH_REG
Definition: DA1459x-00.h:1133
QUADEC_Type::QDEC_XCNT_REG
__IOM uint32_t QDEC_XCNT_REG
Definition: DA1459x-00.h:936
I2C_Type::I2C_SS_SCL_LCNT_REG
__IOM uint32_t I2C_SS_SCL_LCNT_REG
Definition: DA1459x-00.h:740
AES_HASH_Type::CRYPTO_MREG2_REG
__IOM uint32_t CRYPTO_MREG2_REG
Definition: DA1459x-00.h:185
I2C_Type::I2C_RAW_INTR_STAT_REG
__IOM uint32_t I2C_RAW_INTR_STAT_REG
Definition: DA1459x-00.h:747
SPI_Type::SPI_FIFO_READ_REG
__IOM uint32_t SPI_FIFO_READ_REG
Definition: DA1459x-00.h:1019
TIMER_Type::TIMER_GPIO2_CONF_REG
__IOM uint32_t TIMER_GPIO2_CONF_REG
Definition: DA1459x-00.h:1131
DW_Type::AHB_DMA_CCLM1_REG
__IOM uint32_t AHB_DMA_CCLM1_REG
Definition: DA1459x-00.h:589
DMA_Type::DMA2_INT_REG
__IOM uint32_t DMA2_INT_REG
Definition: DA1459x-00.h:530
UART2_Type::UART2_UCV_REG
__IOM uint32_t UART2_UCV_REG
Definition: DA1459x-00.h:1350
RFDIAG_IRQn
Definition: DA1459x-00.h:113
DCDC_Type::DCDC_CTRL_REG
__IOM uint32_t DCDC_CTRL_REG
Definition: DA1459x-00.h:499
SRC2_Type::SRC2_COEF76_SET1_REG
__IOM uint32_t SRC2_COEF76_SET1_REG
Definition: DA1459x-00.h:1077
DMA_Type::DMA3_B_START_REG
__IOM uint32_t DMA3_B_START_REG
Definition: DA1459x-00.h:536
I2C_Type::I2C_ENABLE_STATUS_REG
__IOM uint32_t I2C_ENABLE_STATUS_REG
Definition: DA1459x-00.h:773
UART_Type::UART_HTX_REG
__IOM uint32_t UART_HTX_REG
Definition: DA1459x-00.h:1279
DMA_Type::DMA3_IDX_REG
__IOM uint32_t DMA3_IDX_REG
Definition: DA1459x-00.h:540
UART_Type::UART_USR_REG
__IOM uint32_t UART_USR_REG
Definition: DA1459x-00.h:1269
CRG_AUD_Type::PCM_DIV_REG
__IOM uint32_t PCM_DIV_REG
Definition: DA1459x-00.h:335
CRG_COM_Type::RESERVED
__IM uint32_t RESERVED
Definition: DA1459x-00.h:353
SRC1_Type::SRC1_MUX_REG
__IOM uint32_t SRC1_MUX_REG
Definition: DA1459x-00.h:1045
QSPIC_Type::QSPIC_ERASECMDB_REG
__IOM uint32_t QSPIC_ERASECMDB_REG
Definition: DA1459x-00.h:911
I2C_Type::I2C_INTR_MASK_REG
__IOM uint32_t I2C_INTR_MASK_REG
Definition: DA1459x-00.h:746
AES_HASH_Type::CRYPTO_STATUS_REG
__IOM uint32_t CRYPTO_STATUS_REG
Definition: DA1459x-00.h:181
DMA_Type::DMA_CLEAR_INT_REG
__IOM uint32_t DMA_CLEAR_INT_REG
Definition: DA1459x-00.h:558
RTC_Type::RTC_EVENT_FLAGS_REG
__IOM uint32_t RTC_EVENT_FLAGS_REG
Definition: DA1459x-00.h:963
QSPIC_Type::QSPIC_STATUS_REG
__IOM uint32_t QSPIC_STATUS_REG
Definition: DA1459x-00.h:904
SRC2_Type::SRC2_OUT1_REG
__IOM uint32_t SRC2_OUT1_REG
Definition: DA1459x-00.h:1071
RTC_Type::RTC_TIME_ALARM_REG
__IOM uint32_t RTC_TIME_ALARM_REG
Definition: DA1459x-00.h:960
TIMER_Type::TIMER_CAPTURE_GPIO4_REG
__IOM uint32_t TIMER_CAPTURE_GPIO4_REG
Definition: DA1459x-00.h:1143
GPIO_Type::P1_13_MODE_REG
__IOM uint32_t P1_13_MODE_REG
Definition: DA1459x-00.h:691
UART_IRQn
Definition: DA1459x-00.h:86
CACHE_Type::CACHE_MRM_HITS_REG
__IOM uint32_t CACHE_MRM_HITS_REG
Definition: DA1459x-00.h:227
GPADC_Type::GP_ADC_OFFP_REG
__IOM uint32_t GP_ADC_OFFP_REG
Definition: DA1459x-00.h:637
UART_Type::UART_SRBR_STHR8_REG
__IOM uint32_t UART_SRBR_STHR8_REG
Definition: DA1459x-00.h:1260
TIMER2_Type::TIMER2_SETTINGS_REG
__IOM uint32_t TIMER2_SETTINGS_REG
Definition: DA1459x-00.h:1165
CRG_TOP_Type::RESET_STAT_REG
__IOM uint32_t RESET_STAT_REG
Definition: DA1459x-00.h:438
CRG_TOP_Type::POR_TIMER_REG
__IOM uint32_t POR_TIMER_REG
Definition: DA1459x-00.h:434
MEMCTRL_Type::CMI_CODE_BASE_REG
__IOM uint32_t CMI_CODE_BASE_REG
Definition: DA1459x-00.h:823
PDC_Type::PDC_PENDING_CMAC_REG
__IOM uint32_t PDC_PENDING_CMAC_REG
Definition: DA1459x-00.h:880
UART2_Type::UART2_SRR_REG
__IOM uint32_t UART2_SRR_REG
Definition: DA1459x-00.h:1330
UART_Type
UART registers (UART)
Definition: DA1459x-00.h:1241
SRC1_Type::SRC1_COEF76_SET1_REG
__IOM uint32_t SRC1_COEF76_SET1_REG
Definition: DA1459x-00.h:1049
SVCall_IRQn
Definition: DA1459x-00.h:78
CMAC_CACHE_Type::CM_CACHE_EFLASH_REG
__IOM uint32_t CM_CACHE_EFLASH_REG
Definition: DA1459x-00.h:310
I2C_Type::I2C_INTR_STAT_REG
__IOM uint32_t I2C_INTR_STAT_REG
Definition: DA1459x-00.h:745
AES_HASH_Type
AES_HASH registers (AES_HASH)
Definition: DA1459x-00.h:175
SDADC_IRQn
Definition: DA1459x-00.h:110
WAKEUP_Type::WKUP_STATUS_P1_REG
__IOM uint32_t WKUP_STATUS_P1_REG
Definition: DA1459x-00.h:1379
GPIO_Type::P0_00_MODE_REG
__IOM uint32_t P0_00_MODE_REG
Definition: DA1459x-00.h:662
GPADC_Type::GP_ADC_CTRL_REG
__IOM uint32_t GP_ADC_CTRL_REG
Definition: DA1459x-00.h:633
SPI_Type::SPI_TXBUFFER_FORCE_REG
__IOM uint32_t SPI_TXBUFFER_FORCE_REG
Definition: DA1459x-00.h:1023
CRG_TOP_Type::CLK_RADIO_REG
__IOM uint32_t CLK_RADIO_REG
Definition: DA1459x-00.h:411
SPI_Type::SPI_CONFIG_REG
__IOM uint32_t SPI_CONFIG_REG
Definition: DA1459x-00.h:1013
TIMER4_Type::TIMER4_SETTINGS_REG
__IOM uint32_t TIMER4_SETTINGS_REG
Definition: DA1459x-00.h:1220
CRG_PER_Type
CRG_PER registers (CRG_PER)
Definition: DA1459x-00.h:372
CRG_TOP_Type::P1_PAD_LATCH_REG
__IOM uint32_t P1_PAD_LATCH_REG
Definition: DA1459x-00.h:429
SDADC_Type::SDADC_PGA_CTRL_REG
__IOM uint32_t SDADC_PGA_CTRL_REG
Definition: DA1459x-00.h:991
UART_Type::UART_RFL_REG
__IOM uint32_t UART_RFL_REG
Definition: DA1459x-00.h:1271
I2C_Type::I2C_DMA_RDLR_REG
__IOM uint32_t I2C_DMA_RDLR_REG
Definition: DA1459x-00.h:770
SRC2_Type::SRC2_COEF32_SET1_REG
__IOM uint32_t SRC2_COEF32_SET1_REG
Definition: DA1459x-00.h:1075
GPADC_Type
GPADC registers (GPADC)
Definition: DA1459x-00.h:632
DMA_Type::DMA4_B_START_REG
__IOM uint32_t DMA4_B_START_REG
Definition: DA1459x-00.h:543
SPI_Type::SPI_CLOCK_REG
__IOM uint32_t SPI_CLOCK_REG
Definition: DA1459x-00.h:1014
RTC_Type::RTC_STATUS_REG
__IOM uint32_t RTC_STATUS_REG
Definition: DA1459x-00.h:967
I2C_Type::I2C_FS_SCL_LCNT_REG
__IOM uint32_t I2C_FS_SCL_LCNT_REG
Definition: DA1459x-00.h:742
DMA_Type::DMA2_LEN_REG
__IOM uint32_t DMA2_LEN_REG
Definition: DA1459x-00.h:531
UART_Type::UART_SRBR_STHR9_REG
__IOM uint32_t UART_SRBR_STHR9_REG
Definition: DA1459x-00.h:1261
CRG_TOP_Type::SYS_CTRL_REG
__IOM uint32_t SYS_CTRL_REG
Definition: DA1459x-00.h:416
UART2_Type::UART2_SDMAM_REG
__IOM uint32_t UART2_SDMAM_REG
Definition: DA1459x-00.h:1333
SYS_WDOG_Type::WATCHDOG_CTRL_REG
__IOM uint32_t WATCHDOG_CTRL_REG
Definition: DA1459x-00.h:1095
FCU_Type::FLASH_PTERASE_REG
__IOM uint32_t FLASH_PTERASE_REG
Definition: DA1459x-00.h:613
GPIO_Type::P0_14_MODE_REG
__IOM uint32_t P0_14_MODE_REG
Definition: DA1459x-00.h:676
CRG_PER_Type::SET_CLK_PER_REG
__IOM uint32_t SET_CLK_PER_REG
Definition: DA1459x-00.h:375
UART2_Type::UART2_IRQ_STATUS_REG
__IOM uint32_t UART2_IRQ_STATUS_REG
Definition: DA1459x-00.h:1348
SRC_OUT_IRQn
Definition: DA1459x-00.h:93
PCM1_Type::PCM1_OUT2_REG
__IOM uint32_t PCM1_OUT2_REG
Definition: DA1459x-00.h:848
MEMCTRL_Type::MEM_PRIO_REG
__IOM uint32_t MEM_PRIO_REG
Definition: DA1459x-00.h:818
CRG_TOP_Type::SECURE_BOOT_REG
__IOM uint32_t SECURE_BOOT_REG
Definition: DA1459x-00.h:441
I2C_Type
I2C registers (I2C)
Definition: DA1459x-00.h:733
PCM1_Type::PCM1_CTRL_REG
__IOM uint32_t PCM1_CTRL_REG
Definition: DA1459x-00.h:844
MDCT_Type::MDCT_YBASE_ADDR_REG
__IOM uint32_t MDCT_YBASE_ADDR_REG
Definition: DA1459x-00.h:792
TIMER4_Type::TIMER4_GPIO1_CONF_REG
__IOM uint32_t TIMER4_GPIO1_CONF_REG
Definition: DA1459x-00.h:1218
CRG_AUD_Type::PDM_DIV_REG
__IOM uint32_t PDM_DIV_REG
Definition: DA1459x-00.h:337
UART2_Type::UART2_DMASA_REG
__IOM uint32_t UART2_DMASA_REG
Definition: DA1459x-00.h:1338
UART_Type::UART_SRBR_STHR1_REG
__IOM uint32_t UART_SRBR_STHR1_REG
Definition: DA1459x-00.h:1253
UART2_Type::UART2_LSR_REG
__IOM uint32_t UART2_LSR_REG
Definition: DA1459x-00.h:1306
DebugMonitor_IRQn
Definition: DA1459x-00.h:79
GPIO_Type::P1_14_MODE_REG
__IOM uint32_t P1_14_MODE_REG
Definition: DA1459x-00.h:692
MDCT_Type::MDCT_STAGE0_REG
__IOM uint32_t MDCT_STAGE0_REG
Definition: DA1459x-00.h:794
SRC2_Type
SRC2 registers (SRC2)
Definition: DA1459x-00.h:1065
I2C_Type::I2C_TAR_REG
__IOM uint32_t I2C_TAR_REG
Definition: DA1459x-00.h:735
TIMER_Type::TIMER_CLEAR_GPIO_EVENT_REG
__IOM uint32_t TIMER_CLEAR_GPIO_EVENT_REG
Definition: DA1459x-00.h:1144
CRG_TOP_Type::BOD_CTRL_REG
__IOM uint32_t BOD_CTRL_REG
Definition: DA1459x-00.h:443
DMA_Type::DMA0_LEN_REG
__IOM uint32_t DMA0_LEN_REG
Definition: DA1459x-00.h:517
GPIO_P1_IRQn
Definition: DA1459x-00.h:118
GPIO_Type::P1_06_MODE_REG
__IOM uint32_t P1_06_MODE_REG
Definition: DA1459x-00.h:684
GPIO_Type::P0_07_MODE_REG
__IOM uint32_t P0_07_MODE_REG
Definition: DA1459x-00.h:669
UART2_Type::UART2_MCR_REG
__IOM uint32_t UART2_MCR_REG
Definition: DA1459x-00.h:1305
TIMER3_Type::TIMER3_CAPTURE_GPIO2_REG
__IOM uint32_t TIMER3_CAPTURE_GPIO2_REG
Definition: DA1459x-00.h:1196
PendSV_IRQn
Definition: DA1459x-00.h:80
TIMER4_Type::TIMER4_CLEAR_IRQ_REG
__IOM uint32_t TIMER4_CLEAR_IRQ_REG
Definition: DA1459x-00.h:1227
UART2_Type::UART2_RAR_REG
__IOM uint32_t UART2_RAR_REG
Definition: DA1459x-00.h:1341
QSPIC_Type::QSPIC_STATUSCMD_REG
__IOM uint32_t QSPIC_STATUSCMD_REG
Definition: DA1459x-00.h:914
PCM1_Type
PCM1 registers (PCM1)
Definition: DA1459x-00.h:843
CRG_XTAL_Type::XTAL32M_IRQ_CTRL_REG
__IOM uint32_t XTAL32M_IRQ_CTRL_REG
Definition: DA1459x-00.h:475
CRG_TOP_Type::CLK_RCX_REG
__IOM uint32_t CLK_RCX_REG
Definition: DA1459x-00.h:422
WAKEUP_Type::WKUP_POL_P0_REG
__IOM uint32_t WKUP_POL_P0_REG
Definition: DA1459x-00.h:1375
WAKEUP_Type::WKUP_CLEAR_P0_REG
__IOM uint32_t WKUP_CLEAR_P0_REG
Definition: DA1459x-00.h:1381
UART2_Type::UART2_SRBR_STHR14_REG
__IOM uint32_t UART2_SRBR_STHR14_REG
Definition: DA1459x-00.h:1324
TIMER3_Type::TIMER3_STATUS_REG
__IOM uint32_t TIMER3_STATUS_REG
Definition: DA1459x-00.h:1190
QSPIC_Type::QSPIC_CTRLBUS_REG
__IOM uint32_t QSPIC_CTRLBUS_REG
Definition: DA1459x-00.h:897
GPIO_Type::P1_11_MODE_REG
__IOM uint32_t P1_11_MODE_REG
Definition: DA1459x-00.h:689
MDCT_Type::MDCT_STAGE6_REG
__IOM uint32_t MDCT_STAGE6_REG
Definition: DA1459x-00.h:800
I2C_Type::I2C_FS_SCL_HCNT_REG
__IOM uint32_t I2C_FS_SCL_HCNT_REG
Definition: DA1459x-00.h:741
I2C_Type::I2C_CLR_START_DET_REG
__IOM uint32_t I2C_CLR_START_DET_REG
Definition: DA1459x-00.h:759
ANAMISC_BIF_Type::CLK_REF_SEL_REG
__IOM uint32_t CLK_REF_SEL_REG
Definition: DA1459x-00.h:205
__IM
#define __IM
Definition: core_cm0.h:172
DMA_Type::DMA5_LEN_REG
__IOM uint32_t DMA5_LEN_REG
Definition: DA1459x-00.h:552
UART_Type::UART_CTR_REG
__IOM uint32_t UART_CTR_REG
Definition: DA1459x-00.h:1285
WAKEUP_Type::WKUP_RESET_IRQ_REG
__IOM uint32_t WKUP_RESET_IRQ_REG
Definition: DA1459x-00.h:1368
CMAC_CACHE_Type::CM_CACHE_MRM_HITS_REG
__IOM uint32_t CM_CACHE_MRM_HITS_REG
Definition: DA1459x-00.h:294
DW_Type::AHB_DMA_WTEN_REG
__IOM uint32_t AHB_DMA_WTEN_REG
Definition: DA1459x-00.h:586
UART2_Type::UART2_SRBR_STHR0_REG
__IOM uint32_t UART2_SRBR_STHR0_REG
Definition: DA1459x-00.h:1310
UART2_Type::UART2_USR_REG
__IOM uint32_t UART2_USR_REG
Definition: DA1459x-00.h:1327
GPIO_Type::P0_10_MODE_REG
__IOM uint32_t P0_10_MODE_REG
Definition: DA1459x-00.h:672
I2C_Type::I2C_DMA_TDLR_REG
__IOM uint32_t I2C_DMA_TDLR_REG
Definition: DA1459x-00.h:769
DMA_Type::DMA0_CTRL_REG
__IOM uint32_t DMA0_CTRL_REG
Definition: DA1459x-00.h:518
TIMER4_Type
TIMER4 registers (TIMER4)
Definition: DA1459x-00.h:1214
TIMER_Type
TIMER registers (TIMER)
Definition: DA1459x-00.h:1126
PDC_Type::PDC_CTRL5_REG
__IOM uint32_t PDC_CTRL5_REG
Definition: DA1459x-00.h:868
BusFault_IRQn
Definition: DA1459x-00.h:74
DMA_Type::DMA4_INT_REG
__IOM uint32_t DMA4_INT_REG
Definition: DA1459x-00.h:544
GPADC_Type::GP_ADC_CTRL2_REG
__IOM uint32_t GP_ADC_CTRL2_REG
Definition: DA1459x-00.h:634
GPIO_Type::P1_15_MODE_REG
__IOM uint32_t P1_15_MODE_REG
Definition: DA1459x-00.h:693
PCM1_Type::PCM1_OUT1_REG
__IOM uint32_t PCM1_OUT1_REG
Definition: DA1459x-00.h:847
UART_Type::UART_SDMAM_REG
__IOM uint32_t UART_SDMAM_REG
Definition: DA1459x-00.h:1275
TIMER_Type::TIMER_STATUS_REG
__IOM uint32_t TIMER_STATUS_REG
Definition: DA1459x-00.h:1129
I2C_Type::I2C_CLR_GEN_CALL_REG
__IOM uint32_t I2C_CLR_GEN_CALL_REG
Definition: DA1459x-00.h:760
SRC2_Type::SRC2_IN2_REG
__IOM uint32_t SRC2_IN2_REG
Definition: DA1459x-00.h:1070
PDC_Type::PDC_SET_PENDING_REG
__IOM uint32_t PDC_SET_PENDING_REG
Definition: DA1459x-00.h:881
UART2_IRQn
Definition: DA1459x-00.h:87
GPIO_Type::P1_02_MODE_REG
__IOM uint32_t P1_02_MODE_REG
Definition: DA1459x-00.h:680
AES_HASH_Type::CRYPTO_DEST_ADDR_REG
__IOM uint32_t CRYPTO_DEST_ADDR_REG
Definition: DA1459x-00.h:180
MEMCTRL_Type::CMI_DATA_BASE_REG
__IOM uint32_t CMI_DATA_BASE_REG
Definition: DA1459x-00.h:824
CRG_COM_Type
CRG_COM registers (CRG_COM)
Definition: DA1459x-00.h:352
QSPIC_Type::QSPIC_WRITEDATA_REG
__IOM uint32_t QSPIC_WRITEDATA_REG
Definition: DA1459x-00.h:905
UART_Type::UART_SRBR_STHR14_REG
__IOM uint32_t UART_SRBR_STHR14_REG
Definition: DA1459x-00.h:1266
CRG_TOP_Type::CLK_CTRL_REG
__IOM uint32_t CLK_CTRL_REG
Definition: DA1459x-00.h:412
GPIO_Type
GPIO registers (GPIO)
Definition: DA1459x-00.h:655
SPI_Type::SPI_CTRL_REG
__IOM uint32_t SPI_CTRL_REG
Definition: DA1459x-00.h:1012
RTC_Type::RTC_CONTROL_REG
__IOM uint32_t RTC_CONTROL_REG
Definition: DA1459x-00.h:956
MEMCTRL_Type::MEM_STALL_REG
__IOM uint32_t MEM_STALL_REG
Definition: DA1459x-00.h:819
ANAMISC_BIF_Type
ANAMISC_BIF registers (ANAMISC_BIF)
Definition: DA1459x-00.h:203
UART2_Type::UART2_SRBR_STHR4_REG
__IOM uint32_t UART2_SRBR_STHR4_REG
Definition: DA1459x-00.h:1314
DMA_Type::DMA5_CTRL_REG
__IOM uint32_t DMA5_CTRL_REG
Definition: DA1459x-00.h:553
AES_HASH_Type::CRYPTO_MREG0_REG
__IOM uint32_t CRYPTO_MREG0_REG
Definition: DA1459x-00.h:183
UART_Type::UART_RBR_THR_DLL_REG
__IOM uint32_t UART_RBR_THR_DLL_REG
Definition: DA1459x-00.h:1242
CACHE_Type::CACHE_MRM_TINT_REG
__IOM uint32_t CACHE_MRM_TINT_REG
Definition: DA1459x-00.h:233
QUADEC_Type::QDEC_CTRL_REG
__IOM uint32_t QDEC_CTRL_REG
Definition: DA1459x-00.h:935
DW_Type::AHB_DMA_DFLT_MASTER_REG
__IOM uint32_t AHB_DMA_DFLT_MASTER_REG
Definition: DA1459x-00.h:585
CRG_TOP_Type::CLK_TMR_REG
__IOM uint32_t CLK_TMR_REG
Definition: DA1459x-00.h:413
CRG_TOP_Type::BANDGAP_REG
__IOM uint32_t BANDGAP_REG
Definition: DA1459x-00.h:424
GPIO_Type::P0_03_MODE_REG
__IOM uint32_t P0_03_MODE_REG
Definition: DA1459x-00.h:665
SRC1_Type::SRC1_COEF32_SET1_REG
__IOM uint32_t SRC1_COEF32_SET1_REG
Definition: DA1459x-00.h:1047
PDC_Type::PDC_CTRL9_REG
__IOM uint32_t PDC_CTRL9_REG
Definition: DA1459x-00.h:872
DMA_Type::DMA_INT_MASK_REG
__IOM uint32_t DMA_INT_MASK_REG
Definition: DA1459x-00.h:559
CRG_TOP_Type::STARTUP_STATUS_REG
__IOM uint32_t STARTUP_STATUS_REG
Definition: DA1459x-00.h:454
AES_HASH_Type::CRYPTO_CTRL_REG
__IOM uint32_t CRYPTO_CTRL_REG
Definition: DA1459x-00.h:176
CRG_COM_Type::CLK_COM_REG
__IOM uint32_t CLK_COM_REG
Definition: DA1459x-00.h:354
MDCT_Type::MDCT_XBASE_ADDR_REG
__IOM uint32_t MDCT_XBASE_ADDR_REG
Definition: DA1459x-00.h:791
CRG_TOP_Type::BIAS_VREF_SEL_REG
__IOM uint32_t BIAS_VREF_SEL_REG
Definition: DA1459x-00.h:436
UART2_Type::UART2_DLF_REG
__IOM uint32_t UART2_DLF_REG
Definition: DA1459x-00.h:1340
CMAC_CACHE_Type::CM_CACHE_FLASH_REG
__IOM uint32_t CM_CACHE_FLASH_REG
Definition: DA1459x-00.h:306
MRM_IRQn
Definition: DA1459x-00.h:102
core_cm33.h
CMSIS Cortex-M33 Core Peripheral Access Layer Header File.
RTC_Type::RTC_PDC_EVENT_CLEAR_REG
__IOM uint32_t RTC_PDC_EVENT_CLEAR_REG
Definition: DA1459x-00.h:973
CRG_TOP_Type::PMU_SLEEP_REG
__IOM uint32_t PMU_SLEEP_REG
Definition: DA1459x-00.h:452
GPIO_Type::P0_WEAK_CTRL_REG
__IOM uint32_t P0_WEAK_CTRL_REG
Definition: DA1459x-00.h:696
I2C_Type::I2C_TX_TL_REG
__IOM uint32_t I2C_TX_TL_REG
Definition: DA1459x-00.h:749
CRG_COM_Type::SET_CLK_COM_REG
__IOM uint32_t SET_CLK_COM_REG
Definition: DA1459x-00.h:355
QSPIC_Type::QSPIC_RECVDATA_REG
__IOM uint32_t QSPIC_RECVDATA_REG
Definition: DA1459x-00.h:899
UART_Type::UART_SRBR_STHR13_REG
__IOM uint32_t UART_SRBR_STHR13_REG
Definition: DA1459x-00.h:1265
SRC1_Type::SRC1_COEF54_SET1_REG
__IOM uint32_t SRC1_COEF54_SET1_REG
Definition: DA1459x-00.h:1048
TIMER_Type::TIMER_PWM_CTRL_REG
__IOM uint32_t TIMER_PWM_CTRL_REG
Definition: DA1459x-00.h:1138
QUADEC_Type::QDEC_CTRL2_REG
__IOM uint32_t QDEC_CTRL2_REG
Definition: DA1459x-00.h:939
DMA_Type::DMA4_A_START_REG
__IOM uint32_t DMA4_A_START_REG
Definition: DA1459x-00.h:542
SRC_IN_IRQn
Definition: DA1459x-00.h:92
DMA_Type::DMA0_IDX_REG
__IOM uint32_t DMA0_IDX_REG
Definition: DA1459x-00.h:519
CRG_PER_Type::RESET_CLK_PER_REG
__IOM uint32_t RESET_CLK_PER_REG
Definition: DA1459x-00.h:377
SPI_Type::SPI_FIFO_WRITE_REG
__IOM uint32_t SPI_FIFO_WRITE_REG
Definition: DA1459x-00.h:1020
SRC2_Type::SRC2_OUT2_REG
__IOM uint32_t SRC2_OUT2_REG
Definition: DA1459x-00.h:1072
PDC_Type::PDC_CTRL4_REG
__IOM uint32_t PDC_CTRL4_REG
Definition: DA1459x-00.h:867
CRG_TOP_Type::SYS_STAT_REG
__IOM uint32_t SYS_STAT_REG
Definition: DA1459x-00.h:417
DCDC_Type
DCDC registers (DCDC)
Definition: DA1459x-00.h:498
DW_Type::AHB_DMA_PL1_REG
__IOM uint32_t AHB_DMA_PL1_REG
Definition: DA1459x-00.h:576
CRG_XTAL_Type::XTAL32M_START_REG
__IOM uint32_t XTAL32M_START_REG
Definition: DA1459x-00.h:469
CHIP_VERSION_Type::CHIP_REVISION_REG
__IOM uint32_t CHIP_REVISION_REG
Definition: DA1459x-00.h:272
UART_Type::UART_LCR_REG
__IOM uint32_t UART_LCR_REG
Definition: DA1459x-00.h:1246
UART2_Type::UART2_CONFIG_REG
__IOM uint32_t UART2_CONFIG_REG
Definition: DA1459x-00.h:1308
UART2_Type
UART2 registers (UART2)
Definition: DA1459x-00.h:1299
CRG_TOP_Type::DISCHARGE_RAIL_REG
__IOM uint32_t DISCHARGE_RAIL_REG
Definition: DA1459x-00.h:444
CRG_TOP_Type::PMU_CTRL_REG
__IOM uint32_t PMU_CTRL_REG
Definition: DA1459x-00.h:415
QSPIC_Type::QSPIC_BURSTBRK_REG
__IOM uint32_t QSPIC_BURSTBRK_REG
Definition: DA1459x-00.h:913
I2C_Type::I2C_CLR_STOP_DET_REG
__IOM uint32_t I2C_CLR_STOP_DET_REG
Definition: DA1459x-00.h:758
CMAC_CACHE_Type::CM_CACHE_MRM_MISSES_REG
__IOM uint32_t CM_CACHE_MRM_MISSES_REG
Definition: DA1459x-00.h:296
TIMER3_Type::TIMER3_CAPTURE_GPIO1_REG
__IOM uint32_t TIMER3_CAPTURE_GPIO1_REG
Definition: DA1459x-00.h:1195
I2C_Type::I2C_CLR_RX_UNDER_REG
__IOM uint32_t I2C_CLR_RX_UNDER_REG
Definition: DA1459x-00.h:751
CHIP_VERSION_Type::CHIP_ID3_REG
__IOM uint32_t CHIP_ID3_REG
Definition: DA1459x-00.h:269
QUADEC_Type::QDEC_YCNT_REG
__IOM uint32_t QDEC_YCNT_REG
Definition: DA1459x-00.h:937
SysTick_IRQn
Definition: DA1459x-00.h:81
MDCT_Type::MDCT_STAGE2_REG
__IOM uint32_t MDCT_STAGE2_REG
Definition: DA1459x-00.h:796
SRC2_OUT_IRQn
Definition: DA1459x-00.h:95
PCM1_Type::PCM1_IN2_REG
__IOM uint32_t PCM1_IN2_REG
Definition: DA1459x-00.h:846
UART_Type::UART_TFL_REG
__IOM uint32_t UART_TFL_REG
Definition: DA1459x-00.h:1270
UART2_Type::UART2_TIMER_REG
__IOM uint32_t UART2_TIMER_REG
Definition: DA1459x-00.h:1346
UART2_Type::UART2_SFE_REG
__IOM uint32_t UART2_SFE_REG
Definition: DA1459x-00.h:1334
GPIO_Type::P1_07_MODE_REG
__IOM uint32_t P1_07_MODE_REG
Definition: DA1459x-00.h:685
FCU_Type::FLASH_PTWK_SP_REG
__IOM uint32_t FLASH_PTWK_SP_REG
Definition: DA1459x-00.h:615
PCM_IRQn
Definition: DA1459x-00.h:91
PDC_M33_IRQn
Definition: DA1459x-00.h:101
CHIP_VERSION_Type::CHIP_ID2_REG
__IOM uint32_t CHIP_ID2_REG
Definition: DA1459x-00.h:268
WAKEUP_Type::WKUP_SELECT_P1_REG
__IOM uint32_t WKUP_SELECT_P1_REG
Definition: DA1459x-00.h:1372
TIMER2_Type::TIMER2_GPIO1_CONF_REG
__IOM uint32_t TIMER2_GPIO1_CONF_REG
Definition: DA1459x-00.h:1163
TIMER4_Type::TIMER4_CAPTURE_GPIO2_REG
__IOM uint32_t TIMER4_CAPTURE_GPIO2_REG
Definition: DA1459x-00.h:1223
UART2_Type::UART2_CTR_REG
__IOM uint32_t UART2_CTR_REG
Definition: DA1459x-00.h:1351
CRG_TOP_Type::CLK_SWITCH2XTAL_REG
__IOM uint32_t CLK_SWITCH2XTAL_REG
Definition: DA1459x-00.h:414
GPIO_Type::P1_12_MODE_REG
__IOM uint32_t P1_12_MODE_REG
Definition: DA1459x-00.h:690
TIMER2_Type::TIMER2_CTRL_REG
__IOM uint32_t TIMER2_CTRL_REG
Definition: DA1459x-00.h:1160
UART_Type::UART_SFE_REG
__IOM uint32_t UART_SFE_REG
Definition: DA1459x-00.h:1276
WAKEUP_Type::WKUP_SELECT_P0_REG
__IOM uint32_t WKUP_SELECT_P0_REG
Definition: DA1459x-00.h:1370
CRG_TOP_Type::P0_SET_PAD_LATCH_REG
__IOM uint32_t P0_SET_PAD_LATCH_REG
Definition: DA1459x-00.h:427
QSPIC_Type::QSPIC_CTRLMODE_REG
__IOM uint32_t QSPIC_CTRLMODE_REG
Definition: DA1459x-00.h:898
UART_Type::UART_SRBR_STHR12_REG
__IOM uint32_t UART_SRBR_STHR12_REG
Definition: DA1459x-00.h:1264
CRG_XTAL_Type::CLKDBLR_STATUS_REG
__IOM uint32_t CLKDBLR_STATUS_REG
Definition: DA1459x-00.h:484
MEMCTRL_Type::BUSY_STAT_REG
__IOM uint32_t BUSY_STAT_REG
Definition: DA1459x-00.h:829
GPIO_Type::P0_11_MODE_REG
__IOM uint32_t P0_11_MODE_REG
Definition: DA1459x-00.h:673
TIMER4_Type::TIMER4_GPIO2_CONF_REG
__IOM uint32_t TIMER4_GPIO2_CONF_REG
Definition: DA1459x-00.h:1219
RTC_Type::RTC_CALENDAR_REG
__IOM uint32_t RTC_CALENDAR_REG
Definition: DA1459x-00.h:959
CMAC_CACHE_Type::CM_CACHE_MRM_HITS1WS_REG
__IOM uint32_t CM_CACHE_MRM_HITS1WS_REG
Definition: DA1459x-00.h:314
TIMER2_Type::TIMER2_CLEAR_IRQ_REG
__IOM uint32_t TIMER2_CLEAR_IRQ_REG
Definition: DA1459x-00.h:1173
GPIO_Type::P0_05_MODE_REG
__IOM uint32_t P0_05_MODE_REG
Definition: DA1459x-00.h:667
DMA_Type::DMA_INT_STATUS_REG
__IOM uint32_t DMA_INT_STATUS_REG
Definition: DA1459x-00.h:557
CRG_TOP_Type::P1_SET_PAD_LATCH_REG
__IOM uint32_t P1_SET_PAD_LATCH_REG
Definition: DA1459x-00.h:430
TIMER3_Type::TIMER3_CTRL_REG
__IOM uint32_t TIMER3_CTRL_REG
Definition: DA1459x-00.h:1188
TIMER2_Type::TIMER2_PWM_CTRL_REG
__IOM uint32_t TIMER2_PWM_CTRL_REG
Definition: DA1459x-00.h:1171
SYSB_Type::FLASH_ARB_REG
__IOM uint32_t FLASH_ARB_REG
Definition: DA1459x-00.h:1112
QSPIC_Type::QSPIC_READDATA_REG
__IOM uint32_t QSPIC_READDATA_REG
Definition: DA1459x-00.h:906
MEMCTRL_Type::MEM_STATUS_REG
__IOM uint32_t MEM_STATUS_REG
Definition: DA1459x-00.h:820
I2C_Type::I2C_RXFLR_REG
__IOM uint32_t I2C_RXFLR_REG
Definition: DA1459x-00.h:764
CRG_TOP_Type::RAM_PWR_CTRL_REG
__IOM uint32_t RAM_PWR_CTRL_REG
Definition: DA1459x-00.h:439
GPIO_Type::P1_10_MODE_REG
__IOM uint32_t P1_10_MODE_REG
Definition: DA1459x-00.h:688
FCU_IRQn
Definition: DA1459x-00.h:90
I2C_Type::I2C_TX_ABRT_SOURCE_REG
__IOM uint32_t I2C_TX_ABRT_SOURCE_REG
Definition: DA1459x-00.h:766
UART_Type::UART_SRBR_STHR0_REG
__IOM uint32_t UART_SRBR_STHR0_REG
Definition: DA1459x-00.h:1252
MDCT_Type::MDCT_PHASE_INC_REG
__IOM uint32_t MDCT_PHASE_INC_REG
Definition: DA1459x-00.h:802
DMA_Type::DMA5_B_START_REG
__IOM uint32_t DMA5_B_START_REG
Definition: DA1459x-00.h:550
TIMER_Type::TIMER_CTRL_REG
__IOM uint32_t TIMER_CTRL_REG
Definition: DA1459x-00.h:1127
UART2_Type::UART2_SRTS_REG
__IOM uint32_t UART2_SRTS_REG
Definition: DA1459x-00.h:1331
PDC_Type::PDC_CTRL11_REG
__IOM uint32_t PDC_CTRL11_REG
Definition: DA1459x-00.h:874
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