hw_qspi_read_status_instr_config_t Struct Reference

QSPIC read status instruction configuration structure (auto access mode) More...

#include <hw_qspi_v2.h>

Data Fields
HW_QSPI_BUS_MODE	opcode_bus_mode: 2
HW_QSPI_BUS_MODE	receive_bus_mode: 2
HW_QSPI_BUSY_LEVEL	busy_level: 1
uint32_t	busy_pos: 3
uint8_t	opcode
uint16_t	delay_nsec

Detailed Description

QSPIC read status instruction configuration structure (auto access mode)

Field Documentation

busy_level

HW_QSPI_BUSY_LEVEL hw_qspi_read_status_instr_config_t::busy_level

Busy bit level

busy_pos

uint32_t hw_qspi_read_status_instr_config_t::busy_pos

The position of the Busy bit in the status register (0 - 7)

delay_nsec

uint16_t hw_qspi_read_status_instr_config_t::delay_nsec

The minimum delay in nsec between a Read Status command and the previous Erase command. Usually NOT needed thus is set equal to 0.

opcode

uint8_t hw_qspi_read_status_instr_config_t::opcode

Read Status command opcode

opcode_bus_mode

HW_QSPI_BUS_MODE hw_qspi_read_status_instr_config_t::opcode_bus_mode

The bus mode of the opcode phase

receive_bus_mode

HW_QSPI_BUS_MODE hw_qspi_read_status_instr_config_t::receive_bus_mode

The bus mode of the receive data phase

---

The documentation for this struct was generated from the following file:

• sdk/bsp/peripherals/include/hw_qspi_v2.h