Peripheral Device Register Mask Positioning. More...

Macros
#define	AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL)

#define	AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (16UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x10000UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (15UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x8000UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0x7c00UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL)

#define	AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL)

#define	AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL)

#define	AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL)

#define	AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL)

#define	AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL)

#define	AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL)

#define	AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL)

#define	AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL)

#define	AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL)

#define	AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL)

#define	AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL)

#define	AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL)

#define	AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL)

#define	AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL)

#define	AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL)

#define	AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL)

#define	AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL)

#define	AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL)

#define	AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL)

#define	ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Pos (2UL)

#define	ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Msk (0x4UL)

#define	ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Pos (1UL)

#define	ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Msk (0x2UL)

#define	ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Pos (0UL)

#define	ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Msk (0x1UL)

#define	ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL)

#define	ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL)

#define	ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL)

#define	ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL)

#define	ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_READY_Pos (28UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_READY_Msk (0x10000000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (27UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x8000000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos (17UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk (0x3fe0000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (16UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x10000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (14UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0xc000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (13UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x2000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (12UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x1000UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)

#define	CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)

#define	CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos (16UL)

#define	CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk (0xffff0000UL)

#define	CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos (4UL)

#define	CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk (0xfff0UL)

#define	CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos (0UL)

#define	CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk (0x7UL)

#define	CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)

#define	CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)

#define	CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)

#define	CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)

#define	CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)

#define	CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)

#define	CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)

#define	CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL)

#define	CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL)

#define	CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)

#define	CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)

#define	CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)

#define	CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL)

#define	CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)

#define	CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)

#define	CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL)

#define	CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL)

#define	CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)

#define	CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)

#define	CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)

#define	CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)

#define	CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL)

#define	CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL)

#define	CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL)

#define	CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL)

#define	CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL)

#define	CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL)

#define	CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL)

#define	CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL)

#define	CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL)

#define	CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL)

#define	CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL)

#define	CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL)

#define	CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL)

#define	CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL)

#define	CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL)

#define	CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Pos (28UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Msk (0x10000000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (27UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x8000000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos (17UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk (0x3fe0000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (16UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x10000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (14UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0xc000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (13UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x2000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (12UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x1000UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)

#define	CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos (16UL)

#define	CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk (0xffff0000UL)

#define	CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos (4UL)

#define	CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk (0xfff0UL)

#define	CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk (0x7UL)

#define	CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)

#define	CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)

#define	CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)

#define	CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)

#define	CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)

#define	CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL)

#define	CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)

#define	CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL)

#define	CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)

#define	CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL)

#define	CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)

#define	CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)

#define	CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)

#define	CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL)

#define	CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL)

#define	CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL)

#define	CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL)

#define	CRG_AUD_PCM_DIV_REG_PCM_DIV_Pos (0UL)

#define	CRG_AUD_PCM_DIV_REG_PCM_DIV_Msk (0xfffUL)

#define	CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Pos (0UL)

#define	CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL)

#define	CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL)

#define	CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL)

#define	CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL)

#define	CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL)

#define	CRG_AUD_PDM_DIV_REG_PDM_DIV_Pos (0UL)

#define	CRG_AUD_PDM_DIV_REG_PDM_DIV_Msk (0xffUL)

#define	CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Pos (17UL)

#define	CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Msk (0x20000UL)

#define	CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Pos (16UL)

#define	CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Msk (0x10000UL)

#define	CRG_AUD_SRC_DIV_REG_SRC2_DIV_Pos (8UL)

#define	CRG_AUD_SRC_DIV_REG_SRC2_DIV_Msk (0xff00UL)

#define	CRG_AUD_SRC_DIV_REG_SRC_DIV_Pos (0UL)

#define	CRG_AUD_SRC_DIV_REG_SRC_DIV_Msk (0xffUL)

#define	CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)

#define	CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)

#define	CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos (6UL)

#define	CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)

#define	CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)

#define	CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)

#define	CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos (4UL)

#define	CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)

#define	CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)

#define	CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)

#define	CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos (2UL)

#define	CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)

#define	CRG_COM_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)

#define	CRG_COM_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)

#define	CRG_COM_CLK_COM_REG_UART_ENABLE_Pos (0UL)

#define	CRG_COM_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)

#define	CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)

#define	CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)

#define	CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos (6UL)

#define	CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)

#define	CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)

#define	CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)

#define	CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos (4UL)

#define	CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos (2UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos (0UL)

#define	CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)

#define	CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)

#define	CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)

#define	CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos (6UL)

#define	CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)

#define	CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)

#define	CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)

#define	CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos (4UL)

#define	CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)

#define	CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)

#define	CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)

#define	CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos (2UL)

#define	CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)

#define	CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)

#define	CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)

#define	CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos (0UL)

#define	CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)

#define	CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)

#define	CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)

#define	CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)

#define	CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)

#define	CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)

#define	CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Pos (8UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Msk (0x100UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Pos (7UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Msk (0x80UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Pos (6UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Msk (0x40UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Pos (5UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Msk (0x20UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Pos (4UL)

#define	CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Msk (0x10UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Pos (3UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Msk (0x8UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Pos (2UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Msk (0x4UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (1UL)

#define	CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x2UL)

#define	CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (0UL)

#define	CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x1UL)

#define	CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (6UL)

#define	CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0x7c0UL)

#define	CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos (0UL)

#define	CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk (0x1fUL)

#define	CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos (4UL)

#define	CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk (0xf0UL)

#define	CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos (0UL)

#define	CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk (0xfUL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Pos (8UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Msk (0x100UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Pos (7UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Msk (0x80UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Pos (6UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Msk (0x40UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Pos (4UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Msk (0x10UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Pos (3UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Msk (0x8UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Pos (2UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Msk (0x4UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Pos (0UL)

#define	CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Msk (0x3UL)

#define	CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL)

#define	CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL)

#define	CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL)

#define	CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL)

#define	CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Pos (7UL)

#define	CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Msk (0x80UL)

#define	CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL)

#define	CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL)

#define	CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL)

#define	CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL)

#define	CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL)

#define	CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Pos (15UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Msk (0x8000UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos (14UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk (0x4000UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos (13UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk (0x2000UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (12UL)

#define	CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x1000UL)

#define	CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Pos (5UL)

#define	CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Msk (0x20UL)

#define	CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos (2UL)

#define	CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk (0xcUL)

#define	CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL)

#define	CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL)

#define	CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (3UL)

#define	CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x8UL)

#define	CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos (2UL)

#define	CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk (0x4UL)

#define	CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos (1UL)

#define	CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk (0x2UL)

#define	CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos (0UL)

#define	CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk (0x1UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Pos (7UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Msk (0x780UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Pos (5UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Msk (0x60UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos (1UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk (0x1eUL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos (0UL)

#define	CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk (0x1UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Pos (3UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Msk (0x78UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Pos (2UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Msk (0x4UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Pos (1UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Msk (0x2UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Pos (0UL)

#define	CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Msk (0x1UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos (7UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk (0x780UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_C0_Pos (6UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_C0_Msk (0x40UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos (1UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk (0x3eUL)

#define	CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos (0UL)

#define	CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk (0x1UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos (21UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk (0x200000UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos (20UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk (0x100000UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos (19UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk (0x80000UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos (10UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk (0x7fc00UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos (0UL)

#define	CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk (0x3ffUL)

#define	CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos (0UL)

#define	CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk (0x1UL)

#define	CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos (2UL)

#define	CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk (0x4UL)

#define	CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos (1UL)

#define	CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk (0x2UL)

#define	CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (0UL)

#define	CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x1UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Pos (9UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Msk (0x1e00UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos (7UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x80UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos (3UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk (0x78UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos (1UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk (0x6UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos (0UL)

#define	CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk (0x1UL)

#define	CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Pos (2UL)

#define	CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Msk (0x4UL)

#define	CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Pos (1UL)

#define	CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Msk (0x2UL)

#define	CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Pos (0UL)

#define	CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Msk (0x1UL)

#define	CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Pos (4UL)

#define	CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Msk (0x30UL)

#define	CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Pos (2UL)

#define	CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Msk (0xcUL)

#define	CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Pos (0UL)

#define	CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Msk (0x1UL)

#define	CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos (0UL)

#define	CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk (0xffffUL)

#define	CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos (0UL)

#define	CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk (0xffffUL)

#define	CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos (0UL)

#define	CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk (0xffffUL)

#define	CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos (0UL)

#define	CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk (0xffffUL)

#define	CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos (0UL)

#define	CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk (0xffffUL)

#define	CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos (0UL)

#define	CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk (0xffffUL)

#define	CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Pos (11UL)

#define	CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Msk (0x800UL)

#define	CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Pos (10UL)

#define	CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Msk (0x400UL)

#define	CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Pos (9UL)

#define	CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Msk (0x200UL)

#define	CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (7UL)

#define	CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x80UL)

#define	CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos (6UL)

#define	CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk (0x40UL)

#define	CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL)

#define	CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL)

#define	CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL)

#define	CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL)

#define	CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos (3UL)

#define	CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk (0x8UL)

#define	CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos (2UL)

#define	CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk (0x4UL)

#define	CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL)

#define	CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL)

#define	CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL)

#define	CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL)

#define	CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos (16UL)

#define	CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk (0x10000UL)

#define	CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Pos (15UL)

#define	CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Msk (0x8000UL)

#define	CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Pos (14UL)

#define	CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Msk (0x4000UL)

#define	CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Pos (13UL)

#define	CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Msk (0x2000UL)

#define	CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Pos (12UL)

#define	CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Msk (0x1000UL)

#define	CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos (0UL)

#define	CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk (0xfffUL)

#define	CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos (7UL)

#define	CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk (0x80UL)

#define	CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos (0UL)

#define	CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk (0x3fUL)

#define	CRG_TOP_POR_TIMER_REG_POR_TIME_Pos (0UL)

#define	CRG_TOP_POR_TIMER_REG_POR_TIME_Msk (0x7fUL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Pos (14UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Msk (0x4000UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Pos (13UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Msk (0x2000UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Pos (12UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Msk (0x1000UL)

#define	CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Pos (11UL)

#define	CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Msk (0x800UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos (10UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk (0x400UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos (9UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk (0x200UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Pos (8UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Msk (0x100UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Pos (7UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Msk (0x80UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Pos (6UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Msk (0x40UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Pos (5UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Msk (0x20UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Pos (4UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Msk (0x10UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Pos (3UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Msk (0x8UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos (2UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk (0x4UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Pos (1UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Msk (0x2UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Pos (0UL)

#define	CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Msk (0x1UL)

#define	CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Pos (11UL)

#define	CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Msk (0x3800UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Pos (7UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Msk (0x780UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Pos (4UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Msk (0x70UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Pos (3UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Msk (0x8UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Pos (0UL)

#define	CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Msk (0x7UL)

#define	CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos (4UL)

#define	CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk (0x30UL)

#define	CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos (2UL)

#define	CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk (0xcUL)

#define	CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos (0UL)

#define	CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk (0x3UL)

#define	CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos (5UL)

#define	CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk (0x20UL)

#define	CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL)

#define	CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL)

#define	CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL)

#define	CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL)

#define	CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL)

#define	CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL)

#define	CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL)

#define	CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL)

#define	CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL)

#define	CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL)

#define	CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Pos (2UL)

#define	CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Msk (0x4UL)

#define	CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Pos (1UL)

#define	CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Msk (0x2UL)

#define	CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Pos (0UL)

#define	CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Msk (0x1UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Pos (8UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Msk (0x100UL)

#define	CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (6UL)

#define	CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x40UL)

#define	CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos (5UL)

#define	CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk (0x20UL)

#define	CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Pos (4UL)

#define	CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Msk (0x10UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Pos (3UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Msk (0x8UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Pos (2UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Msk (0x4UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Pos (1UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Msk (0x2UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Pos (0UL)

#define	CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Msk (0x1UL)

#define	CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Pos (9UL)

#define	CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Msk (0x200UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Pos (8UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Msk (0x100UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Pos (7UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Msk (0x80UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Pos (6UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Msk (0x40UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Pos (5UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Msk (0x20UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Pos (3UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Msk (0x18UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Pos (2UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Msk (0x4UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Pos (1UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Msk (0x2UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Pos (0UL)

#define	CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Msk (0x1UL)

#define	CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL)

#define	CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL)

#define	CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL)

#define	CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL)

#define	CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL)

#define	CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL)

#define	CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL)

#define	CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL)

#define	CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL)

#define	CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL)

#define	CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos (15UL)

#define	CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk (0x8000UL)

#define	CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (14UL)

#define	CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x4000UL)

#define	CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Pos (13UL)

#define	CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Msk (0x2000UL)

#define	CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Pos (12UL)

#define	CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Msk (0x1000UL)

#define	CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos (11UL)

#define	CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk (0x800UL)

#define	CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos (10UL)

#define	CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk (0x400UL)

#define	CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos (9UL)

#define	CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk (0x200UL)

#define	CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos (8UL)

#define	CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk (0x100UL)

#define	CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos (7UL)

#define	CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk (0x80UL)

#define	CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos (6UL)

#define	CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk (0x40UL)

#define	CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos (5UL)

#define	CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk (0x20UL)

#define	CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos (4UL)

#define	CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk (0x10UL)

#define	CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL)

#define	CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL)

#define	CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL)

#define	CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL)

#define	CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL)

#define	CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL)

#define	CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL)

#define	CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Pos (17UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Msk (0x7e0000UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Pos (12UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Msk (0x1f000UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Pos (8UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Msk (0xf00UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Pos (3UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Msk (0xf8UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Pos (2UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Msk (0x4UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Pos (1UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Msk (0x2UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Pos (0UL)

#define	CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Msk (0x1UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Pos (14UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Msk (0xc000UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Pos (13UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Msk (0x2000UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Pos (12UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Msk (0x1000UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Pos (8UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Msk (0xf00UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Pos (7UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Msk (0x80UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Pos (6UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Msk (0x40UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Pos (5UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Msk (0x20UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Pos (4UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Msk (0x10UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Pos (3UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Msk (0x8UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Pos (2UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Msk (0x4UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Pos (1UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Msk (0x2UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Pos (0UL)

#define	CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Msk (0x1UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Pos (31UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Msk (0x80000000UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Pos (26UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Msk (0x7c000000UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Pos (25UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Msk (0x2000000UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Pos (20UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Msk (0x1f00000UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Pos (14UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Msk (0xfc000UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Pos (9UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Msk (0x3e00UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Pos (5UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Msk (0x1e0UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Pos (0UL)

#define	CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Msk (0x1fUL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Pos (6UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Msk (0x1c0UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Pos (5UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Msk (0x20UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Pos (3UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Msk (0x18UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Pos (0UL)

#define	CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Msk (0x7UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Pos (8UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Msk (0x100UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Pos (6UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Msk (0xc0UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Pos (4UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Msk (0x30UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Pos (2UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Msk (0xcUL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Pos (0UL)

#define	CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Msk (0x3UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Pos (4UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Msk (0x10UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Pos (3UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Msk (0x8UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Pos (2UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Msk (0x4UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Pos (1UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Msk (0x2UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Pos (0UL)

#define	CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Msk (0x1UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Pos (10UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Msk (0xc00UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Pos (9UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Msk (0x200UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Pos (8UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Msk (0x100UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Pos (0UL)

#define	CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Msk (0xffUL)

#define	CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Pos (8UL)

#define	CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Msk (0xff00UL)

#define	CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Pos (0UL)

#define	CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Msk (0xffUL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Pos (20UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Msk (0x7f00000UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Pos (17UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Msk (0xe0000UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Pos (15UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Pos (12UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Pos (8UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Msk (0xf00UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Pos (0UL)

#define	CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Msk (0xffUL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Pos (20UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Msk (0x7f00000UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Pos (17UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Msk (0xe0000UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Pos (15UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Pos (12UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Pos (8UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Msk (0xf00UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Pos (0UL)

#define	CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Msk (0xffUL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Pos (11UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Msk (0x7f800UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Pos (7UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Msk (0x780UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Pos (6UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Msk (0x40UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Pos (5UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Msk (0x20UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Pos (1UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Msk (0x1eUL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Pos (0UL)

#define	CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Msk (0x1UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Pos (15UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Pos (12UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Pos (8UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Msk (0xf00UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Pos (0UL)

#define	CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Msk (0xffUL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Pos (17UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Msk (0x1e0000UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Pos (16UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Msk (0x10000UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Pos (12UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Msk (0xf000UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Pos (8UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Msk (0xf00UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Pos (6UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Msk (0xc0UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Pos (3UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Msk (0x38UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Pos (1UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Msk (0x6UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Pos (0UL)

#define	DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Msk (0x1UL)

#define	DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL)

#define	DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL)

#define	DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL)

#define	DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL)

#define	DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

#define	DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

#define	DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

#define	DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

#define	DMA_DMA0_CTRL_REG_BURST_MODE_Pos (13UL)

#define	DMA_DMA0_CTRL_REG_BURST_MODE_Msk (0x6000UL)

#define	DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (12UL)

#define	DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

#define	DMA_DMA0_CTRL_REG_DMA_INIT_Pos (11UL)

#define	DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x800UL)

#define	DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (10UL)

#define	DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x400UL)

#define	DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (7UL)

#define	DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x380UL)

#define	DMA_DMA0_CTRL_REG_CIRCULAR_Pos (6UL)

#define	DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x40UL)

#define	DMA_DMA0_CTRL_REG_AINC_Pos (5UL)

#define	DMA_DMA0_CTRL_REG_AINC_Msk (0x20UL)

#define	DMA_DMA0_CTRL_REG_BINC_Pos (4UL)

#define	DMA_DMA0_CTRL_REG_BINC_Msk (0x10UL)

#define	DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (3UL)

#define	DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x8UL)

#define	DMA_DMA0_CTRL_REG_BW_Pos (1UL)

#define	DMA_DMA0_CTRL_REG_BW_Msk (0x6UL)

#define	DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL)

#define	DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL)

#define	DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL)

#define	DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL)

#define	DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL)

#define	DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL)

#define	DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL)

#define	DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL)

#define	DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL)

#define	DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL)

#define	DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL)

#define	DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL)

#define	DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

#define	DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

#define	DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

#define	DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

#define	DMA_DMA1_CTRL_REG_BURST_MODE_Pos (13UL)

#define	DMA_DMA1_CTRL_REG_BURST_MODE_Msk (0x6000UL)

#define	DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (12UL)

#define	DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

#define	DMA_DMA1_CTRL_REG_DMA_INIT_Pos (11UL)

#define	DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x800UL)

#define	DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (10UL)

#define	DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x400UL)

#define	DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (7UL)

#define	DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x380UL)

#define	DMA_DMA1_CTRL_REG_CIRCULAR_Pos (6UL)

#define	DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x40UL)

#define	DMA_DMA1_CTRL_REG_AINC_Pos (5UL)

#define	DMA_DMA1_CTRL_REG_AINC_Msk (0x20UL)

#define	DMA_DMA1_CTRL_REG_BINC_Pos (4UL)

#define	DMA_DMA1_CTRL_REG_BINC_Msk (0x10UL)

#define	DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (3UL)

#define	DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x8UL)

#define	DMA_DMA1_CTRL_REG_BW_Pos (1UL)

#define	DMA_DMA1_CTRL_REG_BW_Msk (0x6UL)

#define	DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL)

#define	DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL)

#define	DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL)

#define	DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL)

#define	DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL)

#define	DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL)

#define	DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL)

#define	DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL)

#define	DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL)

#define	DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL)

#define	DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL)

#define	DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL)

#define	DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

#define	DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

#define	DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

#define	DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

#define	DMA_DMA2_CTRL_REG_BURST_MODE_Pos (13UL)

#define	DMA_DMA2_CTRL_REG_BURST_MODE_Msk (0x6000UL)

#define	DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (12UL)

#define	DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

#define	DMA_DMA2_CTRL_REG_DMA_INIT_Pos (11UL)

#define	DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x800UL)

#define	DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (10UL)

#define	DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x400UL)

#define	DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (7UL)

#define	DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x380UL)

#define	DMA_DMA2_CTRL_REG_CIRCULAR_Pos (6UL)

#define	DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x40UL)

#define	DMA_DMA2_CTRL_REG_AINC_Pos (5UL)

#define	DMA_DMA2_CTRL_REG_AINC_Msk (0x20UL)

#define	DMA_DMA2_CTRL_REG_BINC_Pos (4UL)

#define	DMA_DMA2_CTRL_REG_BINC_Msk (0x10UL)

#define	DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (3UL)

#define	DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x8UL)

#define	DMA_DMA2_CTRL_REG_BW_Pos (1UL)

#define	DMA_DMA2_CTRL_REG_BW_Msk (0x6UL)

#define	DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL)

#define	DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL)

#define	DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL)

#define	DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL)

#define	DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL)

#define	DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL)

#define	DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL)

#define	DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL)

#define	DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL)

#define	DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL)

#define	DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL)

#define	DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL)

#define	DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

#define	DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

#define	DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

#define	DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

#define	DMA_DMA3_CTRL_REG_BURST_MODE_Pos (13UL)

#define	DMA_DMA3_CTRL_REG_BURST_MODE_Msk (0x6000UL)

#define	DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (12UL)

#define	DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

#define	DMA_DMA3_CTRL_REG_DMA_INIT_Pos (11UL)

#define	DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x800UL)

#define	DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (10UL)

#define	DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x400UL)

#define	DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (7UL)

#define	DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x380UL)

#define	DMA_DMA3_CTRL_REG_CIRCULAR_Pos (6UL)

#define	DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x40UL)

#define	DMA_DMA3_CTRL_REG_AINC_Pos (5UL)

#define	DMA_DMA3_CTRL_REG_AINC_Msk (0x20UL)

#define	DMA_DMA3_CTRL_REG_BINC_Pos (4UL)

#define	DMA_DMA3_CTRL_REG_BINC_Msk (0x10UL)

#define	DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (3UL)

#define	DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x8UL)

#define	DMA_DMA3_CTRL_REG_BW_Pos (1UL)

#define	DMA_DMA3_CTRL_REG_BW_Msk (0x6UL)

#define	DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL)

#define	DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL)

#define	DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL)

#define	DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL)

#define	DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL)

#define	DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL)

#define	DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL)

#define	DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL)

#define	DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL)

#define	DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL)

#define	DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL)

#define	DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL)

#define	DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

#define	DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

#define	DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

#define	DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

#define	DMA_DMA4_CTRL_REG_BURST_MODE_Pos (13UL)

#define	DMA_DMA4_CTRL_REG_BURST_MODE_Msk (0x6000UL)

#define	DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (12UL)

#define	DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

#define	DMA_DMA4_CTRL_REG_DMA_INIT_Pos (11UL)

#define	DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x800UL)

#define	DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (10UL)

#define	DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x400UL)

#define	DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (7UL)

#define	DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x380UL)

#define	DMA_DMA4_CTRL_REG_CIRCULAR_Pos (6UL)

#define	DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x40UL)

#define	DMA_DMA4_CTRL_REG_AINC_Pos (5UL)

#define	DMA_DMA4_CTRL_REG_AINC_Msk (0x20UL)

#define	DMA_DMA4_CTRL_REG_BINC_Pos (4UL)

#define	DMA_DMA4_CTRL_REG_BINC_Msk (0x10UL)

#define	DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (3UL)

#define	DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x8UL)

#define	DMA_DMA4_CTRL_REG_BW_Pos (1UL)

#define	DMA_DMA4_CTRL_REG_BW_Msk (0x6UL)

#define	DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL)

#define	DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL)

#define	DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL)

#define	DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL)

#define	DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL)

#define	DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL)

#define	DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL)

#define	DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL)

#define	DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL)

#define	DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL)

#define	DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL)

#define	DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL)

#define	DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

#define	DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

#define	DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

#define	DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

#define	DMA_DMA5_CTRL_REG_BURST_MODE_Pos (13UL)

#define	DMA_DMA5_CTRL_REG_BURST_MODE_Msk (0x6000UL)

#define	DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (12UL)

#define	DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

#define	DMA_DMA5_CTRL_REG_DMA_INIT_Pos (11UL)

#define	DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x800UL)

#define	DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (10UL)

#define	DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x400UL)

#define	DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (7UL)

#define	DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x380UL)

#define	DMA_DMA5_CTRL_REG_CIRCULAR_Pos (6UL)

#define	DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x40UL)

#define	DMA_DMA5_CTRL_REG_AINC_Pos (5UL)

#define	DMA_DMA5_CTRL_REG_AINC_Msk (0x20UL)

#define	DMA_DMA5_CTRL_REG_BINC_Pos (4UL)

#define	DMA_DMA5_CTRL_REG_BINC_Msk (0x10UL)

#define	DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (3UL)

#define	DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x8UL)

#define	DMA_DMA5_CTRL_REG_BW_Pos (1UL)

#define	DMA_DMA5_CTRL_REG_BW_Msk (0x6UL)

#define	DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL)

#define	DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL)

#define	DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL)

#define	DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL)

#define	DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL)

#define	DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL)

#define	DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL)

#define	DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL)

#define	DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL)

#define	DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (13UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x2000UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (12UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x1000UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (11UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x800UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (10UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x400UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (9UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x200UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (8UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x100UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL)

#define	DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL)

#define	DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL)

#define	DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL)

#define	DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL)

#define	DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL)

#define	DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL)

#define	DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Pos (5UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Msk (0x20UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Pos (4UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Msk (0x10UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Pos (3UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Msk (0x8UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Pos (2UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Msk (0x4UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Pos (1UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Msk (0x2UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Pos (0UL)

#define	DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Msk (0x1UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Pos (5UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Msk (0x20UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Pos (4UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Msk (0x10UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Pos (3UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Msk (0x8UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Pos (2UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Msk (0x4UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Pos (1UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Msk (0x2UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Pos (0UL)

#define	DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Msk (0x1UL)

#define	DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL)

#define	DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL)

#define	DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL)

#define	DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL)

#define	DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL)

#define	DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL)

#define	DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL)

#define	DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL)

#define	DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL)

#define	DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL)

#define	DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL)

#define	DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL)

#define	DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL)

#define	DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL)

#define	DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL)

#define	DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL)

#define	DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL)

#define	DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL)

#define	DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL)

#define	DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL)

#define	DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL)

#define	DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL)

#define	DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL)

#define	DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL)

#define	FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Pos (25UL)

#define	FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Msk (0x2000000UL)

#define	FCU_FLASH_CTRL_REG_DFT_EN_Pos (24UL)

#define	FCU_FLASH_CTRL_REG_DFT_EN_Msk (0x1000000UL)

#define	FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Pos (23UL)

#define	FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Msk (0x800000UL)

#define	FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Pos (22UL)

#define	FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Msk (0x400000UL)

#define	FCU_FLASH_CTRL_REG_ERASE_RESUME_Pos (21UL)

#define	FCU_FLASH_CTRL_REG_ERASE_RESUME_Msk (0x200000UL)

#define	FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Pos (20UL)

#define	FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Msk (0x100000UL)

#define	FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Pos (19UL)

#define	FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Msk (0x80000UL)

#define	FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Pos (18UL)

#define	FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Msk (0x40000UL)

#define	FCU_FLASH_CTRL_REG_SLEEP_Pos (17UL)

#define	FCU_FLASH_CTRL_REG_SLEEP_Msk (0x20000UL)

#define	FCU_FLASH_CTRL_REG_DMA_EN_Pos (16UL)

#define	FCU_FLASH_CTRL_REG_DMA_EN_Msk (0x10000UL)

#define	FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Pos (15UL)

#define	FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Msk (0x8000UL)

#define	FCU_FLASH_CTRL_REG_BUS_ERROR_Pos (14UL)

#define	FCU_FLASH_CTRL_REG_BUS_ERROR_Msk (0x4000UL)

#define	FCU_FLASH_CTRL_REG_IRQ_CLEAR_Pos (13UL)

#define	FCU_FLASH_CTRL_REG_IRQ_CLEAR_Msk (0x2000UL)

#define	FCU_FLASH_CTRL_REG_WAIT_CYCLES_Pos (10UL)

#define	FCU_FLASH_CTRL_REG_WAIT_CYCLES_Msk (0x1c00UL)

#define	FCU_FLASH_CTRL_REG_FLASH_RPROT_Pos (9UL)

#define	FCU_FLASH_CTRL_REG_FLASH_RPROT_Msk (0x200UL)

#define	FCU_FLASH_CTRL_REG_FLASH_WPROT_Pos (8UL)

#define	FCU_FLASH_CTRL_REG_FLASH_WPROT_Msk (0x100UL)

#define	FCU_FLASH_CTRL_REG_FLASH_PROT_Pos (7UL)

#define	FCU_FLASH_CTRL_REG_FLASH_PROT_Msk (0x80UL)

#define	FCU_FLASH_CTRL_REG_PROG_RMIN_Pos (6UL)

#define	FCU_FLASH_CTRL_REG_PROG_RMIN_Msk (0x40UL)

#define	FCU_FLASH_CTRL_REG_PROG_ERS_Pos (5UL)

#define	FCU_FLASH_CTRL_REG_PROG_ERS_Msk (0x20UL)

#define	FCU_FLASH_CTRL_REG_PROG_WRS_Pos (4UL)

#define	FCU_FLASH_CTRL_REG_PROG_WRS_Msk (0x10UL)

#define	FCU_FLASH_CTRL_REG_PROG_SEL_Pos (3UL)

#define	FCU_FLASH_CTRL_REG_PROG_SEL_Msk (0x8UL)

#define	FCU_FLASH_CTRL_REG_SLEEP_MODE_Pos (2UL)

#define	FCU_FLASH_CTRL_REG_SLEEP_MODE_Msk (0x4UL)

#define	FCU_FLASH_CTRL_REG_PROG_MODE_Pos (0UL)

#define	FCU_FLASH_CTRL_REG_PROG_MODE_Msk (0x3UL)

#define	FCU_FLASH_PTERASE_REG_PTERASE_Pos (0UL)

#define	FCU_FLASH_PTERASE_REG_PTERASE_Msk (0xffffffUL)

#define	FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Pos (0UL)

#define	FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Msk (0xffffffUL)

#define	FCU_FLASH_PTME_REG_PTME_Pos (0UL)

#define	FCU_FLASH_PTME_REG_PTME_Msk (0xffffffUL)

#define	FCU_FLASH_PTNVH1_REG_PTNVH1_Pos (0UL)

#define	FCU_FLASH_PTNVH1_REG_PTNVH1_Msk (0xffffUL)

#define	FCU_FLASH_PTPROG_REG_PTPROG_Pos (0UL)

#define	FCU_FLASH_PTPROG_REG_PTPROG_Msk (0xffffUL)

#define	FCU_FLASH_PTWK_SP_REG_PTWK_SP_Pos (0UL)

#define	FCU_FLASH_PTWK_SP_REG_PTWK_SP_Msk (0xffUL)

#define	FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Pos (0UL)

#define	FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Msk (0xffffffUL)

#define	FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Pos (0UL)

#define	FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Msk (0xffffffUL)

#define	GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL)

#define	GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (13UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xe000UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (9UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0x1e00UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (6UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0x1c0UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Pos (0UL)

#define	GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Msk (0x3UL)

#define	GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL)

#define	GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL)

#define	GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL)

#define	GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL)

#define	GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Pos (12UL)

#define	GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Msk (0x1000UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Pos (10UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Msk (0x400UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (9UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x200UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (8UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x100UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Pos (3UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Msk (0x8UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL)

#define	GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL)

#define	GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL)

#define	GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL)

#define	GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL)

#define	GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL)

#define	GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL)

#define	GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL)

#define	GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Pos (4UL)

#define	GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Msk (0xf0UL)

#define	GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Pos (0UL)

#define	GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Msk (0xfUL)

#define	GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos (9UL)

#define	GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk (0x200UL)

#define	GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos (8UL)

#define	GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk (0x100UL)

#define	GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos (7UL)

#define	GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk (0x80UL)

#define	GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL)

#define	GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL)

#define	GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL)

#define	GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL)

#define	GPIO_P0_00_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_00_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_00_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_00_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_00_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_00_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_01_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_01_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_01_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_01_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_01_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_01_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_02_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_02_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_02_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_02_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_02_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_02_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_03_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_03_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_03_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_03_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_03_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_03_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_04_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_04_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_04_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_04_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_04_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_04_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_05_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_05_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_05_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_05_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_05_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_05_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_06_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_06_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_06_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_06_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_06_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_06_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_07_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_07_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_07_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_07_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_07_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_07_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_08_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_08_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_08_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_08_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_08_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_08_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_09_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_09_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_09_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_09_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_09_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_09_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_10_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_10_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_10_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_10_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_10_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_10_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_11_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_11_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_11_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_11_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_11_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_11_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_12_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_12_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_12_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_12_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_12_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_12_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_13_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_13_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_13_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_13_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_13_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_13_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_14_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_14_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_14_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_14_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_14_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_14_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_15_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P0_15_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P0_15_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P0_15_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P0_15_MODE_REG_PID_Pos (0UL)

#define	GPIO_P0_15_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P0_DATA_REG_P0_DATA_Pos (0UL)

#define	GPIO_P0_DATA_REG_P0_DATA_Msk (0xffffUL)

#define	GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL)

#define	GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffffUL)

#define	GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL)

#define	GPIO_P0_SET_DATA_REG_P0_SET_Msk (0xffffUL)

#define	GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Pos (6UL)

#define	GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Msk (0xffc0UL)

#define	GPIO_P1_00_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_00_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_00_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_00_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_00_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_00_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_01_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_01_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_01_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_01_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_01_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_01_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_02_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_02_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_02_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_02_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_02_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_02_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_03_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_03_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_03_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_03_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_03_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_03_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_04_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_04_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_04_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_04_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_04_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_04_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_05_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_05_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_05_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_05_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_05_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_05_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_06_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_06_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_06_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_06_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_06_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_06_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_07_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_07_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_07_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_07_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_07_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_07_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_08_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_08_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_08_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_08_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_08_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_08_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_09_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_09_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_09_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_09_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_09_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_09_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_10_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_10_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_10_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_10_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_10_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_10_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_11_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_11_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_11_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_11_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_11_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_11_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_12_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_12_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_12_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_12_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_12_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_12_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_13_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_13_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_13_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_13_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_13_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_13_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_14_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_14_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_14_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_14_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_14_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_14_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_15_MODE_REG_PPOD_Pos (10UL)

#define	GPIO_P1_15_MODE_REG_PPOD_Msk (0x400UL)

#define	GPIO_P1_15_MODE_REG_PUPD_Pos (8UL)

#define	GPIO_P1_15_MODE_REG_PUPD_Msk (0x300UL)

#define	GPIO_P1_15_MODE_REG_PID_Pos (0UL)

#define	GPIO_P1_15_MODE_REG_PID_Msk (0x3fUL)

#define	GPIO_P1_DATA_REG_P1_DATA_Pos (0UL)

#define	GPIO_P1_DATA_REG_P1_DATA_Msk (0xffffUL)

#define	GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL)

#define	GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0xffffUL)

#define	GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL)

#define	GPIO_P1_SET_DATA_REG_P1_SET_Msk (0xffffUL)

#define	GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Pos (0UL)

#define	GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Msk (0xffffUL)

#define	GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos (8UL)

#define	GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk (0x100UL)

#define	GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (7UL)

#define	GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x80UL)

#define	GPREG_DEBUG_REG_SYS_CPUWAIT_Pos (6UL)

#define	GPREG_DEBUG_REG_SYS_CPUWAIT_Msk (0x40UL)

#define	GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos (5UL)

#define	GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk (0x20UL)

#define	GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (4UL)

#define	GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x10UL)

#define	GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos (3UL)

#define	GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk (0x8UL)

#define	GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos (2UL)

#define	GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk (0x4UL)

#define	GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos (1UL)

#define	GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk (0x2UL)

#define	GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL)

#define	GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL)

#define	GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL)

#define	GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)

#define	GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)

#define	GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Pos (1UL)

#define	GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Msk (0x2UL)

#define	GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Pos (0UL)

#define	GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Msk (0x1UL)

#define	GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)

#define	GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)

#define	GPREG_SET_FREEZE_REG_FRZ_DMA_Pos (5UL)

#define	GPREG_SET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)

#define	GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)

#define	GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)

#define	GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)

#define	GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)

#define	GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)

#define	I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)

#define	I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)

#define	I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)

#define	I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)

#define	I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)

#define	I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)

#define	I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL)

#define	I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL)

#define	I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)

#define	I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)

#define	I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)

#define	I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)

#define	I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)

#define	I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)

#define	I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)

#define	I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)

#define	I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)

#define	I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)

#define	I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL)

#define	I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL)

#define	I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)

#define	I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)

#define	I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)

#define	I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)

#define	I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL)

#define	I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL)

#define	I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL)

#define	I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL)

#define	I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL)

#define	I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL)

#define	I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL)

#define	I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL)

#define	I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)

#define	I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)

#define	I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL)

#define	I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL)

#define	I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)

#define	I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)

#define	I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)

#define	I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)

#define	I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL)

#define	I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL)

#define	I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL)

#define	I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos (8UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk (0x100UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos (0UL)

#define	I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk (0xffUL)

#define	I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL)

#define	I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL)

#define	I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL)

#define	I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL)

#define	I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL)

#define	I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL)

#define	I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL)

#define	I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL)

#define	I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL)

#define	I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL)

#define	I2C_I2C_ENABLE_REG_I2C_ABORT_Pos (1UL)

#define	I2C_I2C_ENABLE_REG_I2C_ABORT_Msk (0x2UL)

#define	I2C_I2C_ENABLE_REG_I2C_EN_Pos (0UL)

#define	I2C_I2C_ENABLE_REG_I2C_EN_Msk (0x1UL)

#define	I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)

#define	I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)

#define	I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL)

#define	I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL)

#define	I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL)

#define	I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL)

#define	I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)

#define	I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)

#define	I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)

#define	I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)

#define	I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL)

#define	I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL)

#define	I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL)

#define	I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL)

#define	I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL)

#define	I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL)

#define	I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL)

#define	I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL)

#define	I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL)

#define	I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL)

#define	I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL)

#define	I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL)

#define	I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL)

#define	I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL)

#define	I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL)

#define	I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL)

#define	I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL)

#define	I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL)

#define	I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL)

#define	I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL)

#define	I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL)

#define	I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL)

#define	I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL)

#define	I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL)

#define	I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL)

#define	I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL)

#define	I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL)

#define	I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL)

#define	I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL)

#define	I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL)

#define	I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL)

#define	I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL)

#define	I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL)

#define	I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL)

#define	I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL)

#define	I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL)

#define	I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL)

#define	I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL)

#define	I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL)

#define	I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL)

#define	I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL)

#define	I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL)

#define	I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL)

#define	I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL)

#define	I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL)

#define	I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL)

#define	I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL)

#define	I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL)

#define	I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL)

#define	I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL)

#define	I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL)

#define	I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL)

#define	I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL)

#define	I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL)

#define	I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL)

#define	I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)

#define	I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)

#define	I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL)

#define	I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL)

#define	I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL)

#define	I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL)

#define	I2C_I2C_SAR_REG_IC_SAR_Pos (0UL)

#define	I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL)

#define	I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL)

#define	I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL)

#define	I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL)

#define	I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL)

#define	I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL)

#define	I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL)

#define	I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)

#define	I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)

#define	I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)

#define	I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)

#define	I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL)

#define	I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL)

#define	I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL)

#define	I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL)

#define	I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL)

#define	I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL)

#define	I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL)

#define	I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL)

#define	I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL)

#define	I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL)

#define	I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL)

#define	I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL)

#define	I2C_I2C_STATUS_REG_RFF_Pos (4UL)

#define	I2C_I2C_STATUS_REG_RFF_Msk (0x10UL)

#define	I2C_I2C_STATUS_REG_RFNE_Pos (3UL)

#define	I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL)

#define	I2C_I2C_STATUS_REG_TFE_Pos (2UL)

#define	I2C_I2C_STATUS_REG_TFE_Msk (0x4UL)

#define	I2C_I2C_STATUS_REG_TFNF_Pos (1UL)

#define	I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL)

#define	I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL)

#define	I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL)

#define	I2C_I2C_TAR_REG_SPECIAL_Pos (11UL)

#define	I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL)

#define	I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL)

#define	I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL)

#define	I2C_I2C_TAR_REG_IC_TAR_Pos (0UL)

#define	I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL)

#define	I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL)

#define	I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)

#define	I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL)

#define	I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL)

#define	I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL)

#define	MDCT_MDCT_CTRL_REG_DONE_Pos (31UL)

#define	MDCT_MDCT_CTRL_REG_DONE_Msk (0x80000000UL)

#define	MDCT_MDCT_CTRL_REG_USE_CORDIC_Pos (29UL)

#define	MDCT_MDCT_CTRL_REG_USE_CORDIC_Msk (0x20000000UL)

#define	MDCT_MDCT_CTRL_REG_IRQ_CLR_Pos (28UL)

#define	MDCT_MDCT_CTRL_REG_IRQ_CLR_Msk (0x10000000UL)

#define	MDCT_MDCT_CTRL_REG_CLK_DIV_Pos (26UL)

#define	MDCT_MDCT_CTRL_REG_CLK_DIV_Msk (0xc000000UL)

#define	MDCT_MDCT_CTRL_REG_XFORM_SIZE_Pos (16UL)

#define	MDCT_MDCT_CTRL_REG_XFORM_SIZE_Msk (0x3ff0000UL)

#define	MDCT_MDCT_CTRL_REG_Y_STRIDE_Pos (8UL)

#define	MDCT_MDCT_CTRL_REG_Y_STRIDE_Msk (0xff00UL)

#define	MDCT_MDCT_CTRL_REG_WORD_SIZE_Pos (7UL)

#define	MDCT_MDCT_CTRL_REG_WORD_SIZE_Msk (0x80UL)

#define	MDCT_MDCT_CTRL_REG_INVERSE_Pos (6UL)

#define	MDCT_MDCT_CTRL_REG_INVERSE_Msk (0x40UL)

#define	MDCT_MDCT_CTRL_REG_N_STAGES_Pos (2UL)

#define	MDCT_MDCT_CTRL_REG_N_STAGES_Msk (0x3cUL)

#define	MDCT_MDCT_CTRL_REG_IRQ_EN_Pos (1UL)

#define	MDCT_MDCT_CTRL_REG_IRQ_EN_Msk (0x2UL)

#define	MDCT_MDCT_CTRL_REG_EN_Pos (0UL)

#define	MDCT_MDCT_CTRL_REG_EN_Msk (0x1UL)

#define	MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Pos (0UL)

#define	MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Msk (0xffffffffUL)

#define	MDCT_MDCT_STAGE0_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE0_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE0_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE0_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE0_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE0_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE0_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE0_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE0_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE0_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE1_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE1_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE1_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE1_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE1_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE1_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE1_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE1_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE1_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE1_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE2_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE2_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE2_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE2_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE2_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE2_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE2_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE2_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE2_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE2_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE3_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE3_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE3_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE3_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE3_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE3_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE3_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE3_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE3_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE3_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE4_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE4_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE4_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE4_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE4_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE4_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE4_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE4_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE4_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE4_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE5_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE5_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE5_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE5_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE5_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE5_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE5_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE5_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE5_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE5_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE6_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE6_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE6_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE6_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE6_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE6_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE6_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE6_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE6_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE6_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_STAGE7_REG_STRIDE_Pos (22UL)

#define	MDCT_MDCT_STAGE7_REG_STRIDE_Msk (0xffc00000UL)

#define	MDCT_MDCT_STAGE7_REG_M_Pos (12UL)

#define	MDCT_MDCT_STAGE7_REG_M_Msk (0x3ff000UL)

#define	MDCT_MDCT_STAGE7_REG_RADIX_Pos (8UL)

#define	MDCT_MDCT_STAGE7_REG_RADIX_Msk (0x700UL)

#define	MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Pos (6UL)

#define	MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Msk (0x40UL)

#define	MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Pos (5UL)

#define	MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Msk (0x20UL)

#define	MDCT_MDCT_STAGE7_REG_IN_BUFFER_Pos (4UL)

#define	MDCT_MDCT_STAGE7_REG_IN_BUFFER_Msk (0x10UL)

#define	MDCT_MDCT_STAGE7_REG_MODE_Pos (0UL)

#define	MDCT_MDCT_STAGE7_REG_MODE_Msk (0x7UL)

#define	MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Pos (0UL)

#define	MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Msk (0xffffffffUL)

#define	MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Pos (0UL)

#define	MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Msk (0xffffffffUL)

#define	MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Pos (0UL)

#define	MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Msk (0xffffffffUL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos (30UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk (0xc0000000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Pos (28UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Msk (0x30000000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Pos (26UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Msk (0xc000000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Pos (24UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Msk (0x3000000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos (22UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk (0xc00000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos (20UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk (0x300000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos (18UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk (0xc0000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos (16UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk (0x30000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Pos (14UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Msk (0xc000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos (12UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk (0x3000UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos (10UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk (0xc00UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos (8UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk (0x300UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos (6UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk (0xc0UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos (4UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk (0x30UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos (2UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk (0xcUL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos (0UL)

#define	MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk (0x3UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos (30UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk (0xc0000000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Pos (28UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Msk (0x30000000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Pos (26UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Msk (0xc000000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Pos (24UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Msk (0x3000000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos (22UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk (0xc00000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos (20UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk (0x300000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos (18UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk (0xc0000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos (16UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk (0x30000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Pos (14UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Msk (0xc000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos (12UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk (0x3000UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos (10UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk (0xc00UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos (8UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk (0x300UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos (6UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk (0xc0UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos (4UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk (0x30UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos (2UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk (0xcUL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos (0UL)

#define	MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk (0x3UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos (30UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk (0xc0000000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Pos (28UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Msk (0x30000000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Pos (26UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Msk (0xc000000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Pos (24UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Msk (0x3000000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos (22UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk (0xc00000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos (20UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk (0x300000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos (18UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk (0xc0000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos (16UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk (0x30000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Pos (14UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Msk (0xc000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos (12UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk (0x3000UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos (10UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk (0xc00UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos (8UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk (0x300UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos (6UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk (0xc0UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos (4UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk (0x30UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos (2UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk (0xcUL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos (0UL)

#define	MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk (0x3UL)

#define	MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos (8UL)

#define	MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk (0x7ff00UL)

#define	MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos (2UL)

#define	MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk (0x7fffcUL)

#define	MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos (2UL)

#define	MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk (0x7fffcUL)

#define	MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Pos (6UL)

#define	MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Msk (0x1c0UL)

#define	MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos (3UL)

#define	MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk (0x38UL)

#define	MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos (0UL)

#define	MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk (0x7UL)

#define	MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Pos (8UL)

#define	MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Msk (0xf00UL)

#define	MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos (4UL)

#define	MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk (0xf0UL)

#define	MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos (0UL)

#define	MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk (0xfUL)

#define	MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos (2UL)

#define	MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk (0x4UL)

#define	MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos (1UL)

#define	MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk (0x2UL)

#define	MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos (0UL)

#define	MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk (0x1UL)

#define	MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Pos (21UL)

#define	MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Msk (0x200000UL)

#define	MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Pos (20UL)

#define	MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Msk (0x100000UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Pos (16UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Msk (0xf0000UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos (12UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk (0xf000UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos (8UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk (0xf00UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Pos (6UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Msk (0x40UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos (5UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk (0x20UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos (4UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk (0x10UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Pos (2UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Msk (0x4UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos (1UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk (0x2UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos (0UL)

#define	MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk (0x1UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL)

#define	PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Pos (11UL)

#define	PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Msk (0xf800UL)

#define	PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL)

#define	PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSCINV_Pos (9UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSCINV_Msk (0x200UL)

#define	PCM1_PCM1_CTRL_REG_PCM_CLKINV_Pos (8UL)

#define	PCM1_PCM1_CTRL_REG_PCM_CLKINV_Msk (0x100UL)

#define	PCM1_PCM1_CTRL_REG_PCM_PPOD_Pos (7UL)

#define	PCM1_PCM1_CTRL_REG_PCM_PPOD_Msk (0x80UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Pos (6UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Msk (0x40UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Pos (2UL)

#define	PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Msk (0x3cUL)

#define	PCM1_PCM1_CTRL_REG_PCM_MASTER_Pos (1UL)

#define	PCM1_PCM1_CTRL_REG_PCM_MASTER_Msk (0x2UL)

#define	PCM1_PCM1_CTRL_REG_PCM_EN_Pos (0UL)

#define	PCM1_PCM1_CTRL_REG_PCM_EN_Msk (0x1UL)

#define	PCM1_PCM1_IN1_REG_PCM_IN_Pos (0UL)

#define	PCM1_PCM1_IN1_REG_PCM_IN_Msk (0xffffffffUL)

#define	PCM1_PCM1_IN2_REG_PCM_IN_Pos (0UL)

#define	PCM1_PCM1_IN2_REG_PCM_IN_Msk (0xffffffffUL)

#define	PCM1_PCM1_OUT1_REG_PCM_OUT_Pos (0UL)

#define	PCM1_PCM1_OUT1_REG_PCM_OUT_Msk (0xffffffffUL)

#define	PCM1_PCM1_OUT2_REG_PCM_OUT_Pos (0UL)

#define	PCM1_PCM1_OUT2_REG_PCM_OUT_Msk (0xffffffffUL)

#define	PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos (0UL)

#define	PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk (0x1fUL)

#define	PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Pos (2UL)

#define	PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Msk (0x4UL)

#define	PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Pos (1UL)

#define	PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Msk (0x2UL)

#define	PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Pos (0UL)

#define	PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Msk (0x1UL)

#define	PDC_PDC_CTRL0_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL0_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL0_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL0_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL0_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL0_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL0_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL0_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL0_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL0_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL0_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL0_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL10_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL10_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL10_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL10_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL10_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL10_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL10_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL10_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL10_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL10_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL10_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL10_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL11_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL11_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL11_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL11_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL11_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL11_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL11_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL11_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL11_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL11_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL11_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL11_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL1_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL1_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL1_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL1_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL1_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL1_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL1_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL1_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL1_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL1_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL1_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL1_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL2_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL2_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL2_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL2_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL2_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL2_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL2_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL2_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL2_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL2_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL2_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL2_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL3_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL3_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL3_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL3_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL3_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL3_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL3_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL3_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL3_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL3_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL3_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL3_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL4_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL4_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL4_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL4_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL4_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL4_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL4_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL4_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL4_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL4_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL4_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL4_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL5_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL5_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL5_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL5_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL5_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL5_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL5_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL5_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL5_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL5_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL5_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL5_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL6_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL6_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL6_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL6_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL6_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL6_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL6_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL6_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL6_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL6_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL6_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL6_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL7_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL7_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL7_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL7_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL7_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL7_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL7_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL7_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL7_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL7_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL7_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL7_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL8_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL8_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL8_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL8_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL8_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL8_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL8_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL8_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL8_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL8_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL8_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL8_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_CTRL9_REG_PDC_MASTER_Pos (11UL)

#define	PDC_PDC_CTRL9_REG_PDC_MASTER_Msk (0x1800UL)

#define	PDC_PDC_CTRL9_REG_EN_COM_Pos (10UL)

#define	PDC_PDC_CTRL9_REG_EN_COM_Msk (0x400UL)

#define	PDC_PDC_CTRL9_REG_EN_PER_Pos (9UL)

#define	PDC_PDC_CTRL9_REG_EN_PER_Msk (0x200UL)

#define	PDC_PDC_CTRL9_REG_EN_TMR_Pos (8UL)

#define	PDC_PDC_CTRL9_REG_EN_TMR_Msk (0x100UL)

#define	PDC_PDC_CTRL9_REG_EN_XTAL_Pos (7UL)

#define	PDC_PDC_CTRL9_REG_EN_XTAL_Msk (0x80UL)

#define	PDC_PDC_CTRL9_REG_TRIG_ID_Pos (2UL)

#define	PDC_PDC_CTRL9_REG_TRIG_ID_Msk (0x7cUL)

#define	PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos (0UL)

#define	PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk (0x3UL)

#define	PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos (0UL)

#define	PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk (0xfffUL)

#define	PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos (0UL)

#define	PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk (0xfffUL)

#define	PDC_PDC_PENDING_REG_PDC_PENDING_Pos (0UL)

#define	PDC_PDC_PENDING_REG_PDC_PENDING_Msk (0xfffUL)

#define	PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos (0UL)

#define	PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk (0x1fUL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL)

#define	QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL)

#define	QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL)

#define	QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL)

#define	QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL)

#define	QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL)

#define	QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL)

#define	QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL)

#define	QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL)

#define	QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL)

#define	QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL)

#define	QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL)

#define	QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL)

#define	QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL)

#define	QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL)

#define	QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL)

#define	QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL)

#define	QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL)

#define	QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL)

#define	QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL)

#define	QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL)

#define	QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL)

#define	QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL)

#define	QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL)

#define	QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL)

#define	QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL)

#define	QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL)

#define	QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL)

#define	QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL)

#define	QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL)

#define	QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL)

#define	QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL)

#define	QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL)

#define	QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL)

#define	QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL)

#define	QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL)

#define	QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL)

#define	QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL)

#define	QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Pos (10UL)

#define	QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Msk (0x400UL)

#define	QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Pos (0UL)

#define	QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Msk (0x3ffUL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Pos (14UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Msk (0x4000UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Pos (13UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Msk (0x2000UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Pos (12UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Msk (0x1000UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Pos (8UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Msk (0xf00UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Pos (4UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Msk (0xf0UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Pos (0UL)

#define	QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Msk (0xfUL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Pos (3UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Msk (0x7f8UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Pos (2UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Msk (0x4UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Pos (1UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Msk (0x2UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Pos (0UL)

#define	QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Msk (0x1UL)

#define	QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Pos (0UL)

#define	QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Msk (0xffUL)

#define	QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Pos (0UL)

#define	QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Msk (0xffffUL)

#define	QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Pos (0UL)

#define	QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Msk (0xffffUL)

#define	QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Pos (0UL)

#define	QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Msk (0xffffUL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos (5UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk (0x20UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos (4UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk (0x10UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos (3UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk (0x8UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos (2UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk (0x4UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos (1UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk (0x2UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos (0UL)

#define	RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk (0x1UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos (12UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk (0x3000UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos (8UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk (0xf00UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos (7UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk (0x80UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos (3UL)

#define	RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk (0x78UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos (31UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk (0x80000000UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos (28UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk (0x30000000UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos (24UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk (0xf000000UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos (20UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk (0xf00000UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos (16UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk (0xf0000UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos (12UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk (0x3000UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos (8UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk (0xf00UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos (7UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk (0x80UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos (3UL)

#define	RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk (0x78UL)

#define	RTC_RTC_CALENDAR_REG_RTC_DAY_Pos (0UL)

#define	RTC_RTC_CALENDAR_REG_RTC_DAY_Msk (0x7UL)

#define	RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos (1UL)

#define	RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk (0x2UL)

#define	RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos (0UL)

#define	RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk (0x1UL)

#define	RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos (1UL)

#define	RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk (0x2UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos (6UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk (0x40UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos (5UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk (0x20UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos (4UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk (0x10UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos (3UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk (0x8UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos (2UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk (0x4UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos (1UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk (0x2UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos (0UL)

#define	RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk (0x1UL)

#define	RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos (0UL)

#define	RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk (0x1UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos (6UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk (0x40UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos (5UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk (0x20UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos (4UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk (0x10UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos (3UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk (0x8UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos (2UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk (0x4UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos (1UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk (0x2UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos (0UL)

#define	RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk (0x1UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos (6UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk (0x40UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos (5UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk (0x20UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos (4UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk (0x10UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos (3UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk (0x8UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos (2UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk (0x4UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos (1UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk (0x2UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos (0UL)

#define	RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk (0x1UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos (6UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk (0x40UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos (5UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk (0x20UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos (4UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk (0x10UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos (3UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk (0x8UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos (2UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk (0x4UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos (1UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk (0x2UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos (0UL)

#define	RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk (0x1UL)

#define	RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos (0UL)

#define	RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk (0x1UL)

#define	RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos (0UL)

#define	RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk (0x1UL)

#define	RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos (0UL)

#define	RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk (0x1fffUL)

#define	RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos (0UL)

#define	RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk (0x1fffUL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos (3UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk (0x8UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos (2UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk (0x4UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos (1UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk (0x2UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos (0UL)

#define	RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk (0x1UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos (30UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk (0x40000000UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos (28UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk (0x30000000UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos (24UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk (0xf000000UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos (20UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk (0x700000UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos (16UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk (0xf0000UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos (12UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk (0x7000UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos (8UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk (0xf00UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos (4UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk (0xf0UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos (0UL)

#define	RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk (0xfUL)

#define	RTC_RTC_TIME_REG_RTC_TIME_CH_Pos (31UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_CH_Msk (0x80000000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_PM_Pos (30UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_PM_Msk (0x40000000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos (28UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk (0x30000000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos (24UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk (0xf000000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos (20UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk (0x700000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos (16UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk (0xf0000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos (12UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk (0x7000UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos (8UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk (0xf00UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos (4UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk (0xf0UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos (0UL)

#define	RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk (0xfUL)

#define	SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Pos (0UL)

#define	SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Msk (0x1fffffUL)

#define	SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos (0UL)

#define	SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk (0xffffffffUL)

#define	SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Pos (20UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Msk (0x100000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_MODE_Pos (19UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_MODE_Msk (0x80000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos (18UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk (0x40000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos (17UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk (0x20000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_INT_Pos (16UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_INT_Msk (0x10000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos (15UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk (0x8000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos (13UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk (0x6000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos (12UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk (0x1000UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos (10UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk (0xc00UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_SE_Pos (9UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_SE_Msk (0x200UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos (6UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk (0x1c0UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos (2UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk (0x3cUL)

#define	SDADC_SDADC_CTRL_REG_SDADC_START_Pos (1UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_START_Msk (0x2UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_EN_Pos (0UL)

#define	SDADC_SDADC_CTRL_REG_SDADC_EN_Msk (0x1UL)

#define	SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos (0UL)

#define	SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk (0x3ffUL)

#define	SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos (0UL)

#define	SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk (0x3ffUL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Pos (9UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Msk (0xe00UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Pos (7UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Msk (0x180UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Pos (6UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Msk (0x40UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Pos (3UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Msk (0x38UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Pos (2UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Msk (0x4UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Pos (0UL)

#define	SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Msk (0x3UL)

#define	SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos (0UL)

#define	SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk (0xffffUL)

#define	SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Pos (0UL)

#define	SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Msk (0x7fUL)

#define	SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Pos (7UL)

#define	SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Msk (0x80UL)

#define	SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Pos (2UL)

#define	SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Msk (0x7cUL)

#define	SPI_SPI_CONFIG_REG_SPI_MODE_Pos (0UL)

#define	SPI_SPI_CONFIG_REG_SPI_MODE_Msk (0x3UL)

#define	SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Pos (0UL)

#define	SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Msk (0x7UL)

#define	SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Pos (7UL)

#define	SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Msk (0x80UL)

#define	SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos (6UL)

#define	SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Msk (0x40UL)

#define	SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Pos (5UL)

#define	SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Msk (0x20UL)

#define	SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Pos (4UL)

#define	SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Msk (0x10UL)

#define	SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Pos (3UL)

#define	SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Msk (0x8UL)

#define	SPI_SPI_CTRL_REG_SPI_RX_EN_Pos (2UL)

#define	SPI_SPI_CTRL_REG_SPI_RX_EN_Msk (0x4UL)

#define	SPI_SPI_CTRL_REG_SPI_TX_EN_Pos (1UL)

#define	SPI_SPI_CTRL_REG_SPI_TX_EN_Msk (0x2UL)

#define	SPI_SPI_CTRL_REG_SPI_EN_Pos (0UL)

#define	SPI_SPI_CTRL_REG_SPI_EN_Msk (0x1UL)

#define	SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Pos (4UL)

#define	SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Msk (0xf0UL)

#define	SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Pos (0UL)

#define	SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Msk (0xfUL)

#define	SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Pos (0UL)

#define	SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Msk (0xffffffffUL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Pos (15UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Msk (0x8000UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Pos (14UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Msk (0x4000UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Pos (13UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Msk (0x2000UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Pos (12UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Msk (0x1000UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Pos (6UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Msk (0xfc0UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Pos (0UL)

#define	SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Msk (0x3fUL)

#define	SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Pos (0UL)

#define	SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Msk (0xffffffffUL)

#define	SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Pos (1UL)

#define	SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk (0x2UL)

#define	SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Pos (0UL)

#define	SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk (0x1UL)

#define	SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Pos (1UL)

#define	SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Msk (0x2UL)

#define	SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Pos (0UL)

#define	SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk (0x1UL)

#define	SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Pos (0UL)

#define	SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Msk (0xffffffffUL)

#define	SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)

#define	SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)

#define	SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)

#define	SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)

#define	SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)

#define	SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)

#define	SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)

#define	SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)

#define	SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)

#define	SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)

#define	SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)

#define	SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)

#define	SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)

#define	SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)

#define	SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)

#define	SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)

#define	SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)

#define	SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)

#define	SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)

#define	SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)

#define	SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)

#define	SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL)

#define	SRC1_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_US_Pos (16UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)

#define	SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)

#define	SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)

#define	SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)

#define	SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)

#define	SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)

#define	SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)

#define	SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_OK_Pos (6UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_OK_Msk (0x40UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_DS_Pos (4UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_DS_Msk (0x30UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)

#define	SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL)

#define	SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)

#define	SRC1_SRC1_CTRL_REG_SRC_EN_Pos (0UL)

#define	SRC1_SRC1_CTRL_REG_SRC_EN_Msk (0x1UL)

#define	SRC1_SRC1_IN1_REG_SRC_IN_Pos (0UL)

#define	SRC1_SRC1_IN1_REG_SRC_IN_Msk (0xffffffffUL)

#define	SRC1_SRC1_IN2_REG_SRC_IN_Pos (0UL)

#define	SRC1_SRC1_IN2_REG_SRC_IN_Msk (0xffffffffUL)

#define	SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL)

#define	SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL)

#define	SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Pos (6UL)

#define	SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Msk (0x40UL)

#define	SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Pos (3UL)

#define	SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Msk (0x38UL)

#define	SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Pos (0UL)

#define	SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Msk (0x7UL)

#define	SRC1_SRC1_OUT1_REG_SRC_OUT_Pos (0UL)

#define	SRC1_SRC1_OUT1_REG_SRC_OUT_Msk (0xffffffffUL)

#define	SRC1_SRC1_OUT2_REG_SRC_OUT_Pos (0UL)

#define	SRC1_SRC1_OUT2_REG_SRC_OUT_Msk (0xffffffffUL)

#define	SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)

#define	SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)

#define	SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)

#define	SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)

#define	SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)

#define	SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)

#define	SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)

#define	SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)

#define	SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)

#define	SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)

#define	SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)

#define	SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)

#define	SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)

#define	SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)

#define	SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)

#define	SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)

#define	SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)

#define	SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)

#define	SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)

#define	SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)

#define	SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)

#define	SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)

#define	SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)

#define	SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)

#define	SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Pos (28UL)

#define	SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_RESYNC_Pos (19UL)

#define	SRC2_SRC2_CTRL_REG_SRC_RESYNC_Msk (0x80000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Pos (18UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_US_Pos (16UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_US_Msk (0x30000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)

#define	SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)

#define	SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)

#define	SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)

#define	SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)

#define	SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)

#define	SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)

#define	SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)

#define	SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_OK_Pos (6UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_OK_Msk (0x40UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_DS_Pos (4UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_DS_Msk (0x30UL)

#define	SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)

#define	SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Pos (1UL)

#define	SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)

#define	SRC2_SRC2_CTRL_REG_SRC_EN_Pos (0UL)

#define	SRC2_SRC2_CTRL_REG_SRC_EN_Msk (0x1UL)

#define	SRC2_SRC2_IN1_REG_SRC_IN_Pos (0UL)

#define	SRC2_SRC2_IN1_REG_SRC_IN_Msk (0xffffffffUL)

#define	SRC2_SRC2_IN2_REG_SRC_IN_Pos (0UL)

#define	SRC2_SRC2_IN2_REG_SRC_IN_Msk (0xffffffffUL)

#define	SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Pos (0UL)

#define	SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL)

#define	SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Pos (6UL)

#define	SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Msk (0x40UL)

#define	SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Pos (3UL)

#define	SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Msk (0x38UL)

#define	SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Pos (0UL)

#define	SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Msk (0x7UL)

#define	SRC2_SRC2_OUT1_REG_SRC_OUT_Pos (0UL)

#define	SRC2_SRC2_OUT1_REG_SRC_OUT_Msk (0xffffffffUL)

#define	SRC2_SRC2_OUT2_REG_SRC_OUT_Pos (0UL)

#define	SRC2_SRC2_OUT2_REG_SRC_OUT_Msk (0xffffffffUL)

#define	SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)

#define	SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)

#define	SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL)

#define	SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL)

#define	SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL)

#define	SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL)

#define	SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL)

#define	SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL)

#define	SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL)

#define	SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL)

#define	SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL)

#define	SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL)

#define	SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL)

#define	SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL)

#define	SYSB_BRIDGE_REG_SYNC_BYPASS_Pos (1UL)

#define	SYSB_BRIDGE_REG_SYNC_BYPASS_Msk (0x2UL)

#define	SYSB_BRIDGE_REG_BRIDGE_BYPASS_Pos (0UL)

#define	SYSB_BRIDGE_REG_BRIDGE_BYPASS_Msk (0x1UL)

#define	SYSB_FLASH_ARB_REG_ENABLE_SEQ_Pos (0UL)

#define	SYSB_FLASH_ARB_REG_ENABLE_SEQ_Msk (0x1UL)

#define	SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Pos (6UL)

#define	SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Msk (0xc0UL)

#define	SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Pos (4UL)

#define	SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Msk (0x30UL)

#define	SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Pos (2UL)

#define	SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Msk (0xcUL)

#define	SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Pos (0UL)

#define	SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Msk (0x3UL)

#define	TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

#define	TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

#define	TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

#define	TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

#define	TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos (0UL)

#define	TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk (0xffffffUL)

#define	TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos (0UL)

#define	TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk (0xffffffUL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL)

#define	TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL)

#define	TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

#define	TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL)

#define	TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

#define	TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

#define	TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

#define	TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

#define	TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

#define	TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

#define	TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

#define	TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

#define	TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)

#define	TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)

#define	TIMER_TIMER_CTRL_REG_TIM_EN_Pos (0UL)

#define	TIMER_TIMER_CTRL_REG_TIM_EN_Msk (0x1UL)

#define	TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

#define	TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

#define	TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

#define	TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

#define	TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL)

#define	TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL)

#define	TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL)

#define	TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL)

#define	TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

#define	TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

#define	TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

#define	TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

#define	TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

#define	TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

#define	TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

#define	TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

#define	TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

#define	TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

#define	TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)

#define	TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Pos (13UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Msk (0x2000UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Pos (12UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Msk (0x1000UL)

#define	TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

#define	TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

#define	TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

#define	TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

#define	TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

#define	TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL)

#define	TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL)

#define	TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

#define	TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

#define	TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

#define	TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

#define	TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

#define	TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

#define	TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

#define	TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

#define	TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

#define	TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

#define	TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL)

#define	TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL)

#define	TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

#define	TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

#define	TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

#define	TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

#define	TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

#define	TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

#define	TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

#define	TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

#define	TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

#define	TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

#define	TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

#define	TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

#define	TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

#define	TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

#define	TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)

#define	TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

#define	TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

#define	TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

#define	TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

#define	TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

#define	TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

#define	TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

#define	TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

#define	TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

#define	TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL)

#define	TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL)

#define	TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

#define	TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

#define	TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

#define	TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

#define	TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

#define	TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

#define	TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

#define	TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

#define	TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

#define	TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

#define	TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

#define	TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

#define	TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

#define	TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

#define	TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

#define	TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

#define	TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

#define	TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

#define	TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

#define	TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

#define	TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

#define	TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

#define	TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL)

#define	TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL)

#define	TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

#define	TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

#define	TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

#define	TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

#define	TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

#define	TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

#define	TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

#define	TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

#define	TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

#define	TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

#define	TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

#define	TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

#define	TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

#define	TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

#define	TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

#define	TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

#define	TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

#define	UART_UART_CTR_REG_UART_CTR_Pos (0UL)

#define	UART_UART_CTR_REG_UART_CTR_Msk (0xffffffffUL)

#define	UART_UART_DLF_REG_UART_DLF_Pos (0UL)

#define	UART_UART_DLF_REG_UART_DLF_Msk (0xfUL)

#define	UART_UART_DMASA_REG_UART_DMASA_Pos (0UL)

#define	UART_UART_DMASA_REG_UART_DMASA_Msk (0x1UL)

#define	UART_UART_HTX_REG_UART_HALT_TX_Pos (0UL)

#define	UART_UART_HTX_REG_UART_HALT_TX_Msk (0x1UL)

#define	UART_UART_IER_DLH_REG_PTIME_DLH7_Pos (7UL)

#define	UART_UART_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)

#define	UART_UART_IER_DLH_REG_DLH6_5_Pos (5UL)

#define	UART_UART_IER_DLH_REG_DLH6_5_Msk (0x60UL)

#define	UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)

#define	UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)

#define	UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)

#define	UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)

#define	UART_UART_IER_DLH_REG_ELSI_DLH2_Pos (2UL)

#define	UART_UART_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)

#define	UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)

#define	UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)

#define	UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)

#define	UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)

#define	UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL)

#define	UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)

#define	UART_UART_LCR_REG_UART_DLAB_Pos (7UL)

#define	UART_UART_LCR_REG_UART_DLAB_Msk (0x80UL)

#define	UART_UART_LCR_REG_UART_BC_Pos (6UL)

#define	UART_UART_LCR_REG_UART_BC_Msk (0x40UL)

#define	UART_UART_LCR_REG_UART_EPS_Pos (4UL)

#define	UART_UART_LCR_REG_UART_EPS_Msk (0x10UL)

#define	UART_UART_LCR_REG_UART_PEN_Pos (3UL)

#define	UART_UART_LCR_REG_UART_PEN_Msk (0x8UL)

#define	UART_UART_LCR_REG_UART_STOP_Pos (2UL)

#define	UART_UART_LCR_REG_UART_STOP_Msk (0x4UL)

#define	UART_UART_LCR_REG_UART_DLS_Pos (0UL)

#define	UART_UART_LCR_REG_UART_DLS_Msk (0x3UL)

#define	UART_UART_LSR_REG_UART_RFE_Pos (7UL)

#define	UART_UART_LSR_REG_UART_RFE_Msk (0x80UL)

#define	UART_UART_LSR_REG_UART_TEMT_Pos (6UL)

#define	UART_UART_LSR_REG_UART_TEMT_Msk (0x40UL)

#define	UART_UART_LSR_REG_UART_THRE_Pos (5UL)

#define	UART_UART_LSR_REG_UART_THRE_Msk (0x20UL)

#define	UART_UART_LSR_REG_UART_BI_Pos (4UL)

#define	UART_UART_LSR_REG_UART_BI_Msk (0x10UL)

#define	UART_UART_LSR_REG_UART_FE_Pos (3UL)

#define	UART_UART_LSR_REG_UART_FE_Msk (0x8UL)

#define	UART_UART_LSR_REG_UART_PE_Pos (2UL)

#define	UART_UART_LSR_REG_UART_PE_Msk (0x4UL)

#define	UART_UART_LSR_REG_UART_OE_Pos (1UL)

#define	UART_UART_LSR_REG_UART_OE_Msk (0x2UL)

#define	UART_UART_LSR_REG_UART_DR_Pos (0UL)

#define	UART_UART_LSR_REG_UART_DR_Msk (0x1UL)

#define	UART_UART_MCR_REG_UART_LB_Pos (4UL)

#define	UART_UART_MCR_REG_UART_LB_Msk (0x10UL)

#define	UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)

#define	UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)

#define	UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)

#define	UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)

#define	UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)

#define	UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)

#define	UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)

#define	UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)

#define	UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)

#define	UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)

#define	UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)

#define	UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)

#define	UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)

#define	UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART_UART_SRR_REG_UART_XFR_Pos (2UL)

#define	UART_UART_SRR_REG_UART_XFR_Msk (0x4UL)

#define	UART_UART_SRR_REG_UART_RFR_Pos (1UL)

#define	UART_UART_SRR_REG_UART_RFR_Msk (0x2UL)

#define	UART_UART_SRR_REG_UART_UR_Pos (0UL)

#define	UART_UART_SRR_REG_UART_UR_Msk (0x1UL)

#define	UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)

#define	UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)

#define	UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)

#define	UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)

#define	UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)

#define	UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)

#define	UART_UART_UCV_REG_UART_UCV_Pos (0UL)

#define	UART_UART_UCV_REG_UART_UCV_Msk (0xffffffffUL)

#define	UART_UART_USR_REG_UART_RFF_Pos (4UL)

#define	UART_UART_USR_REG_UART_RFF_Msk (0x10UL)

#define	UART_UART_USR_REG_UART_RFNE_Pos (3UL)

#define	UART_UART_USR_REG_UART_RFNE_Msk (0x8UL)

#define	UART_UART_USR_REG_UART_TFE_Pos (2UL)

#define	UART_UART_USR_REG_UART_TFE_Msk (0x4UL)

#define	UART_UART_USR_REG_UART_TFNF_Pos (1UL)

#define	UART_UART_USR_REG_UART_TFNF_Msk (0x2UL)

#define	UART_UART_USR_REG_UART_BUSY_Pos (0UL)

#define	UART_UART_USR_REG_UART_BUSY_Msk (0x1UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos (3UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk (0xf8UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Pos (2UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Msk (0x4UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos (1UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk (0x2UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Pos (0UL)

#define	UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Msk (0x1UL)

#define	UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Pos (11UL)

#define	UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Msk (0x800UL)

#define	UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos (10UL)

#define	UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk (0x400UL)

#define	UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos (9UL)

#define	UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk (0x200UL)

#define	UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos (8UL)

#define	UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk (0x100UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Pos (7UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Msk (0x80UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Pos (6UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Msk (0x40UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Pos (5UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Msk (0x20UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Pos (0UL)

#define	UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Msk (0x1fUL)

#define	UART2_UART2_CTR_REG_UART_CTR_Pos (0UL)

#define	UART2_UART2_CTR_REG_UART_CTR_Msk (0xffffffffUL)

#define	UART2_UART2_DLF_REG_UART_DLF_Pos (0UL)

#define	UART2_UART2_DLF_REG_UART_DLF_Msk (0xfUL)

#define	UART2_UART2_DMASA_REG_UART_DMASA_Pos (0UL)

#define	UART2_UART2_DMASA_REG_UART_DMASA_Msk (0x1UL)

#define	UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos (4UL)

#define	UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk (0x1f0UL)

#define	UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos (0UL)

#define	UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk (0xfUL)

#define	UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL)

#define	UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL)

#define	UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos (7UL)

#define	UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)

#define	UART2_UART2_IER_DLH_REG_DLH6_5_Pos (5UL)

#define	UART2_UART2_IER_DLH_REG_DLH6_5_Msk (0x60UL)

#define	UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)

#define	UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)

#define	UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)

#define	UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)

#define	UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos (2UL)

#define	UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)

#define	UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)

#define	UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)

#define	UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)

#define	UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)

#define	UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL)

#define	UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)

#define	UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos (2UL)

#define	UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk (0x4UL)

#define	UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos (1UL)

#define	UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk (0x2UL)

#define	UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos (0UL)

#define	UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk (0x1UL)

#define	UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL)

#define	UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL)

#define	UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos (2UL)

#define	UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL)

#define	UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos (1UL)

#define	UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL)

#define	UART2_UART2_LCR_EXT_UART_DLS_E_Pos (0UL)

#define	UART2_UART2_LCR_EXT_UART_DLS_E_Msk (0x1UL)

#define	UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL)

#define	UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL)

#define	UART2_UART2_LCR_REG_UART_BC_Pos (6UL)

#define	UART2_UART2_LCR_REG_UART_BC_Msk (0x40UL)

#define	UART2_UART2_LCR_REG_UART_SP_Pos (5UL)

#define	UART2_UART2_LCR_REG_UART_SP_Msk (0x20UL)

#define	UART2_UART2_LCR_REG_UART_EPS_Pos (4UL)

#define	UART2_UART2_LCR_REG_UART_EPS_Msk (0x10UL)

#define	UART2_UART2_LCR_REG_UART_PEN_Pos (3UL)

#define	UART2_UART2_LCR_REG_UART_PEN_Msk (0x8UL)

#define	UART2_UART2_LCR_REG_UART_STOP_Pos (2UL)

#define	UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL)

#define	UART2_UART2_LCR_REG_UART_DLS_Pos (0UL)

#define	UART2_UART2_LCR_REG_UART_DLS_Msk (0x3UL)

#define	UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos (8UL)

#define	UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL)

#define	UART2_UART2_LSR_REG_UART_RFE_Pos (7UL)

#define	UART2_UART2_LSR_REG_UART_RFE_Msk (0x80UL)

#define	UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL)

#define	UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL)

#define	UART2_UART2_LSR_REG_UART_THRE_Pos (5UL)

#define	UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL)

#define	UART2_UART2_LSR_REG_UART_BI_Pos (4UL)

#define	UART2_UART2_LSR_REG_UART_BI_Msk (0x10UL)

#define	UART2_UART2_LSR_REG_UART_FE_Pos (3UL)

#define	UART2_UART2_LSR_REG_UART_FE_Msk (0x8UL)

#define	UART2_UART2_LSR_REG_UART_PE_Pos (2UL)

#define	UART2_UART2_LSR_REG_UART_PE_Msk (0x4UL)

#define	UART2_UART2_LSR_REG_UART_OE_Pos (1UL)

#define	UART2_UART2_LSR_REG_UART_OE_Msk (0x2UL)

#define	UART2_UART2_LSR_REG_UART_DR_Pos (0UL)

#define	UART2_UART2_LSR_REG_UART_DR_Msk (0x1UL)

#define	UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL)

#define	UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL)

#define	UART2_UART2_MCR_REG_UART_LB_Pos (4UL)

#define	UART2_UART2_MCR_REG_UART_LB_Msk (0x10UL)

#define	UART2_UART2_MCR_REG_UART_RTS_Pos (1UL)

#define	UART2_UART2_MCR_REG_UART_RTS_Msk (0x2UL)

#define	UART2_UART2_MSR_REG_UART_CTS_Pos (4UL)

#define	UART2_UART2_MSR_REG_UART_CTS_Msk (0x10UL)

#define	UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL)

#define	UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL)

#define	UART2_UART2_RAR_REG_UART_RAR_Pos (0UL)

#define	UART2_UART2_RAR_REG_UART_RAR_Msk (0xffUL)

#define	UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL)

#define	UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL)

#define	UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)

#define	UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)

#define	UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)

#define	UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)

#define	UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)

#define	UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)

#define	UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)

#define	UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)

#define	UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)

#define	UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)

#define	UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)

#define	UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)

#define	UART2_UART2_SRR_REG_UART_XFR_Pos (2UL)

#define	UART2_UART2_SRR_REG_UART_XFR_Msk (0x4UL)

#define	UART2_UART2_SRR_REG_UART_RFR_Pos (1UL)

#define	UART2_UART2_SRR_REG_UART_RFR_Msk (0x2UL)

#define	UART2_UART2_SRR_REG_UART_UR_Pos (0UL)

#define	UART2_UART2_SRR_REG_UART_UR_Msk (0x1UL)

#define	UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL)

#define	UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL)

#define	UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)

#define	UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)

#define	UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)

#define	UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)

#define	UART2_UART2_TAR_REG_UART_TAR_Pos (0UL)

#define	UART2_UART2_TAR_REG_UART_TAR_Msk (0xffUL)

#define	UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)

#define	UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)

#define	UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Pos (17UL)

#define	UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Msk (0x20000UL)

#define	UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Pos (16UL)

#define	UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Msk (0x10000UL)

#define	UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Pos (0UL)

#define	UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Msk (0xffffUL)

#define	UART2_UART2_UCV_REG_UART_UCV_Pos (0UL)

#define	UART2_UART2_UCV_REG_UART_UCV_Msk (0xffffffffUL)

#define	UART2_UART2_USR_REG_UART_RFF_Pos (4UL)

#define	UART2_UART2_USR_REG_UART_RFF_Msk (0x10UL)

#define	UART2_UART2_USR_REG_UART_RFNE_Pos (3UL)

#define	UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL)

#define	UART2_UART2_USR_REG_UART_TFE_Pos (2UL)

#define	UART2_UART2_USR_REG_UART_TFE_Msk (0x4UL)

#define	UART2_UART2_USR_REG_UART_TFNF_Pos (1UL)

#define	UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL)

#define	UART2_UART2_USR_REG_UART_BUSY_Pos (0UL)

#define	UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL)

#define	WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos (0UL)

#define	WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk (0xffffUL)

#define	WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos (0UL)

#define	WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk (0xffffUL)

#define	WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL)

#define	WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL)

#define	WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL)

#define	WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL)

#define	WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL)

#define	WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL)

#define	WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL)

#define	WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffffUL)

#define	WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL)

#define	WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0xffffUL)

#define	WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL)

#define	WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL)

#define	WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Pos (0UL)

#define	WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Msk (0xffffUL)

#define	WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Pos (0UL)

#define	WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Msk (0xffffUL)

#define	WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL)

#define	WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffffUL)

#define	WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL)

#define	WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0xffffUL)

#define	WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL)

#define	WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffffUL)

#define	WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL)

#define	WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0xffffUL)

#define	WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos (0UL)

#define	WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk (0xffffUL)

#define	WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos (0UL)

#define	WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk (0xffffUL)

Detailed Description

Peripheral Device Register Mask Positioning.

Macro Definition Documentation

◆ AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk

#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk (0x1UL)

CRYPTO_CLRIRQ (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos

#define AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos (0UL)

CRYPTO_CLRIRQ (Bit 0)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk (0x10000UL)

CRYPTO_AES_KEXP (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos (16UL)

CRYPTO_AES_KEXP (Bit 16)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk (0x60UL)

CRYPTO_AES_KEY_SZ (Bitfield-Mask: 0x03)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos (5UL)

CRYPTO_AES_KEY_SZ (Bit 5)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk (0xcUL)

CRYPTO_ALG_MD (Bitfield-Mask: 0x03)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos (2UL)

CRYPTO_ALG_MD (Bit 2)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk (0x3UL)

CRYPTO_ALG (Bitfield-Mask: 0x03)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos (0UL)

CRYPTO_ALG (Bit 0)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk (0x80UL)

CRYPTO_ENCDEC (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos (7UL)

CRYPTO_ENCDEC (Bit 7)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk (0x7c00UL)

CRYPTO_HASH_OUT_LEN (Bitfield-Mask: 0x1f)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos (10UL)

CRYPTO_HASH_OUT_LEN (Bit 10)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk (0x200UL)

CRYPTO_HASH_SEL (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos (9UL)

CRYPTO_HASH_SEL (Bit 9)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk (0x100UL)

CRYPTO_IRQ_EN (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos (8UL)

CRYPTO_IRQ_EN (Bit 8)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk (0x8000UL)

CRYPTO_MORE_IN (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos (15UL)

CRYPTO_MORE_IN (Bit 15)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk (0x10UL)

CRYPTO_OUT_MD (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos

#define AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos (4UL)

CRYPTO_OUT_MD (Bit 4)

◆ AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk

#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk (0xffffffffUL)

CRYPTO_DEST_ADDR (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos

#define AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos (0UL)

CRYPTO_DEST_ADDR (Bit 0)

◆ AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk

#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk (0xffffffffUL)

CRYPTO_FETCH_ADDR (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos

#define AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos (0UL)

CRYPTO_FETCH_ADDR (Bit 0)

◆ AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk

#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk (0xffffffffUL)

CRYPTO_KEY_X (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos

#define AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos (0UL)

CRYPTO_KEY_X (Bit 0)

◆ AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk

#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk (0xffffffUL)

CRYPTO_LEN (Bitfield-Mask: 0xffffff)

◆ AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos

#define AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos (0UL)

CRYPTO_LEN (Bit 0)

◆ AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk

#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk (0xffffffffUL)

CRYPTO_MREG0 (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos

#define AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos (0UL)

CRYPTO_MREG0 (Bit 0)

◆ AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk

#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk (0xffffffffUL)

CRYPTO_MREG1 (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos

#define AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos (0UL)

CRYPTO_MREG1 (Bit 0)

◆ AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk

#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk (0xffffffffUL)

CRYPTO_MREG2 (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos

#define AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos (0UL)

CRYPTO_MREG2 (Bit 0)

◆ AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk

#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk (0xffffffffUL)

CRYPTO_MREG3 (Bitfield-Mask: 0xffffffff)

◆ AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos

#define AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos (0UL)

CRYPTO_MREG3 (Bit 0)

◆ AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk

#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk (0x1UL)

CRYPTO_START (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos

#define AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos (0UL)

CRYPTO_START (Bit 0)

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk (0x1UL)

CRYPTO_INACTIVE (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos (0UL)

CRYPTO_INACTIVE (Bit 0)

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk (0x4UL)

CRYPTO_IRQ_ST (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos (2UL)

CRYPTO_IRQ_ST (Bit 2)

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk (0x2UL)

CRYPTO_WAIT_FOR_IN (Bitfield-Mask: 0x01)

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos

#define AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos (1UL)

CRYPTO_WAIT_FOR_IN (Bit 1)

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Msk

#define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Msk (0x4UL)

CLK_CAL_IRQ_CLR (Bitfield-Mask: 0x01)

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Pos

#define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Pos (2UL)

CLK_CAL_IRQ_CLR (Bit 2)

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Msk

#define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Msk (0x1UL)

CLK_CAL_IRQ_EN (Bitfield-Mask: 0x01)

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Pos

#define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Pos (0UL)

CLK_CAL_IRQ_EN (Bit 0)

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Msk

#define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Msk (0x2UL)

CLK_CAL_IRQ_STATUS (Bitfield-Mask: 0x01)

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Pos

#define ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Pos (1UL)

CLK_CAL_IRQ_STATUS (Bit 1)

◆ ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk

#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk (0xffffUL)

REF_CNT_VAL (Bitfield-Mask: 0xffff)

◆ ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos

#define ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos (0UL)

REF_CNT_VAL (Bit 0)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk

#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk (0xe0UL)

CAL_CLK_SEL (Bitfield-Mask: 0x07)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos

#define ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos (5UL)

CAL_CLK_SEL (Bit 5)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk

#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk (0x10UL)

EXT_CNT_EN_SEL (Bitfield-Mask: 0x01)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos

#define ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos (4UL)

EXT_CNT_EN_SEL (Bit 4)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk

#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk (0x8UL)

REF_CAL_START (Bitfield-Mask: 0x01)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos

#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos (3UL)

REF_CAL_START (Bit 3)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk

#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk (0x7UL)

REF_CLK_SEL (Bitfield-Mask: 0x07)

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos

#define ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos (0UL)

REF_CLK_SEL (Bit 0)

◆ ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk

#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk (0xffffffffUL)

XTAL_CNT_VAL (Bitfield-Mask: 0xffffffff)

◆ ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos

#define ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos (0UL)

XTAL_CNT_VAL (Bit 0)

◆ CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)

CACHE_CGEN (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)

CACHE_CGEN (Bit 10)

◆ CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x1000UL)

CACHE_CWF_DISABLE (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (12UL)

CACHE_CWF_DISABLE (Bit 12)

◆ CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk (0x3fe0000UL)

CACHE_EF_LEN (Bitfield-Mask: 0x1ff)

◆ CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos (17UL)

CACHE_EF_LEN (Bit 17)

◆ CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x10000UL)

CACHE_FLUSH_DISABLE (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (16UL)

CACHE_FLUSH_DISABLE (Bit 16)

◆ CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)

CACHE_LEN (Bitfield-Mask: 0x1ff)

◆ CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)

CACHE_LEN (Bit 0)

◆ CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x2000UL)

CACHE_MHCLKEN_DISABLE (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (13UL)

CACHE_MHCLKEN_DISABLE (Bit 13)

◆ CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x8000000UL)

CACHE_RAM_INIT (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (27UL)

CACHE_RAM_INIT (Bit 27)

◆ CACHE_CACHE_CTRL2_REG_CACHE_READY_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_READY_Msk (0x10000000UL)

CACHE_READY (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_READY_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_READY_Pos (28UL)

CACHE_READY (Bit 28)

◆ CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0xc000UL)

CACHE_USE_FULL_DB_RANGE (Bitfield-Mask: 0x03)

◆ CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (14UL)

CACHE_USE_FULL_DB_RANGE (Bit 14)

◆ CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk

#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)

CACHE_WEN (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos

#define CACHE_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)

CACHE_WEN (Bit 9)

◆ CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk

#define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk (0xffff0000UL)

EFLASH_REGION_BASE (Bitfield-Mask: 0xffff)

◆ CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos

#define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos (16UL)

EFLASH_REGION_BASE (Bit 16)

◆ CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk

#define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk (0xfff0UL)

EFLASH_REGION_OFFSET (Bitfield-Mask: 0xfff)

◆ CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos

#define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos (4UL)

EFLASH_REGION_OFFSET (Bit 4)

◆ CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk

#define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk (0x7UL)

EFLASH_REGION_SIZE (Bitfield-Mask: 0x07)

◆ CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos

#define CACHE_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos (0UL)

EFLASH_REGION_SIZE (Bit 0)

◆ CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk

#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)

FLASH_REGION_BASE (Bitfield-Mask: 0xffff)

◆ CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos

#define CACHE_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)

FLASH_REGION_BASE (Bit 16)

◆ CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk

#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)

FLASH_REGION_OFFSET (Bitfield-Mask: 0xfff)

◆ CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos

#define CACHE_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)

FLASH_REGION_OFFSET (Bit 4)

◆ CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk

#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)

FLASH_REGION_SIZE (Bitfield-Mask: 0x07)

◆ CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos

#define CACHE_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)

FLASH_REGION_SIZE (Bit 0)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL)

MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL)

MRM_IRQ_HITS_THRES_STATUS (Bit 4)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)

MRM_IRQ_MASK (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)

MRM_IRQ_MASK (Bit 1)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL)

MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL)

MRM_IRQ_MISSES_THRES_STATUS (Bit 3)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)

MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)

MRM_IRQ_TINT_STATUS (Bit 2)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk

#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)

MRM_START (Bitfield-Mask: 0x01)

◆ CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos

#define CACHE_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)

MRM_START (Bit 0)

◆ CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk

#define CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL)

MRM_HITS1WS (Bitfield-Mask: 0xffffffff)

◆ CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos

#define CACHE_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL)

MRM_HITS1WS (Bit 0)

◆ CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk

#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)

MRM_HITS (Bitfield-Mask: 0xffffffff)

◆ CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos

#define CACHE_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)

MRM_HITS (Bit 0)

◆ CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk

#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL)

MRM_HITS_THRES (Bitfield-Mask: 0xffffffff)

◆ CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos

#define CACHE_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)

MRM_HITS_THRES (Bit 0)

◆ CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk

#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)

MRM_MISSES (Bitfield-Mask: 0xffffffff)

◆ CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos

#define CACHE_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)

MRM_MISSES (Bit 0)

◆ CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk

#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL)

MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff)

◆ CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos

#define CACHE_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL)

MRM_MISSES_THRES (Bit 0)

◆ CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk

#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)

MRM_TINT (Bitfield-Mask: 0x7ffff)

◆ CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos

#define CACHE_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)

MRM_TINT (Bit 0)

◆ CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk

#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)

SWD_HW_RESET_REQ (Bitfield-Mask: 0x01)

◆ CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos

#define CACHE_SWD_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)

SWD_HW_RESET_REQ (Bit 0)

◆ CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk

#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk (0xffUL)

CHIP_ID1 (Bitfield-Mask: 0xff)

◆ CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos

#define CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Pos (0UL)

CHIP_ID1 (Bit 0)

◆ CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk

#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk (0xffUL)

CHIP_ID2 (Bitfield-Mask: 0xff)

◆ CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos

#define CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Pos (0UL)

CHIP_ID2 (Bit 0)

◆ CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk

#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk (0xffUL)

CHIP_ID3 (Bitfield-Mask: 0xff)

◆ CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos

#define CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Pos (0UL)

CHIP_ID3 (Bit 0)

◆ CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk

#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk (0xffUL)

CHIP_ID4 (Bitfield-Mask: 0xff)

◆ CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos

#define CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Pos (0UL)

CHIP_ID4 (Bit 0)

◆ CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk

#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Msk (0xffUL)

CHIP_REVISION (Bitfield-Mask: 0xff)

◆ CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos

#define CHIP_VERSION_CHIP_REVISION_REG_CHIP_REVISION_Pos (0UL)

CHIP_REVISION (Bit 0)

◆ CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk

#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Msk (0xfUL)

CHIP_SWC (Bitfield-Mask: 0x0f)

◆ CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos

#define CHIP_VERSION_CHIP_SWC_REG_CHIP_SWC_Pos (0UL)

CHIP_SWC (Bit 0)

◆ CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk

#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Msk (0xffUL)

CHIP_LAYOUT_REVISION (Bitfield-Mask: 0xff)

◆ CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos

#define CHIP_VERSION_CHIP_TEST1_REG_CHIP_LAYOUT_REVISION_Pos (0UL)

CHIP_LAYOUT_REVISION (Bit 0)

◆ CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk

#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Msk (0xfUL)

CHIP_METAL_OPTION (Bitfield-Mask: 0x0f)

◆ CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos

#define CHIP_VERSION_CHIP_TEST2_REG_CHIP_METAL_OPTION_Pos (0UL)

CHIP_METAL_OPTION (Bit 0)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Msk (0x400UL)

CACHE_CGEN (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CGEN_Pos (10UL)

CACHE_CGEN (Bit 10)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk (0x1000UL)

CACHE_CWF_DISABLE (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos (12UL)

CACHE_CWF_DISABLE (Bit 12)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk (0x3fe0000UL)

CACHE_EF_LEN (Bitfield-Mask: 0x1ff)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos (17UL)

CACHE_EF_LEN (Bit 17)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk (0x10000UL)

CACHE_FLUSH_DISABLE (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos (16UL)

CACHE_FLUSH_DISABLE (Bit 16)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Msk (0x1ffUL)

CACHE_LEN (Bitfield-Mask: 0x1ff)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_LEN_Pos (0UL)

CACHE_LEN (Bit 0)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk (0x2000UL)

CACHE_MHCLKEN_DISABLE (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos (13UL)

CACHE_MHCLKEN_DISABLE (Bit 13)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk (0x8000000UL)

CACHE_RAM_INIT (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_RAM_INIT_Pos (27UL)

CACHE_RAM_INIT (Bit 27)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Msk (0x10000000UL)

CACHE_READY (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_READY_Pos (28UL)

CACHE_READY (Bit 28)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Msk (0xc000UL)

CACHE_USE_FULL_DB_RANGE (Bitfield-Mask: 0x03)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_USE_FULL_DB_RANGE_Pos (14UL)

CACHE_USE_FULL_DB_RANGE (Bit 14)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Msk

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Msk (0x200UL)

CACHE_WEN (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Pos

#define CMAC_CACHE_CM_CACHE_CTRL2_REG_CACHE_WEN_Pos (9UL)

CACHE_WEN (Bit 9)

◆ CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk

#define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Msk (0xffff0000UL)

EFLASH_REGION_BASE (Bitfield-Mask: 0xffff)

◆ CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos

#define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_BASE_Pos (16UL)

EFLASH_REGION_BASE (Bit 16)

◆ CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk

#define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Msk (0xfff0UL)

EFLASH_REGION_OFFSET (Bitfield-Mask: 0xfff)

◆ CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos

#define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_OFFSET_Pos (4UL)

EFLASH_REGION_OFFSET (Bit 4)

◆ CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk

#define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Msk (0x7UL)

EFLASH_REGION_SIZE (Bitfield-Mask: 0x07)

◆ CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos

#define CMAC_CACHE_CM_CACHE_EFLASH_REG_EFLASH_REGION_SIZE_Pos (0UL)

EFLASH_REGION_SIZE (Bit 0)

◆ CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk

#define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Msk (0xffff0000UL)

FLASH_REGION_BASE (Bitfield-Mask: 0xffff)

◆ CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos

#define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_BASE_Pos (16UL)

FLASH_REGION_BASE (Bit 16)

◆ CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk

#define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Msk (0xfff0UL)

FLASH_REGION_OFFSET (Bitfield-Mask: 0xfff)

◆ CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos

#define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_OFFSET_Pos (4UL)

FLASH_REGION_OFFSET (Bit 4)

◆ CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk

#define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Msk (0x7UL)

FLASH_REGION_SIZE (Bitfield-Mask: 0x07)

◆ CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos

#define CMAC_CACHE_CM_CACHE_FLASH_REG_FLASH_REGION_SIZE_Pos (0UL)

FLASH_REGION_SIZE (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Msk (0x10UL)

MRM_IRQ_HITS_THRES_STATUS (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_HITS_THRES_STATUS_Pos (4UL)

MRM_IRQ_HITS_THRES_STATUS (Bit 4)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Msk (0x2UL)

MRM_IRQ_MASK (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MASK_Pos (1UL)

MRM_IRQ_MASK (Bit 1)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Msk (0x8UL)

MRM_IRQ_MISSES_THRES_STATUS (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_MISSES_THRES_STATUS_Pos (3UL)

MRM_IRQ_MISSES_THRES_STATUS (Bit 3)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Msk (0x4UL)

MRM_IRQ_TINT_STATUS (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_IRQ_TINT_STATUS_Pos (2UL)

MRM_IRQ_TINT_STATUS (Bit 2)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Msk

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Msk (0x1UL)

MRM_START (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Pos

#define CMAC_CACHE_CM_CACHE_MRM_CTRL_REG_MRM_START_Pos (0UL)

MRM_START (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk

#define CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Msk (0xffffffffUL)

MRM_HITS1WS (Bitfield-Mask: 0xffffffff)

◆ CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos

#define CMAC_CACHE_CM_CACHE_MRM_HITS1WS_REG_MRM_HITS1WS_Pos (0UL)

MRM_HITS1WS (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Msk

#define CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Msk (0xffffffffUL)

MRM_HITS (Bitfield-Mask: 0xffffffff)

◆ CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Pos

#define CMAC_CACHE_CM_CACHE_MRM_HITS_REG_MRM_HITS_Pos (0UL)

MRM_HITS (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk

#define CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Msk (0xffffffffUL)

MRM_HITS_THRES (Bitfield-Mask: 0xffffffff)

◆ CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos

#define CMAC_CACHE_CM_CACHE_MRM_HITS_THRES_REG_MRM_HITS_THRES_Pos (0UL)

MRM_HITS_THRES (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk

#define CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Msk (0xffffffffUL)

MRM_MISSES (Bitfield-Mask: 0xffffffff)

◆ CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos

#define CMAC_CACHE_CM_CACHE_MRM_MISSES_REG_MRM_MISSES_Pos (0UL)

MRM_MISSES (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk

#define CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Msk (0xffffffffUL)

MRM_MISSES_THRES (Bitfield-Mask: 0xffffffff)

◆ CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos

#define CMAC_CACHE_CM_CACHE_MRM_MISSES_THRES_REG_MRM_MISSES_THRES_Pos (0UL)

MRM_MISSES_THRES (Bit 0)

◆ CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Msk

#define CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Msk (0x7ffffUL)

MRM_TINT (Bitfield-Mask: 0x7ffff)

◆ CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Pos

#define CMAC_CACHE_CM_CACHE_MRM_TINT_REG_MRM_TINT_Pos (0UL)

MRM_TINT (Bit 0)

◆ CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Msk

#define CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Msk (0x1UL)

SWD_HW_RESET_REQ (Bitfield-Mask: 0x01)

◆ CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Pos

#define CMAC_CACHE_CM_CACHE_RESET_REG_SWD_HW_RESET_REQ_Pos (0UL)

SWD_HW_RESET_REQ (Bit 0)

◆ CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Msk

#define CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Msk (0x1000UL)

CLK_PCM_EN (Bitfield-Mask: 0x01)

◆ CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Pos

#define CRG_AUD_PCM_DIV_REG_CLK_PCM_EN_Pos (12UL)

CLK_PCM_EN (Bit 12)

◆ CRG_AUD_PCM_DIV_REG_PCM_DIV_Msk

#define CRG_AUD_PCM_DIV_REG_PCM_DIV_Msk (0xfffUL)

PCM_DIV (Bitfield-Mask: 0xfff)

◆ CRG_AUD_PCM_DIV_REG_PCM_DIV_Pos

#define CRG_AUD_PCM_DIV_REG_PCM_DIV_Pos (0UL)

PCM_DIV (Bit 0)

◆ CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Msk

#define CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Msk (0x2000UL)

PCM_SRC_SEL (Bitfield-Mask: 0x01)

◆ CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Pos

#define CRG_AUD_PCM_DIV_REG_PCM_SRC_SEL_Pos (13UL)

PCM_SRC_SEL (Bit 13)

◆ CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Msk

#define CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Msk (0xffffUL)

PCM_FDIV (Bitfield-Mask: 0xffff)

◆ CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Pos

#define CRG_AUD_PCM_FDIV_REG_PCM_FDIV_Pos (0UL)

PCM_FDIV (Bit 0)

◆ CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Msk

#define CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Msk (0x100UL)

CLK_PDM_EN (Bitfield-Mask: 0x01)

◆ CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Pos

#define CRG_AUD_PDM_DIV_REG_CLK_PDM_EN_Pos (8UL)

CLK_PDM_EN (Bit 8)

◆ CRG_AUD_PDM_DIV_REG_PDM_DIV_Msk

#define CRG_AUD_PDM_DIV_REG_PDM_DIV_Msk (0xffUL)

PDM_DIV (Bitfield-Mask: 0xff)

◆ CRG_AUD_PDM_DIV_REG_PDM_DIV_Pos

#define CRG_AUD_PDM_DIV_REG_PDM_DIV_Pos (0UL)

PDM_DIV (Bit 0)

◆ CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Msk

#define CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Msk (0x200UL)

PDM_MASTER_MODE (Bitfield-Mask: 0x01)

◆ CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Pos

#define CRG_AUD_PDM_DIV_REG_PDM_MASTER_MODE_Pos (9UL)

PDM_MASTER_MODE (Bit 9)

◆ CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Msk

#define CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Msk (0x20000UL)

CLK_SRC2_EN (Bitfield-Mask: 0x01)

◆ CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Pos

#define CRG_AUD_SRC_DIV_REG_CLK_SRC2_EN_Pos (17UL)

CLK_SRC2_EN (Bit 17)

◆ CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Msk

#define CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Msk (0x10000UL)

CLK_SRC_EN (Bitfield-Mask: 0x01)

◆ CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Pos

#define CRG_AUD_SRC_DIV_REG_CLK_SRC_EN_Pos (16UL)

CLK_SRC_EN (Bit 16)

◆ CRG_AUD_SRC_DIV_REG_SRC2_DIV_Msk

#define CRG_AUD_SRC_DIV_REG_SRC2_DIV_Msk (0xff00UL)

SRC2_DIV (Bitfield-Mask: 0xff)

◆ CRG_AUD_SRC_DIV_REG_SRC2_DIV_Pos

#define CRG_AUD_SRC_DIV_REG_SRC2_DIV_Pos (8UL)

SRC2_DIV (Bit 8)

◆ CRG_AUD_SRC_DIV_REG_SRC_DIV_Msk

#define CRG_AUD_SRC_DIV_REG_SRC_DIV_Msk (0xffUL)

SRC_DIV (Bitfield-Mask: 0xff)

◆ CRG_AUD_SRC_DIV_REG_SRC_DIV_Pos

#define CRG_AUD_SRC_DIV_REG_SRC_DIV_Pos (0UL)

SRC_DIV (Bit 0)

◆ CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk

#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)

I2C_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos

#define CRG_COM_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)

I2C_CLK_SEL (Bit 7)

◆ CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk

#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)

I2C_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos

#define CRG_COM_CLK_COM_REG_I2C_ENABLE_Pos (6UL)

I2C_ENABLE (Bit 6)

◆ CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk

#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)

SPI_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos

#define CRG_COM_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)

SPI_CLK_SEL (Bit 5)

◆ CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk

#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)

SPI_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos

#define CRG_COM_CLK_COM_REG_SPI_ENABLE_Pos (4UL)

SPI_ENABLE (Bit 4)

◆ CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk

#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)

UART2_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos

#define CRG_COM_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)

UART2_CLK_SEL (Bit 3)

◆ CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk

#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)

UART2_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos

#define CRG_COM_CLK_COM_REG_UART2_ENABLE_Pos (2UL)

UART2_ENABLE (Bit 2)

◆ CRG_COM_CLK_COM_REG_UART_CLK_SEL_Msk

#define CRG_COM_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)

UART_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_UART_CLK_SEL_Pos

#define CRG_COM_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)

UART_CLK_SEL (Bit 1)

◆ CRG_COM_CLK_COM_REG_UART_ENABLE_Msk

#define CRG_COM_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)

UART_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_CLK_COM_REG_UART_ENABLE_Pos

#define CRG_COM_CLK_COM_REG_UART_ENABLE_Pos (0UL)

UART_ENABLE (Bit 0)

◆ CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk

#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)

I2C_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos

#define CRG_COM_RESET_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)

I2C_CLK_SEL (Bit 7)

◆ CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk

#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)

I2C_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos

#define CRG_COM_RESET_CLK_COM_REG_I2C_ENABLE_Pos (6UL)

I2C_ENABLE (Bit 6)

◆ CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk

#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)

SPI_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos

#define CRG_COM_RESET_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)

SPI_CLK_SEL (Bit 5)

◆ CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk

#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)

SPI_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos

#define CRG_COM_RESET_CLK_COM_REG_SPI_ENABLE_Pos (4UL)

SPI_ENABLE (Bit 4)

◆ CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk

#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)

UART2_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos

#define CRG_COM_RESET_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)

UART2_CLK_SEL (Bit 3)

◆ CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk

#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)

UART2_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos

#define CRG_COM_RESET_CLK_COM_REG_UART2_ENABLE_Pos (2UL)

UART2_ENABLE (Bit 2)

◆ CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Msk

#define CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)

UART_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Pos

#define CRG_COM_RESET_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)

UART_CLK_SEL (Bit 1)

◆ CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk

#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)

UART_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos

#define CRG_COM_RESET_CLK_COM_REG_UART_ENABLE_Pos (0UL)

UART_ENABLE (Bit 0)

◆ CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk

#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Msk (0x80UL)

I2C_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos

#define CRG_COM_SET_CLK_COM_REG_I2C_CLK_SEL_Pos (7UL)

I2C_CLK_SEL (Bit 7)

◆ CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk

#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Msk (0x40UL)

I2C_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos

#define CRG_COM_SET_CLK_COM_REG_I2C_ENABLE_Pos (6UL)

I2C_ENABLE (Bit 6)

◆ CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk

#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Msk (0x20UL)

SPI_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos

#define CRG_COM_SET_CLK_COM_REG_SPI_CLK_SEL_Pos (5UL)

SPI_CLK_SEL (Bit 5)

◆ CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk

#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Msk (0x10UL)

SPI_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos

#define CRG_COM_SET_CLK_COM_REG_SPI_ENABLE_Pos (4UL)

SPI_ENABLE (Bit 4)

◆ CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk

#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Msk (0x8UL)

UART2_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos

#define CRG_COM_SET_CLK_COM_REG_UART2_CLK_SEL_Pos (3UL)

UART2_CLK_SEL (Bit 3)

◆ CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk

#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Msk (0x4UL)

UART2_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos

#define CRG_COM_SET_CLK_COM_REG_UART2_ENABLE_Pos (2UL)

UART2_ENABLE (Bit 2)

◆ CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Msk

#define CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Msk (0x2UL)

UART_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Pos

#define CRG_COM_SET_CLK_COM_REG_UART_CLK_SEL_Pos (1UL)

UART_CLK_SEL (Bit 1)

◆ CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk

#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Msk (0x1UL)

UART_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos

#define CRG_COM_SET_CLK_COM_REG_UART_ENABLE_Pos (0UL)

UART_ENABLE (Bit 0)

◆ CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk

#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)

GPADC_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos

#define CRG_PER_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)

GPADC_CLK_SEL (Bit 0)

◆ CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk

#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)

GPADC_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos

#define CRG_PER_RESET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)

GPADC_CLK_SEL (Bit 0)

◆ CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk

#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Msk (0x1UL)

GPADC_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos

#define CRG_PER_SET_CLK_PER_REG_GPADC_CLK_SEL_Pos (0UL)

GPADC_CLK_SEL (Bit 0)

◆ CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Msk (0x1UL)

BANDGAP_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_BANDGAP_OK_Pos (0UL)

BANDGAP_OK (Bit 0)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Msk (0x40UL)

BOD_COMP_VDCDC_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDCDC_OK_Pos (6UL)

BOD_COMP_VDCDC_OK (Bit 6)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Msk (0x10UL)

BOD_COMP_VDD_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDD_OK_Pos (4UL)

BOD_COMP_VDD_OK (Bit 4)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Msk (0x20UL)

BOD_COMP_VDDIO_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VDDIO_OK_Pos (5UL)

BOD_COMP_VDDIO_OK (Bit 5)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Msk (0x80UL)

BOD_COMP_VEFLASH_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_BOD_COMP_VEFLASH_OK_Pos (7UL)

BOD_COMP_VEFLASH_OK (Bit 7)

◆ CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Msk (0x2UL)

LDO_CORE_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_CORE_OK_Pos (1UL)

LDO_CORE_OK (Bit 1)

◆ CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Msk (0x100UL)

LDO_GPADC_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_GPADC_OK_Pos (8UL)

LDO_GPADC_OK (Bit 8)

◆ CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Msk (0x8UL)

LDO_IO_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_IO_OK_Pos (3UL)

LDO_IO_OK (Bit 3)

◆ CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Msk

#define CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Msk (0x4UL)

LDO_LOW_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Pos

#define CRG_TOP_ANA_STATUS_REG_LDO_LOW_OK_Pos (2UL)

LDO_LOW_OK (Bit 2)

◆ CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk

#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Msk (0x7c0UL)

BGR_ITRIM (Bitfield-Mask: 0x1f)

◆ CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos

#define CRG_TOP_BANDGAP_REG_BGR_ITRIM_Pos (6UL)

BGR_ITRIM (Bit 6)

◆ CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk

#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Msk (0x1fUL)

BGR_TRIM (Bitfield-Mask: 0x1f)

◆ CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos

#define CRG_TOP_BANDGAP_REG_BGR_TRIM_Pos (0UL)

BGR_TRIM (Bit 0)

◆ CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk

#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Msk (0xfUL)

BIAS_VREF_RF1_SEL (Bitfield-Mask: 0x0f)

◆ CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos

#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF1_SEL_Pos (0UL)

BIAS_VREF_RF1_SEL (Bit 0)

◆ CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk

#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Msk (0xf0UL)

BIAS_VREF_RF2_SEL (Bitfield-Mask: 0x0f)

◆ CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos

#define CRG_TOP_BIAS_VREF_SEL_REG_BIAS_VREF_RF2_SEL_Pos (4UL)

BIAS_VREF_RF2_SEL (Bit 4)

◆ CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Msk (0x8UL)

BOD_DIS_VDCDC_COMP (Bitfield-Mask: 0x01)

◆ CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDCDC_COMP_Pos (3UL)

BOD_DIS_VDCDC_COMP (Bit 3)

◆ CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Msk (0x4UL)

BOD_DIS_VDD_COMP (Bitfield-Mask: 0x01)

◆ CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDD_COMP_Pos (2UL)

BOD_DIS_VDD_COMP (Bit 2)

◆ CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Msk (0x10UL)

BOD_DIS_VDDIO_COMP (Bitfield-Mask: 0x01)

◆ CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_DIS_VDDIO_COMP_Pos (4UL)

BOD_DIS_VDDIO_COMP (Bit 4)

◆ CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Msk (0x3UL)

BOD_SEL_VDD_LVL (Bitfield-Mask: 0x03)

◆ CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_SEL_VDD_LVL_Pos (0UL)

BOD_SEL_VDD_LVL (Bit 0)

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Msk (0x80UL)

BOD_VDCDC_MASK (Bitfield-Mask: 0x01)

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_VDCDC_MASK_Pos (7UL)

BOD_VDCDC_MASK (Bit 7)

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Msk (0x40UL)

BOD_VDD_MASK (Bitfield-Mask: 0x01)

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_VDD_MASK_Pos (6UL)

BOD_VDD_MASK (Bit 6)

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Msk

#define CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Msk (0x100UL)

BOD_VDDIO_MASK (Bitfield-Mask: 0x01)

◆ CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Pos

#define CRG_TOP_BOD_CTRL_REG_BOD_VDDIO_MASK_Pos (8UL)

BOD_VDDIO_MASK (Bit 8)

◆ CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Msk (0x40UL)

AES_CLK_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_AES_CLK_ENABLE_Pos (6UL)

AES_CLK_ENABLE (Bit 6)

◆ CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk

#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Msk (0x7UL)

HCLK_DIV (Bitfield-Mask: 0x07)

◆ CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos

#define CRG_TOP_CLK_AMBA_REG_HCLK_DIV_Pos (0UL)

HCLK_DIV (Bit 0)

◆ CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk

#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Msk (0x30UL)

PCLK_DIV (Bitfield-Mask: 0x03)

◆ CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos

#define CRG_TOP_CLK_AMBA_REG_PCLK_DIV_Pos (4UL)

PCLK_DIV (Bit 4)

◆ CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Msk (0x80UL)

QDEC_CLK_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_QDEC_CLK_ENABLE_Pos (7UL)

QDEC_CLK_ENABLE (Bit 7)

◆ CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk

#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Msk (0xc00UL)

QSPI_DIV (Bitfield-Mask: 0x03)

◆ CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos

#define CRG_TOP_CLK_AMBA_REG_QSPI_DIV_Pos (10UL)

QSPI_DIV (Bit 10)

◆ CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk

#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Msk (0x1000UL)

QSPI_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos

#define CRG_TOP_CLK_AMBA_REG_QSPI_ENABLE_Pos (12UL)

QSPI_ENABLE (Bit 12)

◆ CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk

#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Msk (0xcUL)

LP_CLK_SEL (Bitfield-Mask: 0x03)

◆ CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos

#define CRG_TOP_CLK_CTRL_REG_LP_CLK_SEL_Pos (2UL)

LP_CLK_SEL (Bit 2)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Msk (0x8000UL)

RUNNING_AT_DBLR64M (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_DBLR64M_Pos (15UL)

RUNNING_AT_DBLR64M (Bit 15)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Msk (0x1000UL)

RUNNING_AT_LP_CLK (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_LP_CLK_Pos (12UL)

RUNNING_AT_LP_CLK (Bit 12)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Msk (0x2000UL)

RUNNING_AT_RC32M (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_RC32M_Pos (13UL)

RUNNING_AT_RC32M (Bit 13)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Msk (0x4000UL)

RUNNING_AT_XTAL32M (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos

#define CRG_TOP_CLK_CTRL_REG_RUNNING_AT_XTAL32M_Pos (14UL)

RUNNING_AT_XTAL32M (Bit 14)

◆ CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk

#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Msk (0x3UL)

SYS_CLK_SEL (Bitfield-Mask: 0x03)

◆ CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos

#define CRG_TOP_CLK_CTRL_REG_SYS_CLK_SEL_Pos (0UL)

SYS_CLK_SEL (Bit 0)

◆ CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Msk

#define CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Msk (0x20UL)

XTAL32M_DISABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Pos

#define CRG_TOP_CLK_CTRL_REG_XTAL32M_DISABLE_Pos (5UL)

XTAL32M_DISABLE (Bit 5)

◆ CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk

#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Msk (0x1UL)

CMAC_CLK_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos

#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_ENABLE_Pos (0UL)

CMAC_CLK_ENABLE (Bit 0)

◆ CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk

#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Msk (0x2UL)

CMAC_CLK_SEL (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos

#define CRG_TOP_CLK_RADIO_REG_CMAC_CLK_SEL_Pos (1UL)

CMAC_CLK_SEL (Bit 1)

◆ CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk

#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Msk (0x4UL)

CMAC_SYNCH_RESET (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos

#define CRG_TOP_CLK_RADIO_REG_CMAC_SYNCH_RESET_Pos (2UL)

CMAC_SYNCH_RESET (Bit 2)

◆ CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk

#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Msk (0x8UL)

RFCU_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos

#define CRG_TOP_CLK_RADIO_REG_RFCU_ENABLE_Pos (3UL)

RFCU_ENABLE (Bit 3)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk

#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Msk (0x1eUL)

RC32M_BIAS (Bitfield-Mask: 0x0f)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos

#define CRG_TOP_CLK_RC32M_REG_RC32M_BIAS_Pos (1UL)

RC32M_BIAS (Bit 1)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Msk

#define CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Msk (0x780UL)

RC32M_COSC (Bitfield-Mask: 0x0f)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Pos

#define CRG_TOP_CLK_RC32M_REG_RC32M_COSC_Pos (7UL)

RC32M_COSC (Bit 7)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk

#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Msk (0x1UL)

RC32M_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos

#define CRG_TOP_CLK_RC32M_REG_RC32M_ENABLE_Pos (0UL)

RC32M_ENABLE (Bit 0)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Msk

#define CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Msk (0x60UL)

RC32M_RANGE (Bitfield-Mask: 0x03)

◆ CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Pos

#define CRG_TOP_CLK_RC32M_REG_RC32M_RANGE_Pos (5UL)

RC32M_RANGE (Bit 5)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Msk

#define CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Msk (0x1UL)

RCLP_DISABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Pos

#define CRG_TOP_CLK_RCLP_REG_RCLP_DISABLE_Pos (0UL)

RCLP_DISABLE (Bit 0)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Msk

#define CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Msk (0x2UL)

RCLP_HIGH_SPEED_FORCE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Pos

#define CRG_TOP_CLK_RCLP_REG_RCLP_HIGH_SPEED_FORCE_Pos (1UL)

RCLP_HIGH_SPEED_FORCE (Bit 1)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Msk

#define CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Msk (0x4UL)

RCLP_LOW_SPEED_FORCE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Pos

#define CRG_TOP_CLK_RCLP_REG_RCLP_LOW_SPEED_FORCE_Pos (2UL)

RCLP_LOW_SPEED_FORCE (Bit 2)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Msk

#define CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Msk (0x78UL)

RCLP_TRIM (Bitfield-Mask: 0x0f)

◆ CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Pos

#define CRG_TOP_CLK_RCLP_REG_RCLP_TRIM_Pos (3UL)

RCLP_TRIM (Bit 3)

◆ CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk

#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Msk (0x780UL)

RCX_BIAS (Bitfield-Mask: 0x0f)

◆ CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos

#define CRG_TOP_CLK_RCX_REG_RCX_BIAS_Pos (7UL)

RCX_BIAS (Bit 7)

◆ CRG_TOP_CLK_RCX_REG_RCX_C0_Msk

#define CRG_TOP_CLK_RCX_REG_RCX_C0_Msk (0x40UL)

RCX_C0 (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RCX_REG_RCX_C0_Pos

#define CRG_TOP_CLK_RCX_REG_RCX_C0_Pos (6UL)

RCX_C0 (Bit 6)

◆ CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk

#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Msk (0x3eUL)

RCX_CADJUST (Bitfield-Mask: 0x1f)

◆ CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos

#define CRG_TOP_CLK_RCX_REG_RCX_CADJUST_Pos (1UL)

RCX_CADJUST (Bit 1)

◆ CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk

#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk (0x1UL)

RCX_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos

#define CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Pos (0UL)

RCX_ENABLE (Bit 0)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Msk (0x80000UL)

RTC_DIV_DENOM (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_DENOM_Pos (19UL)

RTC_DIV_DENOM (Bit 19)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Msk (0x100000UL)

RTC_DIV_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_ENABLE_Pos (20UL)

RTC_DIV_ENABLE (Bit 20)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Msk (0x3ffUL)

RTC_DIV_FRAC (Bitfield-Mask: 0x3ff)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_FRAC_Pos (0UL)

RTC_DIV_FRAC (Bit 0)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Msk (0x7fc00UL)

RTC_DIV_INT (Bitfield-Mask: 0x1ff)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos

#define CRG_TOP_CLK_RTCDIV_REG_RTC_DIV_INT_Pos (10UL)

RTC_DIV_INT (Bit 10)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk

#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Msk (0x200000UL)

RTC_RESET_REQ (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos

#define CRG_TOP_CLK_RTCDIV_REG_RTC_RESET_REQ_Pos (21UL)

RTC_RESET_REQ (Bit 21)

◆ CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk

#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Msk (0x1UL)

SWITCH2XTAL (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos

#define CRG_TOP_CLK_SWITCH2XTAL_REG_SWITCH2XTAL_Pos (0UL)

SWITCH2XTAL (Bit 0)

◆ CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk

#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Msk (0x4UL)

TMR2_PWM_AON_MODE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos

#define CRG_TOP_CLK_TMR_REG_TMR2_PWM_AON_MODE_Pos (2UL)

TMR2_PWM_AON_MODE (Bit 2)

◆ CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk

#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Msk (0x2UL)

TMR_PWM_AON_MODE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos

#define CRG_TOP_CLK_TMR_REG_TMR_PWM_AON_MODE_Pos (1UL)

TMR_PWM_AON_MODE (Bit 1)

◆ CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk

#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Msk (0x1UL)

WAKEUPCT_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos

#define CRG_TOP_CLK_TMR_REG_WAKEUPCT_ENABLE_Pos (0UL)

WAKEUPCT_ENABLE (Bit 0)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Msk (0x78UL)

XTAL32K_CUR (Bitfield-Mask: 0x0f)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_CUR_Pos (3UL)

XTAL32K_CUR (Bit 3)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Msk (0x80UL)

XTAL32K_DISABLE_AMPREG (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_DISABLE_AMPREG_Pos (7UL)

XTAL32K_DISABLE_AMPREG (Bit 7)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Msk (0x1UL)

XTAL32K_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_ENABLE_Pos (0UL)

XTAL32K_ENABLE (Bit 0)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Msk (0x6UL)

XTAL32K_RBIAS (Bitfield-Mask: 0x03)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_RBIAS_Pos (1UL)

XTAL32K_RBIAS (Bit 1)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Msk

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Msk (0x1e00UL)

XTAL32K_VDDX_TRIM (Bitfield-Mask: 0x0f)

◆ CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Pos

#define CRG_TOP_CLK_XTAL32K_REG_XTAL32K_VDDX_TRIM_Pos (9UL)

XTAL32K_VDDX_TRIM (Bit 9)

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Msk

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Msk (0x2UL)

RESET_VDCDC (Bitfield-Mask: 0x01)

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Pos

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDCDC_Pos (1UL)

RESET_VDCDC (Bit 1)

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Msk

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Msk (0x4UL)

RESET_VDD (Bitfield-Mask: 0x01)

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Pos

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VDD_Pos (2UL)

RESET_VDD (Bit 2)

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Msk

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Msk (0x1UL)

RESET_VIO (Bitfield-Mask: 0x01)

◆ CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Pos

#define CRG_TOP_DISCHARGE_RAIL_REG_RESET_VIO_Pos (0UL)

RESET_VIO (Bit 0)

◆ CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Msk

#define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Msk (0x30UL)

HIBERN_WKUP_MASK (Bitfield-Mask: 0x03)

◆ CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Pos

#define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_MASK_Pos (4UL)

HIBERN_WKUP_MASK (Bit 4)

◆ CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Msk

#define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Msk (0xcUL)

HIBERN_WKUP_POLARITY (Bitfield-Mask: 0x03)

◆ CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Pos

#define CRG_TOP_HIBERN_CTRL_REG_HIBERN_WKUP_POLARITY_Pos (2UL)

HIBERN_WKUP_POLARITY (Bit 2)

◆ CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Msk

#define CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Msk (0x1UL)

HIBERNATION_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Pos

#define CRG_TOP_HIBERN_CTRL_REG_HIBERNATION_ENABLE_Pos (0UL)

HIBERNATION_ENABLE (Bit 0)

◆ CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk

#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Msk (0xffffUL)

P0_LATCH_EN (Bitfield-Mask: 0xffff)

◆ CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos

#define CRG_TOP_P0_PAD_LATCH_REG_P0_LATCH_EN_Pos (0UL)

P0_LATCH_EN (Bit 0)

◆ CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk

#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Msk (0xffffUL)

P0_RESET_LATCH_EN (Bitfield-Mask: 0xffff)

◆ CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos

#define CRG_TOP_P0_RESET_PAD_LATCH_REG_P0_RESET_LATCH_EN_Pos (0UL)

P0_RESET_LATCH_EN (Bit 0)

◆ CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk

#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Msk (0xffffUL)

P0_SET_LATCH_EN (Bitfield-Mask: 0xffff)

◆ CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos

#define CRG_TOP_P0_SET_PAD_LATCH_REG_P0_SET_LATCH_EN_Pos (0UL)

P0_SET_LATCH_EN (Bit 0)

◆ CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk

#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Msk (0xffffUL)

P1_LATCH_EN (Bitfield-Mask: 0xffff)

◆ CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos

#define CRG_TOP_P1_PAD_LATCH_REG_P1_LATCH_EN_Pos (0UL)

P1_LATCH_EN (Bit 0)

◆ CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk

#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Msk (0xffffUL)

P1_RESET_LATCH_EN (Bitfield-Mask: 0xffff)

◆ CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos

#define CRG_TOP_P1_RESET_PAD_LATCH_REG_P1_RESET_LATCH_EN_Pos (0UL)

P1_RESET_LATCH_EN (Bit 0)

◆ CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk

#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Msk (0xffffUL)

P1_SET_LATCH_EN (Bitfield-Mask: 0xffff)

◆ CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos

#define CRG_TOP_P1_SET_PAD_LATCH_REG_P1_SET_LATCH_EN_Pos (0UL)

P1_SET_LATCH_EN (Bit 0)

◆ CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Msk (0x400UL)

AUD_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_AUD_SLEEP_Pos (10UL)

AUD_SLEEP (Bit 10)

◆ CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Msk (0x8UL)

COM_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_COM_SLEEP_Pos (3UL)

COM_SLEEP (Bit 3)

◆ CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Msk

#define CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Msk (0x200UL)

LP_CLK_OUTPUT_EN (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Pos

#define CRG_TOP_PMU_CTRL_REG_LP_CLK_OUTPUT_EN_Pos (9UL)

LP_CLK_OUTPUT_EN (Bit 9)

◆ CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk

#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Msk (0x10UL)

MAP_BANDGAP_EN (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos

#define CRG_TOP_PMU_CTRL_REG_MAP_BANDGAP_EN_Pos (4UL)

MAP_BANDGAP_EN (Bit 4)

◆ CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Msk (0x1UL)

PERIPH_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_PERIPH_SLEEP_Pos (0UL)

PERIPH_SLEEP (Bit 0)

◆ CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Msk (0x2UL)

RADIO_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_RADIO_SLEEP_Pos (1UL)

RADIO_SLEEP (Bit 1)

◆ CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk

#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Msk (0x20UL)

RESET_ON_WAKEUP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos

#define CRG_TOP_PMU_CTRL_REG_RESET_ON_WAKEUP_Pos (5UL)

RESET_ON_WAKEUP (Bit 5)

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk

#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Msk (0x80UL)

RETAIN_CACHE (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos

#define CRG_TOP_PMU_CTRL_REG_RETAIN_CACHE_Pos (7UL)

RETAIN_CACHE (Bit 7)

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Msk

#define CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Msk (0x800UL)

RETAIN_CMAC_CACHE (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Pos

#define CRG_TOP_PMU_CTRL_REG_RETAIN_CMAC_CACHE_Pos (11UL)

RETAIN_CMAC_CACHE (Bit 11)

◆ CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Msk (0x40UL)

SYS_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos (6UL)

SYS_SLEEP (Bit 6)

◆ CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk

#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Msk (0x4UL)

TIM_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos

#define CRG_TOP_PMU_CTRL_REG_TIM_SLEEP_Pos (2UL)

TIM_SLEEP (Bit 2)

◆ CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Msk

#define CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Msk (0x1000UL)

BG_ENABLE_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Pos

#define CRG_TOP_PMU_SLEEP_REG_BG_ENABLE_SLEEP_Pos (12UL)

BG_ENABLE_SLEEP (Bit 12)

◆ CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk

#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Msk (0xfffUL)

BG_REFRESH_INTERVAL (Bitfield-Mask: 0xfff)

◆ CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos

#define CRG_TOP_PMU_SLEEP_REG_BG_REFRESH_INTERVAL_Pos (0UL)

BG_REFRESH_INTERVAL (Bit 0)

◆ CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Msk

#define CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Msk (0x2000UL)

BOD_MASK_BGR_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Pos

#define CRG_TOP_PMU_SLEEP_REG_BOD_MASK_BGR_OK_Pos (13UL)

BOD_MASK_BGR_OK (Bit 13)

◆ CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk

#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Msk (0x10000UL)

FAST_WAKEUP (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos

#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_Pos (16UL)

FAST_WAKEUP (Bit 16)

◆ CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Msk

#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Msk (0x4000UL)

FAST_WAKEUP_SKIP_BGR_OK (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Pos

#define CRG_TOP_PMU_SLEEP_REG_FAST_WAKEUP_SKIP_BGR_OK_Pos (14UL)

FAST_WAKEUP_SKIP_BGR_OK (Bit 14)

◆ CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Msk

#define CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Msk (0x8000UL)

LDO_OK_BYPASS (Bitfield-Mask: 0x01)

◆ CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Pos

#define CRG_TOP_PMU_SLEEP_REG_LDO_OK_BYPASS_Pos (15UL)

LDO_OK_BYPASS (Bit 15)

◆ CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk

#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Msk (0x80UL)

POR_PIN_POLARITY (Bitfield-Mask: 0x01)

◆ CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos

#define CRG_TOP_POR_PIN_REG_POR_PIN_POLARITY_Pos (7UL)

POR_PIN_POLARITY (Bit 7)

◆ CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk

#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Msk (0x3fUL)

POR_PIN_SELECT (Bitfield-Mask: 0x3f)

◆ CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos

#define CRG_TOP_POR_PIN_REG_POR_PIN_SELECT_Pos (0UL)

POR_PIN_SELECT (Bit 0)

◆ CRG_TOP_POR_TIMER_REG_POR_TIME_Msk

#define CRG_TOP_POR_TIMER_REG_POR_TIME_Msk (0x7fUL)

POR_TIME (Bitfield-Mask: 0x7f)

◆ CRG_TOP_POR_TIMER_REG_POR_TIME_Pos

#define CRG_TOP_POR_TIMER_REG_POR_TIME_Pos (0UL)

POR_TIME (Bit 0)

◆ CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Msk

#define CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Msk (0x800UL)

DCDC_ENABLE_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Pos

#define CRG_TOP_POWER_CTRL_REG_DCDC_ENABLE_SLEEP_Pos (11UL)

DCDC_ENABLE_SLEEP (Bit 11)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Msk (0x4UL)

LDO_CORE_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_ENABLE_Pos (2UL)

LDO_CORE_ENABLE (Bit 2)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Msk (0x200UL)

LDO_CORE_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_ACTIVE_Pos (9UL)

LDO_CORE_RET_ENABLE_ACTIVE (Bit 9)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Msk (0x400UL)

LDO_CORE_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_ENABLE_SLEEP_Pos (10UL)

LDO_CORE_RET_ENABLE_SLEEP (Bit 10)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Msk (0x4000UL)

LDO_CORE_RET_VREF_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_CORE_RET_VREF_ENABLE_Pos (14UL)

LDO_CORE_RET_VREF_ENABLE (Bit 14)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Msk (0x20UL)

LDO_IO_BYPASS_ACTIVE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_ACTIVE_Pos (5UL)

LDO_IO_BYPASS_ACTIVE (Bit 5)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Msk (0x40UL)

LDO_IO_BYPASS_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_BYPASS_SLEEP_Pos (6UL)

LDO_IO_BYPASS_SLEEP (Bit 6)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Msk (0x1UL)

LDO_IO_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_ENABLE_Pos (0UL)

LDO_IO_ENABLE (Bit 0)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Msk (0x8UL)

LDO_IO_RET_ENABLE_ACTIVE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_ACTIVE_Pos (3UL)

LDO_IO_RET_ENABLE_ACTIVE (Bit 3)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Msk (0x10UL)

LDO_IO_RET_ENABLE_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_ENABLE_SLEEP_Pos (4UL)

LDO_IO_RET_ENABLE_SLEEP (Bit 4)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Msk (0x2000UL)

LDO_IO_RET_VREF_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_IO_RET_VREF_ENABLE_Pos (13UL)

LDO_IO_RET_VREF_ENABLE (Bit 13)

◆ CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Msk (0x2UL)

LDO_LOW_ENABLE_ACTIVE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_ACTIVE_Pos (1UL)

LDO_LOW_ENABLE_ACTIVE (Bit 1)

◆ CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Msk (0x100UL)

LDO_LOW_ENABLE_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_LOW_ENABLE_SLEEP_Pos (8UL)

LDO_LOW_ENABLE_SLEEP (Bit 8)

◆ CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Msk (0x80UL)

LDO_LOW_HIGH_CURRENT (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_LOW_HIGH_CURRENT_Pos (7UL)

LDO_LOW_HIGH_CURRENT (Bit 7)

◆ CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Msk

#define CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Msk (0x1000UL)

LDO_VREF_HOLD_FORCE (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Pos

#define CRG_TOP_POWER_CTRL_REG_LDO_VREF_HOLD_FORCE_Pos (12UL)

LDO_VREF_HOLD_FORCE (Bit 12)

◆ CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Msk

#define CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Msk (0x70UL)

VDCDC_LEVEL (Bitfield-Mask: 0x07)

◆ CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Pos

#define CRG_TOP_POWER_LEVEL_REG_VDCDC_LEVEL_Pos (4UL)

VDCDC_LEVEL (Bit 4)

◆ CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Msk

#define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Msk (0x7UL)

VDD_LEVEL_ACTIVE (Bitfield-Mask: 0x07)

◆ CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Pos

#define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_ACTIVE_Pos (0UL)

VDD_LEVEL_ACTIVE (Bit 0)

◆ CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Msk

#define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Msk (0x8UL)

VDD_LEVEL_SLEEP (Bitfield-Mask: 0x01)

◆ CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Pos

#define CRG_TOP_POWER_LEVEL_REG_VDD_LEVEL_SLEEP_Pos (3UL)

VDD_LEVEL_SLEEP (Bit 3)

◆ CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Msk

#define CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Msk (0x780UL)

VDDIO_TRIM (Bitfield-Mask: 0x0f)

◆ CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Pos

#define CRG_TOP_POWER_LEVEL_REG_VDDIO_TRIM_Pos (7UL)

VDDIO_TRIM (Bit 7)

◆ CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Msk

#define CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Msk (0x3800UL)

XTAL32M_LDO_LEVEL (Bitfield-Mask: 0x07)

◆ CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Pos

#define CRG_TOP_POWER_LEVEL_REG_XTAL32M_LDO_LEVEL_Pos (11UL)

XTAL32M_LDO_LEVEL (Bit 11)

◆ CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk

#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Msk (0x3UL)

RAM1_PWR_CTRL (Bitfield-Mask: 0x03)

◆ CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos

#define CRG_TOP_RAM_PWR_CTRL_REG_RAM1_PWR_CTRL_Pos (0UL)

RAM1_PWR_CTRL (Bit 0)

◆ CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk

#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Msk (0xcUL)

RAM2_PWR_CTRL (Bitfield-Mask: 0x03)

◆ CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos

#define CRG_TOP_RAM_PWR_CTRL_REG_RAM2_PWR_CTRL_Pos (2UL)

RAM2_PWR_CTRL (Bit 2)

◆ CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk

#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Msk (0x30UL)

RAM3_PWR_CTRL (Bitfield-Mask: 0x03)

◆ CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos

#define CRG_TOP_RAM_PWR_CTRL_REG_RAM3_PWR_CTRL_Pos (4UL)

RAM3_PWR_CTRL (Bit 4)

◆ CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Msk (0x20UL)

CMAC_WDOGRESET_STAT (Bitfield-Mask: 0x01)

◆ CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_CMAC_WDOGRESET_STAT_Pos (5UL)

CMAC_WDOGRESET_STAT (Bit 5)

◆ CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Msk (0x2UL)

HWRESET_STAT (Bitfield-Mask: 0x01)

◆ CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_HWRESET_STAT_Pos (1UL)

HWRESET_STAT (Bit 1)

◆ CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Msk (0x1UL)

PORESET_STAT (Bitfield-Mask: 0x01)

◆ CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_PORESET_STAT_Pos (0UL)

PORESET_STAT (Bit 0)

◆ CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Msk (0x10UL)

SWD_HWRESET_STAT (Bitfield-Mask: 0x01)

◆ CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_SWD_HWRESET_STAT_Pos (4UL)

SWD_HWRESET_STAT (Bit 4)

◆ CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Msk (0x4UL)

SWRESET_STAT (Bitfield-Mask: 0x01)

◆ CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_SWRESET_STAT_Pos (2UL)

SWRESET_STAT (Bit 2)

◆ CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk

#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Msk (0x8UL)

WDOGRESET_STAT (Bitfield-Mask: 0x01)

◆ CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos

#define CRG_TOP_RESET_STAT_REG_WDOGRESET_STAT_Pos (3UL)

WDOGRESET_STAT (Bit 3)

◆ CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Msk

#define CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Msk (0x4UL)

CMAC_CACHE_FLUSH_WITH_SW_RESET (Bitfield-Mask: 0x01)

◆ CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Pos

#define CRG_TOP_RST_CTRL_REG_CMAC_CACHE_FLUSH_WITH_SW_RESET_Pos (2UL)

CMAC_CACHE_FLUSH_WITH_SW_RESET (Bit 2)

◆ CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Msk

#define CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Msk (0x1UL)

GATE_RST_WITH_FCU (Bitfield-Mask: 0x01)

◆ CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Pos

#define CRG_TOP_RST_CTRL_REG_GATE_RST_WITH_FCU_Pos (0UL)

GATE_RST_WITH_FCU (Bit 0)

◆ CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Msk

#define CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Msk (0x2UL)

SYS_CACHE_FLUSH_WITH_SW_RESET (Bitfield-Mask: 0x01)

◆ CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Pos

#define CRG_TOP_RST_CTRL_REG_SYS_CACHE_FLUSH_WITH_SW_RESET_Pos (1UL)

SYS_CACHE_FLUSH_WITH_SW_RESET (Bit 1)

◆ CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk

#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Msk (0x20UL)

FORCE_CMAC_DEBUGGER_OFF (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos

#define CRG_TOP_SECURE_BOOT_REG_FORCE_CMAC_DEBUGGER_OFF_Pos (5UL)

FORCE_CMAC_DEBUGGER_OFF (Bit 5)

◆ CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Msk

#define CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Msk (0x10UL)

FORCE_M33_DEBUGGER_OFF (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Pos

#define CRG_TOP_SECURE_BOOT_REG_FORCE_M33_DEBUGGER_OFF_Pos (4UL)

FORCE_M33_DEBUGGER_OFF (Bit 4)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Msk

#define CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Msk (0x2UL)

PROT_APP_KEY (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Pos

#define CRG_TOP_SECURE_BOOT_REG_PROT_APP_KEY_Pos (1UL)

PROT_APP_KEY (Bit 1)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Msk

#define CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Msk (0x1UL)

PROT_CONFIG_SCRIPT (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Pos

#define CRG_TOP_SECURE_BOOT_REG_PROT_CONFIG_SCRIPT_Pos (0UL)

PROT_CONFIG_SCRIPT (Bit 0)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Msk

#define CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Msk (0x100UL)

PROT_INFO_PAGE (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Pos

#define CRG_TOP_SECURE_BOOT_REG_PROT_INFO_PAGE_Pos (8UL)

PROT_INFO_PAGE (Bit 8)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Msk

#define CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Msk (0x8UL)

PROT_USER_APP_CODE (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Pos

#define CRG_TOP_SECURE_BOOT_REG_PROT_USER_APP_CODE_Pos (3UL)

PROT_USER_APP_CODE (Bit 3)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Msk

#define CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Msk (0x4UL)

PROT_VALID_KEY (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Pos

#define CRG_TOP_SECURE_BOOT_REG_PROT_VALID_KEY_Pos (2UL)

PROT_VALID_KEY (Bit 2)

◆ CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk

#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Msk (0x40UL)

SECURE_BOOT (Bitfield-Mask: 0x01)

◆ CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos

#define CRG_TOP_SECURE_BOOT_REG_SECURE_BOOT_Pos (6UL)

SECURE_BOOT (Bit 6)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Msk (0x1UL)

BOD_VDCDC_MASK_SYNC_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_MASK_SYNC_RD_Pos (0UL)

BOD_VDCDC_MASK_SYNC_RD (Bit 0)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Msk (0x20UL)

BOD_VDCDC_OK_SYNC_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDCDC_OK_SYNC_RD_Pos (5UL)

BOD_VDCDC_OK_SYNC_RD (Bit 5)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Msk (0x18UL)

BOD_VDDD_LVL_RD (Bitfield-Mask: 0x03)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_LVL_RD_Pos (3UL)

BOD_VDDD_LVL_RD (Bit 3)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Msk (0x2UL)

BOD_VDDD_MASK_SYNC_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_MASK_SYNC_RD_Pos (1UL)

BOD_VDDD_MASK_SYNC_RD (Bit 1)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Msk (0x40UL)

BOD_VDDD_OK_SYNC_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDD_OK_SYNC_RD_Pos (6UL)

BOD_VDDD_OK_SYNC_RD (Bit 6)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Msk (0x4UL)

BOD_VDDIO_MASK_SYNC_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_MASK_SYNC_RD_Pos (2UL)

BOD_VDDIO_MASK_SYNC_RD (Bit 2)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Msk (0x80UL)

BOD_VDDIO_OK_SYNC_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VDDIO_OK_SYNC_RD_Pos (7UL)

BOD_VDDIO_OK_SYNC_RD (Bit 7)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Msk

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Msk (0x100UL)

BOD_VEFLASH_OK_SYNC (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Pos

#define CRG_TOP_STARTUP_STATUS_REG_BOD_VEFLASH_OK_SYNC_Pos (8UL)

BOD_VEFLASH_OK_SYNC (Bit 8)

◆ CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Msk

#define CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Msk (0x200UL)

VEFLASH_LVL_RD (Bitfield-Mask: 0x01)

◆ CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Pos

#define CRG_TOP_STARTUP_STATUS_REG_VEFLASH_LVL_RD_Pos (9UL)

VEFLASH_LVL_RD (Bit 9)

◆ CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk

#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Msk (0x400UL)

CACHERAM_MUX (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos

#define CRG_TOP_SYS_CTRL_REG_CACHERAM_MUX_Pos (10UL)

CACHERAM_MUX (Bit 10)

◆ CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk

#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Msk (0x80UL)

DEBUGGER_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos

#define CRG_TOP_SYS_CTRL_REG_DEBUGGER_ENABLE_Pos (7UL)

DEBUGGER_ENABLE (Bit 7)

◆ CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk

#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Msk (0x7UL)

REMAP_ADR0 (Bitfield-Mask: 0x07)

◆ CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos

#define CRG_TOP_SYS_CTRL_REG_REMAP_ADR0_Pos (0UL)

REMAP_ADR0 (Bit 0)

◆ CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk

#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Msk (0x8UL)

REMAP_INTVECT (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos

#define CRG_TOP_SYS_CTRL_REG_REMAP_INTVECT_Pos (3UL)

REMAP_INTVECT (Bit 3)

◆ CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk

#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Msk (0x8000UL)

SW_RESET (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos

#define CRG_TOP_SYS_CTRL_REG_SW_RESET_Pos (15UL)

SW_RESET (Bit 15)

◆ CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Msk (0x1000UL)

AUD_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_AUD_IS_DOWN_Pos (12UL)

AUD_IS_DOWN (Bit 12)

◆ CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Msk (0x2000UL)

AUD_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_AUD_IS_UP_Pos (13UL)

AUD_IS_UP (Bit 13)

◆ CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Msk (0x400UL)

COM_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_COM_IS_DOWN_Pos (10UL)

COM_IS_DOWN (Bit 10)

◆ CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Msk (0x800UL)

COM_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_COM_IS_UP_Pos (11UL)

COM_IS_UP (Bit 11)

◆ CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk

#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Msk (0x4000UL)

DBG_IS_ACTIVE (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos

#define CRG_TOP_SYS_STAT_REG_DBG_IS_ACTIVE_Pos (14UL)

DBG_IS_ACTIVE (Bit 14)

◆ CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Msk (0x40UL)

MEM_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_MEM_IS_DOWN_Pos (6UL)

MEM_IS_DOWN (Bit 6)

◆ CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Msk (0x80UL)

MEM_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_MEM_IS_UP_Pos (7UL)

MEM_IS_UP (Bit 7)

◆ CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Msk (0x4UL)

PER_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_PER_IS_DOWN_Pos (2UL)

PER_IS_DOWN (Bit 2)

◆ CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Msk (0x8UL)

PER_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_PER_IS_UP_Pos (3UL)

PER_IS_UP (Bit 3)

◆ CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Msk (0x8000UL)

POWER_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_POWER_IS_UP_Pos (15UL)

POWER_IS_UP (Bit 15)

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Msk (0x1UL)

RAD_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_RAD_IS_DOWN_Pos (0UL)

RAD_IS_DOWN (Bit 0)

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Msk (0x2UL)

RAD_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_RAD_IS_UP_Pos (1UL)

RAD_IS_UP (Bit 1)

◆ CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Msk (0x10UL)

SYS_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_SYS_IS_DOWN_Pos (4UL)

SYS_IS_DOWN (Bit 4)

◆ CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Msk (0x20UL)

SYS_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_SYS_IS_UP_Pos (5UL)

SYS_IS_UP (Bit 5)

◆ CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk

#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Msk (0x100UL)

TIM_IS_DOWN (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos

#define CRG_TOP_SYS_STAT_REG_TIM_IS_DOWN_Pos (8UL)

TIM_IS_DOWN (Bit 8)

◆ CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk

#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Msk (0x200UL)

TIM_IS_UP (Bitfield-Mask: 0x01)

◆ CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos

#define CRG_TOP_SYS_STAT_REG_TIM_IS_UP_Pos (9UL)

TIM_IS_UP (Bit 9)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Msk (0xf8UL)

DELAY_32M_OVR (Bitfield-Mask: 0x1f)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_32M_OVR_Pos (3UL)

DELAY_32M_OVR (Bit 3)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Msk (0xf00UL)

DELAY_64M_OVR (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_OVR_Pos (8UL)

DELAY_64M_OVR (Bit 8)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Msk (0x1f000UL)

DELAY_64M_PRE_OVR (Bitfield-Mask: 0x1f)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_64M_PRE_OVR_Pos (12UL)

DELAY_64M_PRE_OVR (Bit 12)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Msk (0x7e0000UL)

DELAY_TDC_OVR (Bitfield-Mask: 0x3f)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_DELAY_TDC_OVR_Pos (17UL)

DELAY_TDC_OVR (Bit 17)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Msk (0x2UL)

ENABLE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_ENABLE_Pos (1UL)

ENABLE (Bit 1)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Msk (0x4UL)

OVERRIDE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_OVERRIDE_Pos (2UL)

OVERRIDE (Bit 2)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Msk

#define CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Msk (0x1UL)

RESET_N (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Pos

#define CRG_XTAL_CLKDBLR_CTRL1_REG_RESET_N_Pos (0UL)

RESET_N (Bit 0)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Msk (0xc000UL)

DELAY_64M_PRE_OFFSET (Bitfield-Mask: 0x03)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_DELAY_64M_PRE_OFFSET_Pos (14UL)

DELAY_64M_PRE_OFFSET (Bit 14)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Msk (0xf00UL)

DUTY_CYCLE_CORR_COUNT (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_DUTY_CYCLE_CORR_COUNT_Pos (8UL)

DUTY_CYCLE_CORR_COUNT (Bit 8)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Msk (0x40UL)

EN_ADJ_32M_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_32M_OVR_Pos (6UL)

EN_ADJ_32M_OVR (Bit 6)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Msk (0x20UL)

EN_ADJ_64M_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_ADJ_64M_OVR_Pos (5UL)

EN_ADJ_64M_OVR (Bit 5)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Msk (0x10UL)

EN_TDC_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_EN_TDC_OVR_Pos (4UL)

EN_TDC_OVR (Bit 4)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Msk (0x1000UL)

INV_CLK (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_INV_CLK_Pos (12UL)

INV_CLK (Bit 12)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Msk (0x80UL)

LOW_POWER_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_LOW_POWER_OVR_Pos (7UL)

LOW_POWER_OVR (Bit 7)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Msk (0x1UL)

OUTPUT_ENABLE_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_OUTPUT_ENABLE_OVR_Pos (0UL)

OUTPUT_ENABLE_OVR (Bit 0)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Msk (0x8UL)

PHASE_INV_32M_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_PHASE_INV_32M_OVR_Pos (3UL)

PHASE_INV_32M_OVR (Bit 3)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Msk (0x2000UL)

PRELOAD (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_PRELOAD_Pos (13UL)

PRELOAD (Bit 13)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Msk (0x4UL)

SEL_32M_64M_CLK_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_SEL_32M_64M_CLK_OVR_Pos (2UL)

SEL_32M_64M_CLK_OVR (Bit 2)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Msk

#define CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Msk (0x2UL)

TDC_CLK_INV_OVR (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Pos

#define CRG_XTAL_CLKDBLR_CTRL2_REG_TDC_CLK_INV_OVR_Pos (1UL)

TDC_CLK_INV_OVR (Bit 1)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Msk (0x7c000000UL)

CLKDBLR_STATE (Bitfield-Mask: 0x1f)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_CLKDBLR_STATE_Pos (26UL)

CLKDBLR_STATE (Bit 26)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Msk (0x1fUL)

DELAY_32M_OUT (Bitfield-Mask: 0x1f)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_32M_OUT_Pos (0UL)

DELAY_32M_OUT (Bit 0)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Msk (0x1e0UL)

DELAY_64M_OUT (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_OUT_Pos (5UL)

DELAY_64M_OUT (Bit 5)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Msk (0x3e00UL)

DELAY_64M_PRE_OUT (Bitfield-Mask: 0x1f)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_64M_PRE_OUT_Pos (9UL)

DELAY_64M_PRE_OUT (Bit 9)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Msk (0xfc000UL)

DELAY_TDC_OUT (Bitfield-Mask: 0x3f)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_DELAY_TDC_OUT_Pos (14UL)

DELAY_TDC_OUT (Bit 14)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Msk (0x2000000UL)

OUTPUT_READY (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_OUTPUT_READY_Pos (25UL)

OUTPUT_READY (Bit 25)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Msk (0x80000000UL)

PHASE_INV_32M (Bitfield-Mask: 0x01)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_PHASE_INV_32M_Pos (31UL)

PHASE_INV_32M (Bit 31)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Msk

#define CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Msk (0x1f00000UL)

TDC_BIN_OUT (Bitfield-Mask: 0x1f)

◆ CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Pos

#define CRG_XTAL_CLKDBLR_STATUS_REG_TDC_BIN_OUT_Pos (20UL)

TDC_BIN_OUT (Bit 20)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Msk

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Msk (0x7UL)

XTAL32M_CAP_SELECT (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Pos

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_CAP_SELECT_Pos (0UL)

XTAL32M_CAP_SELECT (Bit 0)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Msk

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Msk (0x18UL)

XTAL32M_MEAS_CUR (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Pos

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_CUR_Pos (3UL)

XTAL32M_MEAS_CUR (Bit 3)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Msk

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Msk (0x20UL)

XTAL32M_MEAS_START (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Pos

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_START_Pos (5UL)

XTAL32M_MEAS_START (Bit 5)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Msk

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Msk (0x1c0UL)

XTAL32M_MEAS_TIME (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Pos

#define CRG_XTAL_XTAL32M_CAP_MEAS_REG_XTAL32M_MEAS_TIME_Pos (6UL)

XTAL32M_MEAS_TIME (Bit 6)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Msk

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Msk (0xcUL)

XTAL32M_AMPREG_SAH (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Pos

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_AMPREG_SAH_Pos (2UL)

XTAL32M_AMPREG_SAH (Bit 2)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Msk

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Msk (0x3UL)

XTAL32M_BIAS_SAH (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Pos

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIAS_SAH_Pos (0UL)

XTAL32M_BIAS_SAH (Bit 0)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Msk

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Msk (0xc0UL)

XTAL32M_BIASPROT (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Pos

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_BIASPROT_Pos (6UL)

XTAL32M_BIASPROT (Bit 6)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Msk

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Msk (0x100UL)

XTAL32M_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Pos

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_ENABLE_Pos (8UL)

XTAL32M_ENABLE (Bit 8)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Msk

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Msk (0x30UL)

XTAL32M_LDO_SAH (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Pos

#define CRG_XTAL_XTAL32M_CTRL_REG_XTAL32M_LDO_SAH_Pos (4UL)

XTAL32M_LDO_SAH (Bit 4)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Msk

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Msk (0x4UL)

XTAL32M_CMP_MODE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Pos

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CMP_MODE_Pos (2UL)

XTAL32M_CMP_MODE (Bit 2)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Msk

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Msk (0x1UL)

XTAL32M_CUR_MODE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Pos

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_CUR_MODE_Pos (0UL)

XTAL32M_CUR_MODE (Bit 0)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Msk

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Msk (0x10UL)

XTAL32M_FSM_APPLY_CONFIG (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Pos

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_APPLY_CONFIG_Pos (4UL)

XTAL32M_FSM_APPLY_CONFIG (Bit 4)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Msk

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Msk (0x8UL)

XTAL32M_FSM_FORCE_IDLE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Pos

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_FSM_FORCE_IDLE_Pos (3UL)

XTAL32M_FSM_FORCE_IDLE (Bit 3)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Msk

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Msk (0x2UL)

XTAL32M_TRIM_MODE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Pos

#define CRG_XTAL_XTAL32M_FSM_REG_XTAL32M_TRIM_MODE_Pos (1UL)

XTAL32M_TRIM_MODE (Bit 1)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Msk

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Msk (0xc00UL)

XTAL32M_IRQ_CAP_CTRL (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Pos

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CAP_CTRL_Pos (10UL)

XTAL32M_IRQ_CAP_CTRL (Bit 10)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Msk

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Msk (0x100UL)

XTAL32M_IRQ_CLK (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Pos

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CLK_Pos (8UL)

XTAL32M_IRQ_CLK (Bit 8)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Msk

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Msk (0xffUL)

XTAL32M_IRQ_CNT (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Pos

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_CNT_Pos (0UL)

XTAL32M_IRQ_CNT (Bit 0)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Msk

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Msk (0x200UL)

XTAL32M_IRQ_ENABLE (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Pos

#define CRG_XTAL_XTAL32M_IRQ_CTRL_REG_XTAL32M_IRQ_ENABLE_Pos (9UL)

XTAL32M_IRQ_ENABLE (Bit 9)

◆ CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Msk

#define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Msk (0xff00UL)

XTAL32M_IRQ_COUNT_CAP (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Pos

#define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_CAP_Pos (8UL)

XTAL32M_IRQ_COUNT_CAP (Bit 8)

◆ CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Msk

#define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Msk (0xffUL)

XTAL32M_IRQ_COUNT_STAT (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Pos

#define CRG_XTAL_XTAL32M_IRQ_STAT_REG_XTAL32M_IRQ_COUNT_STAT_Pos (0UL)

XTAL32M_IRQ_COUNT_STAT (Bit 0)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Msk

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)

XTAL32M_AMPL_SET (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Pos

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_AMPL_SET_Pos (12UL)

XTAL32M_AMPL_SET (Bit 12)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Msk

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Msk (0xe0000UL)

XTAL32M_CMP_BLANK (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Pos

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_BLANK_Pos (17UL)

XTAL32M_CMP_BLANK (Bit 17)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Msk

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)

XTAL32M_CMP_LVL (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Pos

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CMP_LVL_Pos (15UL)

XTAL32M_CMP_LVL (Bit 15)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Msk

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Msk (0xf00UL)

XTAL32M_CUR_SET (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Pos

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_CUR_SET_Pos (8UL)

XTAL32M_CUR_SET (Bit 8)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Msk

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Msk (0x7f00000UL)

XTAL32M_TIMEOUT (Bitfield-Mask: 0x7f)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Pos

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TIMEOUT_Pos (20UL)

XTAL32M_TIMEOUT (Bit 20)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Msk

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Msk (0xffUL)

XTAL32M_TRIM (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Pos

#define CRG_XTAL_XTAL32M_SETTLE_REG_XTAL32M_TRIM_Pos (0UL)

XTAL32M_TRIM (Bit 0)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Msk

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)

XTAL32M_AMPL_SET (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Pos

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_AMPL_SET_Pos (12UL)

XTAL32M_AMPL_SET (Bit 12)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Msk

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Msk (0xe0000UL)

XTAL32M_CMP_BLANK (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Pos

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_BLANK_Pos (17UL)

XTAL32M_CMP_BLANK (Bit 17)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Msk

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)

XTAL32M_CMP_LVL (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Pos

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CMP_LVL_Pos (15UL)

XTAL32M_CMP_LVL (Bit 15)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Msk

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Msk (0xf00UL)

XTAL32M_CUR_SET (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Pos

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_CUR_SET_Pos (8UL)

XTAL32M_CUR_SET (Bit 8)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Msk

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Msk (0x7f00000UL)

XTAL32M_TIMEOUT (Bitfield-Mask: 0x7f)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Pos

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TIMEOUT_Pos (20UL)

XTAL32M_TIMEOUT (Bit 20)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Msk

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Msk (0xffUL)

XTAL32M_TRIM (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Pos

#define CRG_XTAL_XTAL32M_START_REG_XTAL32M_TRIM_Pos (0UL)

XTAL32M_TRIM (Bit 0)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Msk

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Msk (0x20UL)

XTAL32M_CMP_OUT (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Pos

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CMP_OUT_Pos (5UL)

XTAL32M_CMP_OUT (Bit 5)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Msk

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Msk (0x780UL)

XTAL32M_CUR_SET_STAT (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Pos

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_CUR_SET_STAT_Pos (7UL)

XTAL32M_CUR_SET_STAT (Bit 7)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Msk

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Msk (0x40UL)

XTAL32M_LDO_OK (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Pos

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_LDO_OK_Pos (6UL)

XTAL32M_LDO_OK (Bit 6)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Msk

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Msk (0x1UL)

XTAL32M_READY (Bitfield-Mask: 0x01)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Pos

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_READY_Pos (0UL)

XTAL32M_READY (Bit 0)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Msk

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Msk (0x1eUL)

XTAL32M_STATE (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Pos

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_STATE_Pos (1UL)

XTAL32M_STATE (Bit 1)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Msk

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Msk (0x7f800UL)

XTAL32M_TRIM_VAL (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Pos

#define CRG_XTAL_XTAL32M_STAT0_REG_XTAL32M_TRIM_VAL_Pos (11UL)

XTAL32M_TRIM_VAL (Bit 11)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Msk

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Msk (0x7000UL)

XTAL32M_AMPL_SET (Bitfield-Mask: 0x07)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Pos

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_AMPL_SET_Pos (12UL)

XTAL32M_AMPL_SET (Bit 12)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Msk

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Msk (0x18000UL)

XTAL32M_CMP_LVL (Bitfield-Mask: 0x03)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Pos

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CMP_LVL_Pos (15UL)

XTAL32M_CMP_LVL (Bit 15)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Msk

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Msk (0xf00UL)

XTAL32M_CUR_SET (Bitfield-Mask: 0x0f)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Pos

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_CUR_SET_Pos (8UL)

XTAL32M_CUR_SET (Bit 8)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Msk

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Msk (0xffUL)

XTAL32M_TRIM (Bitfield-Mask: 0xff)

◆ CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Pos

#define CRG_XTAL_XTAL32M_TRIM_REG_XTAL32M_TRIM_Pos (0UL)

XTAL32M_TRIM (Bit 0)

◆ DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Msk (0x6UL)

DCDC_CLK_DIV (Bitfield-Mask: 0x03)

◆ DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_CLK_DIV_Pos (1UL)

DCDC_CLK_DIV (Bit 1)

◆ DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Msk (0x1UL)

DCDC_ENABLE (Bitfield-Mask: 0x01)

◆ DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_ENABLE_Pos (0UL)

DCDC_ENABLE (Bit 0)

◆ DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Msk (0x10000UL)

DCDC_FIX_ILIM_SLP (Bitfield-Mask: 0x01)

◆ DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_FIX_ILIM_SLP_Pos (16UL)

DCDC_FIX_ILIM_SLP (Bit 16)

◆ DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Msk (0xf000UL)

DCDC_ILIM_MAX (Bitfield-Mask: 0x0f)

◆ DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MAX_Pos (12UL)

DCDC_ILIM_MAX (Bit 12)

◆ DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Msk (0xf00UL)

DCDC_ILIM_MIN (Bitfield-Mask: 0x0f)

◆ DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_ILIM_MIN_Pos (8UL)

DCDC_ILIM_MIN (Bit 8)

◆ DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Msk (0x1e0000UL)

DCDC_ILIM_SLP (Bitfield-Mask: 0x0f)

◆ DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_ILIM_SLP_Pos (17UL)

DCDC_ILIM_SLP (Bit 17)

◆ DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Msk (0xc0UL)

DCDC_OK_CLR_CNT (Bitfield-Mask: 0x03)

◆ DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_OK_CLR_CNT_Pos (6UL)

DCDC_OK_CLR_CNT (Bit 6)

◆ DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Msk

#define DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Msk (0x38UL)

DCDC_TIMEOUT (Bitfield-Mask: 0x07)

◆ DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Pos

#define DCDC_DCDC_CTRL_REG_DCDC_TIMEOUT_Pos (3UL)

DCDC_TIMEOUT (Bit 3)

◆ DMA_DMA0_A_START_REG_DMA0_A_START_Msk

#define DMA_DMA0_A_START_REG_DMA0_A_START_Msk (0xffffffffUL)

DMA0_A_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA0_A_START_REG_DMA0_A_START_Pos

#define DMA_DMA0_A_START_REG_DMA0_A_START_Pos (0UL)

DMA0_A_START (Bit 0)

◆ DMA_DMA0_B_START_REG_DMA0_B_START_Msk

#define DMA_DMA0_B_START_REG_DMA0_B_START_Msk (0xffffffffUL)

DMA0_B_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA0_B_START_REG_DMA0_B_START_Pos

#define DMA_DMA0_B_START_REG_DMA0_B_START_Pos (0UL)

DMA0_B_START (Bit 0)

◆ DMA_DMA0_CTRL_REG_AINC_Msk

#define DMA_DMA0_CTRL_REG_AINC_Msk (0x20UL)

AINC (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_AINC_Pos

#define DMA_DMA0_CTRL_REG_AINC_Pos (5UL)

AINC (Bit 5)

◆ DMA_DMA0_CTRL_REG_BINC_Msk

#define DMA_DMA0_CTRL_REG_BINC_Msk (0x10UL)

BINC (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_BINC_Pos

#define DMA_DMA0_CTRL_REG_BINC_Pos (4UL)

BINC (Bit 4)

◆ DMA_DMA0_CTRL_REG_BURST_MODE_Msk

#define DMA_DMA0_CTRL_REG_BURST_MODE_Msk (0x6000UL)

BURST_MODE (Bitfield-Mask: 0x03)

◆ DMA_DMA0_CTRL_REG_BURST_MODE_Pos

#define DMA_DMA0_CTRL_REG_BURST_MODE_Pos (13UL)

BURST_MODE (Bit 13)

◆ DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk

#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

BUS_ERROR_DETECT (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos

#define DMA_DMA0_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

BUS_ERROR_DETECT (Bit 15)

◆ DMA_DMA0_CTRL_REG_BW_Msk

#define DMA_DMA0_CTRL_REG_BW_Msk (0x6UL)

BW (Bitfield-Mask: 0x03)

◆ DMA_DMA0_CTRL_REG_BW_Pos

#define DMA_DMA0_CTRL_REG_BW_Pos (1UL)

BW (Bit 1)

◆ DMA_DMA0_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA0_CTRL_REG_CIRCULAR_Msk (0x40UL)

CIRCULAR (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA0_CTRL_REG_CIRCULAR_Pos (6UL)

CIRCULAR (Bit 6)

◆ DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk

#define DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

DMA_EXCLUSIVE_ACCESS (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos

#define DMA_DMA0_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

DMA_EXCLUSIVE_ACCESS (Bit 16)

◆ DMA_DMA0_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA0_CTRL_REG_DMA_IDLE_Msk (0x400UL)

DMA_IDLE (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA0_CTRL_REG_DMA_IDLE_Pos (10UL)

DMA_IDLE (Bit 10)

◆ DMA_DMA0_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA0_CTRL_REG_DMA_INIT_Msk (0x800UL)

DMA_INIT (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA0_CTRL_REG_DMA_INIT_Pos (11UL)

DMA_INIT (Bit 11)

◆ DMA_DMA0_CTRL_REG_DMA_ON_Msk

#define DMA_DMA0_CTRL_REG_DMA_ON_Msk (0x1UL)

DMA_ON (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_DMA_ON_Pos

#define DMA_DMA0_CTRL_REG_DMA_ON_Pos (0UL)

DMA_ON (Bit 0)

◆ DMA_DMA0_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA0_CTRL_REG_DMA_PRIO_Msk (0x380UL)

DMA_PRIO (Bitfield-Mask: 0x07)

◆ DMA_DMA0_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA0_CTRL_REG_DMA_PRIO_Pos (7UL)

DMA_PRIO (Bit 7)

◆ DMA_DMA0_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA0_CTRL_REG_DREQ_MODE_Msk (0x8UL)

DREQ_MODE (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA0_CTRL_REG_DREQ_MODE_Pos (3UL)

DREQ_MODE (Bit 3)

◆ DMA_DMA0_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA0_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

REQ_SENSE (Bitfield-Mask: 0x01)

◆ DMA_DMA0_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA0_CTRL_REG_REQ_SENSE_Pos (12UL)

REQ_SENSE (Bit 12)

◆ DMA_DMA0_IDX_REG_DMA0_IDX_Msk

#define DMA_DMA0_IDX_REG_DMA0_IDX_Msk (0xffffUL)

DMA0_IDX (Bitfield-Mask: 0xffff)

◆ DMA_DMA0_IDX_REG_DMA0_IDX_Pos

#define DMA_DMA0_IDX_REG_DMA0_IDX_Pos (0UL)

DMA0_IDX (Bit 0)

◆ DMA_DMA0_INT_REG_DMA0_INT_Msk

#define DMA_DMA0_INT_REG_DMA0_INT_Msk (0xffffUL)

DMA0_INT (Bitfield-Mask: 0xffff)

◆ DMA_DMA0_INT_REG_DMA0_INT_Pos

#define DMA_DMA0_INT_REG_DMA0_INT_Pos (0UL)

DMA0_INT (Bit 0)

◆ DMA_DMA0_LEN_REG_DMA0_LEN_Msk

#define DMA_DMA0_LEN_REG_DMA0_LEN_Msk (0xffffUL)

DMA0_LEN (Bitfield-Mask: 0xffff)

◆ DMA_DMA0_LEN_REG_DMA0_LEN_Pos

#define DMA_DMA0_LEN_REG_DMA0_LEN_Pos (0UL)

DMA0_LEN (Bit 0)

◆ DMA_DMA1_A_START_REG_DMA1_A_START_Msk

#define DMA_DMA1_A_START_REG_DMA1_A_START_Msk (0xffffffffUL)

DMA1_A_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA1_A_START_REG_DMA1_A_START_Pos

#define DMA_DMA1_A_START_REG_DMA1_A_START_Pos (0UL)

DMA1_A_START (Bit 0)

◆ DMA_DMA1_B_START_REG_DMA1_B_START_Msk

#define DMA_DMA1_B_START_REG_DMA1_B_START_Msk (0xffffffffUL)

DMA1_B_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA1_B_START_REG_DMA1_B_START_Pos

#define DMA_DMA1_B_START_REG_DMA1_B_START_Pos (0UL)

DMA1_B_START (Bit 0)

◆ DMA_DMA1_CTRL_REG_AINC_Msk

#define DMA_DMA1_CTRL_REG_AINC_Msk (0x20UL)

AINC (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_AINC_Pos

#define DMA_DMA1_CTRL_REG_AINC_Pos (5UL)

AINC (Bit 5)

◆ DMA_DMA1_CTRL_REG_BINC_Msk

#define DMA_DMA1_CTRL_REG_BINC_Msk (0x10UL)

BINC (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_BINC_Pos

#define DMA_DMA1_CTRL_REG_BINC_Pos (4UL)

BINC (Bit 4)

◆ DMA_DMA1_CTRL_REG_BURST_MODE_Msk

#define DMA_DMA1_CTRL_REG_BURST_MODE_Msk (0x6000UL)

BURST_MODE (Bitfield-Mask: 0x03)

◆ DMA_DMA1_CTRL_REG_BURST_MODE_Pos

#define DMA_DMA1_CTRL_REG_BURST_MODE_Pos (13UL)

BURST_MODE (Bit 13)

◆ DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk

#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

BUS_ERROR_DETECT (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos

#define DMA_DMA1_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

BUS_ERROR_DETECT (Bit 15)

◆ DMA_DMA1_CTRL_REG_BW_Msk

#define DMA_DMA1_CTRL_REG_BW_Msk (0x6UL)

BW (Bitfield-Mask: 0x03)

◆ DMA_DMA1_CTRL_REG_BW_Pos

#define DMA_DMA1_CTRL_REG_BW_Pos (1UL)

BW (Bit 1)

◆ DMA_DMA1_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA1_CTRL_REG_CIRCULAR_Msk (0x40UL)

CIRCULAR (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA1_CTRL_REG_CIRCULAR_Pos (6UL)

CIRCULAR (Bit 6)

◆ DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk

#define DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

DMA_EXCLUSIVE_ACCESS (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos

#define DMA_DMA1_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

DMA_EXCLUSIVE_ACCESS (Bit 16)

◆ DMA_DMA1_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA1_CTRL_REG_DMA_IDLE_Msk (0x400UL)

DMA_IDLE (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA1_CTRL_REG_DMA_IDLE_Pos (10UL)

DMA_IDLE (Bit 10)

◆ DMA_DMA1_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA1_CTRL_REG_DMA_INIT_Msk (0x800UL)

DMA_INIT (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA1_CTRL_REG_DMA_INIT_Pos (11UL)

DMA_INIT (Bit 11)

◆ DMA_DMA1_CTRL_REG_DMA_ON_Msk

#define DMA_DMA1_CTRL_REG_DMA_ON_Msk (0x1UL)

DMA_ON (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_DMA_ON_Pos

#define DMA_DMA1_CTRL_REG_DMA_ON_Pos (0UL)

DMA_ON (Bit 0)

◆ DMA_DMA1_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA1_CTRL_REG_DMA_PRIO_Msk (0x380UL)

DMA_PRIO (Bitfield-Mask: 0x07)

◆ DMA_DMA1_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA1_CTRL_REG_DMA_PRIO_Pos (7UL)

DMA_PRIO (Bit 7)

◆ DMA_DMA1_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA1_CTRL_REG_DREQ_MODE_Msk (0x8UL)

DREQ_MODE (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA1_CTRL_REG_DREQ_MODE_Pos (3UL)

DREQ_MODE (Bit 3)

◆ DMA_DMA1_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA1_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

REQ_SENSE (Bitfield-Mask: 0x01)

◆ DMA_DMA1_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA1_CTRL_REG_REQ_SENSE_Pos (12UL)

REQ_SENSE (Bit 12)

◆ DMA_DMA1_IDX_REG_DMA1_IDX_Msk

#define DMA_DMA1_IDX_REG_DMA1_IDX_Msk (0xffffUL)

DMA1_IDX (Bitfield-Mask: 0xffff)

◆ DMA_DMA1_IDX_REG_DMA1_IDX_Pos

#define DMA_DMA1_IDX_REG_DMA1_IDX_Pos (0UL)

DMA1_IDX (Bit 0)

◆ DMA_DMA1_INT_REG_DMA1_INT_Msk

#define DMA_DMA1_INT_REG_DMA1_INT_Msk (0xffffUL)

DMA1_INT (Bitfield-Mask: 0xffff)

◆ DMA_DMA1_INT_REG_DMA1_INT_Pos

#define DMA_DMA1_INT_REG_DMA1_INT_Pos (0UL)

DMA1_INT (Bit 0)

◆ DMA_DMA1_LEN_REG_DMA1_LEN_Msk

#define DMA_DMA1_LEN_REG_DMA1_LEN_Msk (0xffffUL)

DMA1_LEN (Bitfield-Mask: 0xffff)

◆ DMA_DMA1_LEN_REG_DMA1_LEN_Pos

#define DMA_DMA1_LEN_REG_DMA1_LEN_Pos (0UL)

DMA1_LEN (Bit 0)

◆ DMA_DMA2_A_START_REG_DMA2_A_START_Msk

#define DMA_DMA2_A_START_REG_DMA2_A_START_Msk (0xffffffffUL)

DMA2_A_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA2_A_START_REG_DMA2_A_START_Pos

#define DMA_DMA2_A_START_REG_DMA2_A_START_Pos (0UL)

DMA2_A_START (Bit 0)

◆ DMA_DMA2_B_START_REG_DMA2_B_START_Msk

#define DMA_DMA2_B_START_REG_DMA2_B_START_Msk (0xffffffffUL)

DMA2_B_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA2_B_START_REG_DMA2_B_START_Pos

#define DMA_DMA2_B_START_REG_DMA2_B_START_Pos (0UL)

DMA2_B_START (Bit 0)

◆ DMA_DMA2_CTRL_REG_AINC_Msk

#define DMA_DMA2_CTRL_REG_AINC_Msk (0x20UL)

AINC (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_AINC_Pos

#define DMA_DMA2_CTRL_REG_AINC_Pos (5UL)

AINC (Bit 5)

◆ DMA_DMA2_CTRL_REG_BINC_Msk

#define DMA_DMA2_CTRL_REG_BINC_Msk (0x10UL)

BINC (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_BINC_Pos

#define DMA_DMA2_CTRL_REG_BINC_Pos (4UL)

BINC (Bit 4)

◆ DMA_DMA2_CTRL_REG_BURST_MODE_Msk

#define DMA_DMA2_CTRL_REG_BURST_MODE_Msk (0x6000UL)

BURST_MODE (Bitfield-Mask: 0x03)

◆ DMA_DMA2_CTRL_REG_BURST_MODE_Pos

#define DMA_DMA2_CTRL_REG_BURST_MODE_Pos (13UL)

BURST_MODE (Bit 13)

◆ DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk

#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

BUS_ERROR_DETECT (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos

#define DMA_DMA2_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

BUS_ERROR_DETECT (Bit 15)

◆ DMA_DMA2_CTRL_REG_BW_Msk

#define DMA_DMA2_CTRL_REG_BW_Msk (0x6UL)

BW (Bitfield-Mask: 0x03)

◆ DMA_DMA2_CTRL_REG_BW_Pos

#define DMA_DMA2_CTRL_REG_BW_Pos (1UL)

BW (Bit 1)

◆ DMA_DMA2_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA2_CTRL_REG_CIRCULAR_Msk (0x40UL)

CIRCULAR (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA2_CTRL_REG_CIRCULAR_Pos (6UL)

CIRCULAR (Bit 6)

◆ DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk

#define DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

DMA_EXCLUSIVE_ACCESS (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos

#define DMA_DMA2_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

DMA_EXCLUSIVE_ACCESS (Bit 16)

◆ DMA_DMA2_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA2_CTRL_REG_DMA_IDLE_Msk (0x400UL)

DMA_IDLE (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA2_CTRL_REG_DMA_IDLE_Pos (10UL)

DMA_IDLE (Bit 10)

◆ DMA_DMA2_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA2_CTRL_REG_DMA_INIT_Msk (0x800UL)

DMA_INIT (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA2_CTRL_REG_DMA_INIT_Pos (11UL)

DMA_INIT (Bit 11)

◆ DMA_DMA2_CTRL_REG_DMA_ON_Msk

#define DMA_DMA2_CTRL_REG_DMA_ON_Msk (0x1UL)

DMA_ON (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_DMA_ON_Pos

#define DMA_DMA2_CTRL_REG_DMA_ON_Pos (0UL)

DMA_ON (Bit 0)

◆ DMA_DMA2_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA2_CTRL_REG_DMA_PRIO_Msk (0x380UL)

DMA_PRIO (Bitfield-Mask: 0x07)

◆ DMA_DMA2_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA2_CTRL_REG_DMA_PRIO_Pos (7UL)

DMA_PRIO (Bit 7)

◆ DMA_DMA2_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA2_CTRL_REG_DREQ_MODE_Msk (0x8UL)

DREQ_MODE (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA2_CTRL_REG_DREQ_MODE_Pos (3UL)

DREQ_MODE (Bit 3)

◆ DMA_DMA2_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA2_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

REQ_SENSE (Bitfield-Mask: 0x01)

◆ DMA_DMA2_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA2_CTRL_REG_REQ_SENSE_Pos (12UL)

REQ_SENSE (Bit 12)

◆ DMA_DMA2_IDX_REG_DMA2_IDX_Msk

#define DMA_DMA2_IDX_REG_DMA2_IDX_Msk (0xffffUL)

DMA2_IDX (Bitfield-Mask: 0xffff)

◆ DMA_DMA2_IDX_REG_DMA2_IDX_Pos

#define DMA_DMA2_IDX_REG_DMA2_IDX_Pos (0UL)

DMA2_IDX (Bit 0)

◆ DMA_DMA2_INT_REG_DMA2_INT_Msk

#define DMA_DMA2_INT_REG_DMA2_INT_Msk (0xffffUL)

DMA2_INT (Bitfield-Mask: 0xffff)

◆ DMA_DMA2_INT_REG_DMA2_INT_Pos

#define DMA_DMA2_INT_REG_DMA2_INT_Pos (0UL)

DMA2_INT (Bit 0)

◆ DMA_DMA2_LEN_REG_DMA2_LEN_Msk

#define DMA_DMA2_LEN_REG_DMA2_LEN_Msk (0xffffUL)

DMA2_LEN (Bitfield-Mask: 0xffff)

◆ DMA_DMA2_LEN_REG_DMA2_LEN_Pos

#define DMA_DMA2_LEN_REG_DMA2_LEN_Pos (0UL)

DMA2_LEN (Bit 0)

◆ DMA_DMA3_A_START_REG_DMA3_A_START_Msk

#define DMA_DMA3_A_START_REG_DMA3_A_START_Msk (0xffffffffUL)

DMA3_A_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA3_A_START_REG_DMA3_A_START_Pos

#define DMA_DMA3_A_START_REG_DMA3_A_START_Pos (0UL)

DMA3_A_START (Bit 0)

◆ DMA_DMA3_B_START_REG_DMA3_B_START_Msk

#define DMA_DMA3_B_START_REG_DMA3_B_START_Msk (0xffffffffUL)

DMA3_B_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA3_B_START_REG_DMA3_B_START_Pos

#define DMA_DMA3_B_START_REG_DMA3_B_START_Pos (0UL)

DMA3_B_START (Bit 0)

◆ DMA_DMA3_CTRL_REG_AINC_Msk

#define DMA_DMA3_CTRL_REG_AINC_Msk (0x20UL)

AINC (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_AINC_Pos

#define DMA_DMA3_CTRL_REG_AINC_Pos (5UL)

AINC (Bit 5)

◆ DMA_DMA3_CTRL_REG_BINC_Msk

#define DMA_DMA3_CTRL_REG_BINC_Msk (0x10UL)

BINC (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_BINC_Pos

#define DMA_DMA3_CTRL_REG_BINC_Pos (4UL)

BINC (Bit 4)

◆ DMA_DMA3_CTRL_REG_BURST_MODE_Msk

#define DMA_DMA3_CTRL_REG_BURST_MODE_Msk (0x6000UL)

BURST_MODE (Bitfield-Mask: 0x03)

◆ DMA_DMA3_CTRL_REG_BURST_MODE_Pos

#define DMA_DMA3_CTRL_REG_BURST_MODE_Pos (13UL)

BURST_MODE (Bit 13)

◆ DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk

#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

BUS_ERROR_DETECT (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos

#define DMA_DMA3_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

BUS_ERROR_DETECT (Bit 15)

◆ DMA_DMA3_CTRL_REG_BW_Msk

#define DMA_DMA3_CTRL_REG_BW_Msk (0x6UL)

BW (Bitfield-Mask: 0x03)

◆ DMA_DMA3_CTRL_REG_BW_Pos

#define DMA_DMA3_CTRL_REG_BW_Pos (1UL)

BW (Bit 1)

◆ DMA_DMA3_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA3_CTRL_REG_CIRCULAR_Msk (0x40UL)

CIRCULAR (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA3_CTRL_REG_CIRCULAR_Pos (6UL)

CIRCULAR (Bit 6)

◆ DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk

#define DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

DMA_EXCLUSIVE_ACCESS (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos

#define DMA_DMA3_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

DMA_EXCLUSIVE_ACCESS (Bit 16)

◆ DMA_DMA3_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA3_CTRL_REG_DMA_IDLE_Msk (0x400UL)

DMA_IDLE (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA3_CTRL_REG_DMA_IDLE_Pos (10UL)

DMA_IDLE (Bit 10)

◆ DMA_DMA3_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA3_CTRL_REG_DMA_INIT_Msk (0x800UL)

DMA_INIT (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA3_CTRL_REG_DMA_INIT_Pos (11UL)

DMA_INIT (Bit 11)

◆ DMA_DMA3_CTRL_REG_DMA_ON_Msk

#define DMA_DMA3_CTRL_REG_DMA_ON_Msk (0x1UL)

DMA_ON (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_DMA_ON_Pos

#define DMA_DMA3_CTRL_REG_DMA_ON_Pos (0UL)

DMA_ON (Bit 0)

◆ DMA_DMA3_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA3_CTRL_REG_DMA_PRIO_Msk (0x380UL)

DMA_PRIO (Bitfield-Mask: 0x07)

◆ DMA_DMA3_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA3_CTRL_REG_DMA_PRIO_Pos (7UL)

DMA_PRIO (Bit 7)

◆ DMA_DMA3_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA3_CTRL_REG_DREQ_MODE_Msk (0x8UL)

DREQ_MODE (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA3_CTRL_REG_DREQ_MODE_Pos (3UL)

DREQ_MODE (Bit 3)

◆ DMA_DMA3_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA3_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

REQ_SENSE (Bitfield-Mask: 0x01)

◆ DMA_DMA3_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA3_CTRL_REG_REQ_SENSE_Pos (12UL)

REQ_SENSE (Bit 12)

◆ DMA_DMA3_IDX_REG_DMA3_IDX_Msk

#define DMA_DMA3_IDX_REG_DMA3_IDX_Msk (0xffffUL)

DMA3_IDX (Bitfield-Mask: 0xffff)

◆ DMA_DMA3_IDX_REG_DMA3_IDX_Pos

#define DMA_DMA3_IDX_REG_DMA3_IDX_Pos (0UL)

DMA3_IDX (Bit 0)

◆ DMA_DMA3_INT_REG_DMA3_INT_Msk

#define DMA_DMA3_INT_REG_DMA3_INT_Msk (0xffffUL)

DMA3_INT (Bitfield-Mask: 0xffff)

◆ DMA_DMA3_INT_REG_DMA3_INT_Pos

#define DMA_DMA3_INT_REG_DMA3_INT_Pos (0UL)

DMA3_INT (Bit 0)

◆ DMA_DMA3_LEN_REG_DMA3_LEN_Msk

#define DMA_DMA3_LEN_REG_DMA3_LEN_Msk (0xffffUL)

DMA3_LEN (Bitfield-Mask: 0xffff)

◆ DMA_DMA3_LEN_REG_DMA3_LEN_Pos

#define DMA_DMA3_LEN_REG_DMA3_LEN_Pos (0UL)

DMA3_LEN (Bit 0)

◆ DMA_DMA4_A_START_REG_DMA4_A_START_Msk

#define DMA_DMA4_A_START_REG_DMA4_A_START_Msk (0xffffffffUL)

DMA4_A_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA4_A_START_REG_DMA4_A_START_Pos

#define DMA_DMA4_A_START_REG_DMA4_A_START_Pos (0UL)

DMA4_A_START (Bit 0)

◆ DMA_DMA4_B_START_REG_DMA4_B_START_Msk

#define DMA_DMA4_B_START_REG_DMA4_B_START_Msk (0xffffffffUL)

DMA4_B_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA4_B_START_REG_DMA4_B_START_Pos

#define DMA_DMA4_B_START_REG_DMA4_B_START_Pos (0UL)

DMA4_B_START (Bit 0)

◆ DMA_DMA4_CTRL_REG_AINC_Msk

#define DMA_DMA4_CTRL_REG_AINC_Msk (0x20UL)

AINC (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_AINC_Pos

#define DMA_DMA4_CTRL_REG_AINC_Pos (5UL)

AINC (Bit 5)

◆ DMA_DMA4_CTRL_REG_BINC_Msk

#define DMA_DMA4_CTRL_REG_BINC_Msk (0x10UL)

BINC (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_BINC_Pos

#define DMA_DMA4_CTRL_REG_BINC_Pos (4UL)

BINC (Bit 4)

◆ DMA_DMA4_CTRL_REG_BURST_MODE_Msk

#define DMA_DMA4_CTRL_REG_BURST_MODE_Msk (0x6000UL)

BURST_MODE (Bitfield-Mask: 0x03)

◆ DMA_DMA4_CTRL_REG_BURST_MODE_Pos

#define DMA_DMA4_CTRL_REG_BURST_MODE_Pos (13UL)

BURST_MODE (Bit 13)

◆ DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk

#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

BUS_ERROR_DETECT (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos

#define DMA_DMA4_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

BUS_ERROR_DETECT (Bit 15)

◆ DMA_DMA4_CTRL_REG_BW_Msk

#define DMA_DMA4_CTRL_REG_BW_Msk (0x6UL)

BW (Bitfield-Mask: 0x03)

◆ DMA_DMA4_CTRL_REG_BW_Pos

#define DMA_DMA4_CTRL_REG_BW_Pos (1UL)

BW (Bit 1)

◆ DMA_DMA4_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA4_CTRL_REG_CIRCULAR_Msk (0x40UL)

CIRCULAR (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA4_CTRL_REG_CIRCULAR_Pos (6UL)

CIRCULAR (Bit 6)

◆ DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk

#define DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

DMA_EXCLUSIVE_ACCESS (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos

#define DMA_DMA4_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

DMA_EXCLUSIVE_ACCESS (Bit 16)

◆ DMA_DMA4_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA4_CTRL_REG_DMA_IDLE_Msk (0x400UL)

DMA_IDLE (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA4_CTRL_REG_DMA_IDLE_Pos (10UL)

DMA_IDLE (Bit 10)

◆ DMA_DMA4_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA4_CTRL_REG_DMA_INIT_Msk (0x800UL)

DMA_INIT (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA4_CTRL_REG_DMA_INIT_Pos (11UL)

DMA_INIT (Bit 11)

◆ DMA_DMA4_CTRL_REG_DMA_ON_Msk

#define DMA_DMA4_CTRL_REG_DMA_ON_Msk (0x1UL)

DMA_ON (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_DMA_ON_Pos

#define DMA_DMA4_CTRL_REG_DMA_ON_Pos (0UL)

DMA_ON (Bit 0)

◆ DMA_DMA4_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA4_CTRL_REG_DMA_PRIO_Msk (0x380UL)

DMA_PRIO (Bitfield-Mask: 0x07)

◆ DMA_DMA4_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA4_CTRL_REG_DMA_PRIO_Pos (7UL)

DMA_PRIO (Bit 7)

◆ DMA_DMA4_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA4_CTRL_REG_DREQ_MODE_Msk (0x8UL)

DREQ_MODE (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA4_CTRL_REG_DREQ_MODE_Pos (3UL)

DREQ_MODE (Bit 3)

◆ DMA_DMA4_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA4_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

REQ_SENSE (Bitfield-Mask: 0x01)

◆ DMA_DMA4_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA4_CTRL_REG_REQ_SENSE_Pos (12UL)

REQ_SENSE (Bit 12)

◆ DMA_DMA4_IDX_REG_DMA4_IDX_Msk

#define DMA_DMA4_IDX_REG_DMA4_IDX_Msk (0xffffUL)

DMA4_IDX (Bitfield-Mask: 0xffff)

◆ DMA_DMA4_IDX_REG_DMA4_IDX_Pos

#define DMA_DMA4_IDX_REG_DMA4_IDX_Pos (0UL)

DMA4_IDX (Bit 0)

◆ DMA_DMA4_INT_REG_DMA4_INT_Msk

#define DMA_DMA4_INT_REG_DMA4_INT_Msk (0xffffUL)

DMA4_INT (Bitfield-Mask: 0xffff)

◆ DMA_DMA4_INT_REG_DMA4_INT_Pos

#define DMA_DMA4_INT_REG_DMA4_INT_Pos (0UL)

DMA4_INT (Bit 0)

◆ DMA_DMA4_LEN_REG_DMA4_LEN_Msk

#define DMA_DMA4_LEN_REG_DMA4_LEN_Msk (0xffffUL)

DMA4_LEN (Bitfield-Mask: 0xffff)

◆ DMA_DMA4_LEN_REG_DMA4_LEN_Pos

#define DMA_DMA4_LEN_REG_DMA4_LEN_Pos (0UL)

DMA4_LEN (Bit 0)

◆ DMA_DMA5_A_START_REG_DMA5_A_START_Msk

#define DMA_DMA5_A_START_REG_DMA5_A_START_Msk (0xffffffffUL)

DMA5_A_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA5_A_START_REG_DMA5_A_START_Pos

#define DMA_DMA5_A_START_REG_DMA5_A_START_Pos (0UL)

DMA5_A_START (Bit 0)

◆ DMA_DMA5_B_START_REG_DMA5_B_START_Msk

#define DMA_DMA5_B_START_REG_DMA5_B_START_Msk (0xffffffffUL)

DMA5_B_START (Bitfield-Mask: 0xffffffff)

◆ DMA_DMA5_B_START_REG_DMA5_B_START_Pos

#define DMA_DMA5_B_START_REG_DMA5_B_START_Pos (0UL)

DMA5_B_START (Bit 0)

◆ DMA_DMA5_CTRL_REG_AINC_Msk

#define DMA_DMA5_CTRL_REG_AINC_Msk (0x20UL)

AINC (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_AINC_Pos

#define DMA_DMA5_CTRL_REG_AINC_Pos (5UL)

AINC (Bit 5)

◆ DMA_DMA5_CTRL_REG_BINC_Msk

#define DMA_DMA5_CTRL_REG_BINC_Msk (0x10UL)

BINC (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_BINC_Pos

#define DMA_DMA5_CTRL_REG_BINC_Pos (4UL)

BINC (Bit 4)

◆ DMA_DMA5_CTRL_REG_BURST_MODE_Msk

#define DMA_DMA5_CTRL_REG_BURST_MODE_Msk (0x6000UL)

BURST_MODE (Bitfield-Mask: 0x03)

◆ DMA_DMA5_CTRL_REG_BURST_MODE_Pos

#define DMA_DMA5_CTRL_REG_BURST_MODE_Pos (13UL)

BURST_MODE (Bit 13)

◆ DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk

#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Msk (0x8000UL)

BUS_ERROR_DETECT (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos

#define DMA_DMA5_CTRL_REG_BUS_ERROR_DETECT_Pos (15UL)

BUS_ERROR_DETECT (Bit 15)

◆ DMA_DMA5_CTRL_REG_BW_Msk

#define DMA_DMA5_CTRL_REG_BW_Msk (0x6UL)

BW (Bitfield-Mask: 0x03)

◆ DMA_DMA5_CTRL_REG_BW_Pos

#define DMA_DMA5_CTRL_REG_BW_Pos (1UL)

BW (Bit 1)

◆ DMA_DMA5_CTRL_REG_CIRCULAR_Msk

#define DMA_DMA5_CTRL_REG_CIRCULAR_Msk (0x40UL)

CIRCULAR (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_CIRCULAR_Pos

#define DMA_DMA5_CTRL_REG_CIRCULAR_Pos (6UL)

CIRCULAR (Bit 6)

◆ DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk

#define DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Msk (0x10000UL)

DMA_EXCLUSIVE_ACCESS (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos

#define DMA_DMA5_CTRL_REG_DMA_EXCLUSIVE_ACCESS_Pos (16UL)

DMA_EXCLUSIVE_ACCESS (Bit 16)

◆ DMA_DMA5_CTRL_REG_DMA_IDLE_Msk

#define DMA_DMA5_CTRL_REG_DMA_IDLE_Msk (0x400UL)

DMA_IDLE (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_DMA_IDLE_Pos

#define DMA_DMA5_CTRL_REG_DMA_IDLE_Pos (10UL)

DMA_IDLE (Bit 10)

◆ DMA_DMA5_CTRL_REG_DMA_INIT_Msk

#define DMA_DMA5_CTRL_REG_DMA_INIT_Msk (0x800UL)

DMA_INIT (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_DMA_INIT_Pos

#define DMA_DMA5_CTRL_REG_DMA_INIT_Pos (11UL)

DMA_INIT (Bit 11)

◆ DMA_DMA5_CTRL_REG_DMA_ON_Msk

#define DMA_DMA5_CTRL_REG_DMA_ON_Msk (0x1UL)

DMA_ON (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_DMA_ON_Pos

#define DMA_DMA5_CTRL_REG_DMA_ON_Pos (0UL)

DMA_ON (Bit 0)

◆ DMA_DMA5_CTRL_REG_DMA_PRIO_Msk

#define DMA_DMA5_CTRL_REG_DMA_PRIO_Msk (0x380UL)

DMA_PRIO (Bitfield-Mask: 0x07)

◆ DMA_DMA5_CTRL_REG_DMA_PRIO_Pos

#define DMA_DMA5_CTRL_REG_DMA_PRIO_Pos (7UL)

DMA_PRIO (Bit 7)

◆ DMA_DMA5_CTRL_REG_DREQ_MODE_Msk

#define DMA_DMA5_CTRL_REG_DREQ_MODE_Msk (0x8UL)

DREQ_MODE (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_DREQ_MODE_Pos

#define DMA_DMA5_CTRL_REG_DREQ_MODE_Pos (3UL)

DREQ_MODE (Bit 3)

◆ DMA_DMA5_CTRL_REG_REQ_SENSE_Msk

#define DMA_DMA5_CTRL_REG_REQ_SENSE_Msk (0x1000UL)

REQ_SENSE (Bitfield-Mask: 0x01)

◆ DMA_DMA5_CTRL_REG_REQ_SENSE_Pos

#define DMA_DMA5_CTRL_REG_REQ_SENSE_Pos (12UL)

REQ_SENSE (Bit 12)

◆ DMA_DMA5_IDX_REG_DMA5_IDX_Msk

#define DMA_DMA5_IDX_REG_DMA5_IDX_Msk (0xffffUL)

DMA5_IDX (Bitfield-Mask: 0xffff)

◆ DMA_DMA5_IDX_REG_DMA5_IDX_Pos

#define DMA_DMA5_IDX_REG_DMA5_IDX_Pos (0UL)

DMA5_IDX (Bit 0)

◆ DMA_DMA5_INT_REG_DMA5_INT_Msk

#define DMA_DMA5_INT_REG_DMA5_INT_Msk (0xffffUL)

DMA5_INT (Bitfield-Mask: 0xffff)

◆ DMA_DMA5_INT_REG_DMA5_INT_Pos

#define DMA_DMA5_INT_REG_DMA5_INT_Pos (0UL)

DMA5_INT (Bit 0)

◆ DMA_DMA5_LEN_REG_DMA5_LEN_Msk

#define DMA_DMA5_LEN_REG_DMA5_LEN_Msk (0xffffUL)

DMA5_LEN (Bitfield-Mask: 0xffff)

◆ DMA_DMA5_LEN_REG_DMA5_LEN_Pos

#define DMA_DMA5_LEN_REG_DMA5_LEN_Pos (0UL)

DMA5_LEN (Bit 0)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Msk (0x1UL)

DMA_RST_IRQ_CH0 (Bitfield-Mask: 0x01)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH0_Pos (0UL)

DMA_RST_IRQ_CH0 (Bit 0)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Msk (0x2UL)

DMA_RST_IRQ_CH1 (Bitfield-Mask: 0x01)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH1_Pos (1UL)

DMA_RST_IRQ_CH1 (Bit 1)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Msk (0x4UL)

DMA_RST_IRQ_CH2 (Bitfield-Mask: 0x01)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH2_Pos (2UL)

DMA_RST_IRQ_CH2 (Bit 2)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Msk (0x8UL)

DMA_RST_IRQ_CH3 (Bitfield-Mask: 0x01)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH3_Pos (3UL)

DMA_RST_IRQ_CH3 (Bit 3)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Msk (0x10UL)

DMA_RST_IRQ_CH4 (Bitfield-Mask: 0x01)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH4_Pos (4UL)

DMA_RST_IRQ_CH4 (Bit 4)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Msk (0x20UL)

DMA_RST_IRQ_CH5 (Bitfield-Mask: 0x01)

◆ DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos

#define DMA_DMA_CLEAR_INT_REG_DMA_RST_IRQ_CH5_Pos (5UL)

DMA_RST_IRQ_CH5 (Bit 5)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Msk (0x1UL)

DMA_IRQ_ENABLE0 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE0_Pos (0UL)

DMA_IRQ_ENABLE0 (Bit 0)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Msk (0x2UL)

DMA_IRQ_ENABLE1 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE1_Pos (1UL)

DMA_IRQ_ENABLE1 (Bit 1)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Msk (0x4UL)

DMA_IRQ_ENABLE2 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE2_Pos (2UL)

DMA_IRQ_ENABLE2 (Bit 2)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Msk (0x8UL)

DMA_IRQ_ENABLE3 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE3_Pos (3UL)

DMA_IRQ_ENABLE3 (Bit 3)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Msk (0x10UL)

DMA_IRQ_ENABLE4 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE4_Pos (4UL)

DMA_IRQ_ENABLE4 (Bit 4)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Msk (0x20UL)

DMA_IRQ_ENABLE5 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos

#define DMA_DMA_INT_MASK_REG_DMA_IRQ_ENABLE5_Pos (5UL)

DMA_IRQ_ENABLE5 (Bit 5)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Msk (0x100UL)

DMA_BUS_ERR0 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR0_Pos (8UL)

DMA_BUS_ERR0 (Bit 8)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Msk (0x200UL)

DMA_BUS_ERR1 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR1_Pos (9UL)

DMA_BUS_ERR1 (Bit 9)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Msk (0x400UL)

DMA_BUS_ERR2 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR2_Pos (10UL)

DMA_BUS_ERR2 (Bit 10)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Msk (0x800UL)

DMA_BUS_ERR3 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR3_Pos (11UL)

DMA_BUS_ERR3 (Bit 11)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Msk (0x1000UL)

DMA_BUS_ERR4 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR4_Pos (12UL)

DMA_BUS_ERR4 (Bit 12)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Msk (0x2000UL)

DMA_BUS_ERR5 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_BUS_ERR5_Pos (13UL)

DMA_BUS_ERR5 (Bit 13)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Msk (0x1UL)

DMA_IRQ_CH0 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH0_Pos (0UL)

DMA_IRQ_CH0 (Bit 0)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Msk (0x2UL)

DMA_IRQ_CH1 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH1_Pos (1UL)

DMA_IRQ_CH1 (Bit 1)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Msk (0x4UL)

DMA_IRQ_CH2 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH2_Pos (2UL)

DMA_IRQ_CH2 (Bit 2)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Msk (0x8UL)

DMA_IRQ_CH3 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH3_Pos (3UL)

DMA_IRQ_CH3 (Bit 3)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Msk (0x10UL)

DMA_IRQ_CH4 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH4_Pos (4UL)

DMA_IRQ_CH4 (Bit 4)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Msk (0x20UL)

DMA_IRQ_CH5 (Bitfield-Mask: 0x01)

◆ DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos

#define DMA_DMA_INT_STATUS_REG_DMA_IRQ_CH5_Pos (5UL)

DMA_IRQ_CH5 (Bit 5)

◆ DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Msk (0xfUL)

DMA01_SEL (Bitfield-Mask: 0x0f)

◆ DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA01_SEL_Pos (0UL)

DMA01_SEL (Bit 0)

◆ DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Msk (0xf0UL)

DMA23_SEL (Bitfield-Mask: 0x0f)

◆ DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA23_SEL_Pos (4UL)

DMA23_SEL (Bit 4)

◆ DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk

#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Msk (0xf00UL)

DMA45_SEL (Bitfield-Mask: 0x0f)

◆ DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos

#define DMA_DMA_REQ_MUX_REG_DMA45_SEL_Pos (8UL)

DMA45_SEL (Bit 8)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Msk

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Msk (0x1UL)

DMA_RESET_IRQ_ENABLE0 (Bitfield-Mask: 0x01)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Pos

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE0_Pos (0UL)

DMA_RESET_IRQ_ENABLE0 (Bit 0)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Msk

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Msk (0x2UL)

DMA_RESET_IRQ_ENABLE1 (Bitfield-Mask: 0x01)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Pos

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE1_Pos (1UL)

DMA_RESET_IRQ_ENABLE1 (Bit 1)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Msk

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Msk (0x4UL)

DMA_RESET_IRQ_ENABLE2 (Bitfield-Mask: 0x01)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Pos

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE2_Pos (2UL)

DMA_RESET_IRQ_ENABLE2 (Bit 2)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Msk

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Msk (0x8UL)

DMA_RESET_IRQ_ENABLE3 (Bitfield-Mask: 0x01)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Pos

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE3_Pos (3UL)

DMA_RESET_IRQ_ENABLE3 (Bit 3)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Msk

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Msk (0x10UL)

DMA_RESET_IRQ_ENABLE4 (Bitfield-Mask: 0x01)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Pos

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE4_Pos (4UL)

DMA_RESET_IRQ_ENABLE4 (Bit 4)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Msk

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Msk (0x20UL)

DMA_RESET_IRQ_ENABLE5 (Bitfield-Mask: 0x01)

◆ DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Pos

#define DMA_DMA_RESET_INT_MASK_REG_DMA_RESET_IRQ_ENABLE5_Pos (5UL)

DMA_RESET_IRQ_ENABLE5 (Bit 5)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Msk

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Msk (0x1UL)

DMA_SET_IRQ_ENABLE0 (Bitfield-Mask: 0x01)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Pos

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE0_Pos (0UL)

DMA_SET_IRQ_ENABLE0 (Bit 0)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Msk

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Msk (0x2UL)

DMA_SET_IRQ_ENABLE1 (Bitfield-Mask: 0x01)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Pos

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE1_Pos (1UL)

DMA_SET_IRQ_ENABLE1 (Bit 1)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Msk

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Msk (0x4UL)

DMA_SET_IRQ_ENABLE2 (Bitfield-Mask: 0x01)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Pos

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE2_Pos (2UL)

DMA_SET_IRQ_ENABLE2 (Bit 2)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Msk

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Msk (0x8UL)

DMA_SET_IRQ_ENABLE3 (Bitfield-Mask: 0x01)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Pos

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE3_Pos (3UL)

DMA_SET_IRQ_ENABLE3 (Bit 3)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Msk

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Msk (0x10UL)

DMA_SET_IRQ_ENABLE4 (Bitfield-Mask: 0x01)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Pos

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE4_Pos (4UL)

DMA_SET_IRQ_ENABLE4 (Bit 4)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Msk

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Msk (0x20UL)

DMA_SET_IRQ_ENABLE5 (Bitfield-Mask: 0x01)

◆ DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Pos

#define DMA_DMA_SET_INT_MASK_REG_DMA_SET_IRQ_ENABLE5_Pos (5UL)

DMA_SET_IRQ_ENABLE5 (Bit 5)

◆ DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk

#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Msk (0xffffUL)

AHB_DMA_CCLM (Bitfield-Mask: 0xffff)

◆ DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos

#define DW_AHB_DMA_CCLM1_REG_AHB_DMA_CCLM_Pos (0UL)

AHB_DMA_CCLM (Bit 0)

◆ DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk

#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Msk (0xffffUL)

AHB_DMA_CCLM (Bitfield-Mask: 0xffff)

◆ DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos

#define DW_AHB_DMA_CCLM2_REG_AHB_DMA_CCLM_Pos (0UL)

AHB_DMA_CCLM (Bit 0)

◆ DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk

#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Msk (0xffffUL)

AHB_DMA_CCLM (Bitfield-Mask: 0xffff)

◆ DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos

#define DW_AHB_DMA_CCLM3_REG_AHB_DMA_CCLM_Pos (0UL)

AHB_DMA_CCLM (Bit 0)

◆ DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk

#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Msk (0xffffUL)

AHB_DMA_CCLM (Bitfield-Mask: 0xffff)

◆ DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos

#define DW_AHB_DMA_CCLM4_REG_AHB_DMA_CCLM_Pos (0UL)

AHB_DMA_CCLM (Bit 0)

◆ DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk

#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Msk (0xfUL)

AHB_DMA_DFLT_MASTER (Bitfield-Mask: 0x0f)

◆ DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos

#define DW_AHB_DMA_DFLT_MASTER_REG_AHB_DMA_DFLT_MASTER_Pos (0UL)

AHB_DMA_DFLT_MASTER (Bit 0)

◆ DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk

#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Msk (0xfUL)

AHB_DMA_PL1 (Bitfield-Mask: 0x0f)

◆ DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos

#define DW_AHB_DMA_PL1_REG_AHB_DMA_PL1_Pos (0UL)

AHB_DMA_PL1 (Bit 0)

◆ DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk

#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Msk (0xfUL)

AHB_DMA_PL2 (Bitfield-Mask: 0x0f)

◆ DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos

#define DW_AHB_DMA_PL2_REG_AHB_DMA_PL2_Pos (0UL)

AHB_DMA_PL2 (Bit 0)

◆ DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk

#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Msk (0xfUL)

AHB_DMA_PL3 (Bitfield-Mask: 0x0f)

◆ DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos

#define DW_AHB_DMA_PL3_REG_AHB_DMA_PL3_Pos (0UL)

AHB_DMA_PL3 (Bit 0)

◆ DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk

#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Msk (0xfUL)

AHB_DMA_PL4 (Bitfield-Mask: 0x0f)

◆ DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos

#define DW_AHB_DMA_PL4_REG_AHB_DMA_PL4_Pos (0UL)

AHB_DMA_PL4 (Bit 0)

◆ DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk

#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Msk (0xffffUL)

AHB_DMA_TCL (Bitfield-Mask: 0xffff)

◆ DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos

#define DW_AHB_DMA_TCL_REG_AHB_DMA_TCL_Pos (0UL)

AHB_DMA_TCL (Bit 0)

◆ DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk

#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Msk (0xffffffffUL)

AHB_DMA_VERSION (Bitfield-Mask: 0xffffffff)

◆ DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos

#define DW_AHB_DMA_VERSION_REG_AHB_DMA_VERSION_Pos (0UL)

AHB_DMA_VERSION (Bit 0)

◆ DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk

#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Msk (0x1UL)

AHB_DMA_WTEN (Bitfield-Mask: 0x01)

◆ DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos

#define DW_AHB_DMA_WTEN_REG_AHB_DMA_WTEN_Pos (0UL)

AHB_DMA_WTEN (Bit 0)

◆ FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Msk

#define FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Msk (0x8000UL)

BUS_ERROR_EN (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Pos

#define FCU_FLASH_CTRL_REG_BUS_ERROR_EN_Pos (15UL)

BUS_ERROR_EN (Bit 15)

◆ FCU_FLASH_CTRL_REG_BUS_ERROR_Msk

#define FCU_FLASH_CTRL_REG_BUS_ERROR_Msk (0x4000UL)

BUS_ERROR (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_BUS_ERROR_Pos

#define FCU_FLASH_CTRL_REG_BUS_ERROR_Pos (14UL)

BUS_ERROR (Bit 14)

◆ FCU_FLASH_CTRL_REG_DFT_EN_Msk

#define FCU_FLASH_CTRL_REG_DFT_EN_Msk (0x1000000UL)

DFT_EN (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_DFT_EN_Pos

#define FCU_FLASH_CTRL_REG_DFT_EN_Pos (24UL)

DFT_EN (Bit 24)

◆ FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Msk

#define FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Msk (0x2000000UL)

DISCHARGE_STAT (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Pos

#define FCU_FLASH_CTRL_REG_DISCHARGE_STAT_Pos (25UL)

DISCHARGE_STAT (Bit 25)

◆ FCU_FLASH_CTRL_REG_DMA_EN_Msk

#define FCU_FLASH_CTRL_REG_DMA_EN_Msk (0x10000UL)

DMA_EN (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_DMA_EN_Pos

#define FCU_FLASH_CTRL_REG_DMA_EN_Pos (16UL)

DMA_EN (Bit 16)

◆ FCU_FLASH_CTRL_REG_ERASE_RESUME_Msk

#define FCU_FLASH_CTRL_REG_ERASE_RESUME_Msk (0x200000UL)

ERASE_RESUME (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_ERASE_RESUME_Pos

#define FCU_FLASH_CTRL_REG_ERASE_RESUME_Pos (21UL)

ERASE_RESUME (Bit 21)

◆ FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Msk

#define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Msk (0x40000UL)

ERASE_SUSPEND_EN (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Pos

#define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_EN_Pos (18UL)

ERASE_SUSPEND_EN (Bit 18)

◆ FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Msk

#define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Msk (0x80000UL)

ERASE_SUSPEND_MODE (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Pos

#define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_MODE_Pos (19UL)

ERASE_SUSPEND_MODE (Bit 19)

◆ FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Msk

#define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Msk (0x100000UL)

ERASE_SUSPEND_STAT (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Pos

#define FCU_FLASH_CTRL_REG_ERASE_SUSPEND_STAT_Pos (20UL)

ERASE_SUSPEND_STAT (Bit 20)

◆ FCU_FLASH_CTRL_REG_FLASH_PROT_Msk

#define FCU_FLASH_CTRL_REG_FLASH_PROT_Msk (0x80UL)

FLASH_PROT (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_FLASH_PROT_Pos

#define FCU_FLASH_CTRL_REG_FLASH_PROT_Pos (7UL)

FLASH_PROT (Bit 7)

◆ FCU_FLASH_CTRL_REG_FLASH_RPROT_Msk

#define FCU_FLASH_CTRL_REG_FLASH_RPROT_Msk (0x200UL)

FLASH_RPROT (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_FLASH_RPROT_Pos

#define FCU_FLASH_CTRL_REG_FLASH_RPROT_Pos (9UL)

FLASH_RPROT (Bit 9)

◆ FCU_FLASH_CTRL_REG_FLASH_WPROT_Msk

#define FCU_FLASH_CTRL_REG_FLASH_WPROT_Msk (0x100UL)

FLASH_WPROT (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_FLASH_WPROT_Pos

#define FCU_FLASH_CTRL_REG_FLASH_WPROT_Pos (8UL)

FLASH_WPROT (Bit 8)

◆ FCU_FLASH_CTRL_REG_IRQ_CLEAR_Msk

#define FCU_FLASH_CTRL_REG_IRQ_CLEAR_Msk (0x2000UL)

IRQ_CLEAR (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_IRQ_CLEAR_Pos

#define FCU_FLASH_CTRL_REG_IRQ_CLEAR_Pos (13UL)

IRQ_CLEAR (Bit 13)

◆ FCU_FLASH_CTRL_REG_PROG_ERS_Msk

#define FCU_FLASH_CTRL_REG_PROG_ERS_Msk (0x20UL)

PROG_ERS (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_PROG_ERS_Pos

#define FCU_FLASH_CTRL_REG_PROG_ERS_Pos (5UL)

PROG_ERS (Bit 5)

◆ FCU_FLASH_CTRL_REG_PROG_MODE_Msk

#define FCU_FLASH_CTRL_REG_PROG_MODE_Msk (0x3UL)

PROG_MODE (Bitfield-Mask: 0x03)

◆ FCU_FLASH_CTRL_REG_PROG_MODE_Pos

#define FCU_FLASH_CTRL_REG_PROG_MODE_Pos (0UL)

PROG_MODE (Bit 0)

◆ FCU_FLASH_CTRL_REG_PROG_RMIN_Msk

#define FCU_FLASH_CTRL_REG_PROG_RMIN_Msk (0x40UL)

PROG_RMIN (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_PROG_RMIN_Pos

#define FCU_FLASH_CTRL_REG_PROG_RMIN_Pos (6UL)

PROG_RMIN (Bit 6)

◆ FCU_FLASH_CTRL_REG_PROG_SEL_Msk

#define FCU_FLASH_CTRL_REG_PROG_SEL_Msk (0x8UL)

PROG_SEL (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_PROG_SEL_Pos

#define FCU_FLASH_CTRL_REG_PROG_SEL_Pos (3UL)

PROG_SEL (Bit 3)

◆ FCU_FLASH_CTRL_REG_PROG_WRS_Msk

#define FCU_FLASH_CTRL_REG_PROG_WRS_Msk (0x10UL)

PROG_WRS (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_PROG_WRS_Pos

#define FCU_FLASH_CTRL_REG_PROG_WRS_Pos (4UL)

PROG_WRS (Bit 4)

◆ FCU_FLASH_CTRL_REG_SLEEP_MODE_Msk

#define FCU_FLASH_CTRL_REG_SLEEP_MODE_Msk (0x4UL)

SLEEP_MODE (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_SLEEP_MODE_Pos

#define FCU_FLASH_CTRL_REG_SLEEP_MODE_Pos (2UL)

SLEEP_MODE (Bit 2)

◆ FCU_FLASH_CTRL_REG_SLEEP_Msk

#define FCU_FLASH_CTRL_REG_SLEEP_Msk (0x20000UL)

SLEEP (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_SLEEP_Pos

#define FCU_FLASH_CTRL_REG_SLEEP_Pos (17UL)

SLEEP (Bit 17)

◆ FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Msk

#define FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Msk (0x400000UL)

VDD_LEVEL_FORCE (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Pos

#define FCU_FLASH_CTRL_REG_VDD_LEVEL_FORCE_Pos (22UL)

VDD_LEVEL_FORCE (Bit 22)

◆ FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Msk

#define FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Msk (0x800000UL)

VDD_LEVEL_VALUE (Bitfield-Mask: 0x01)

◆ FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Pos

#define FCU_FLASH_CTRL_REG_VDD_LEVEL_VALUE_Pos (23UL)

VDD_LEVEL_VALUE (Bit 23)

◆ FCU_FLASH_CTRL_REG_WAIT_CYCLES_Msk

#define FCU_FLASH_CTRL_REG_WAIT_CYCLES_Msk (0x1c00UL)

WAIT_CYCLES (Bitfield-Mask: 0x07)

◆ FCU_FLASH_CTRL_REG_WAIT_CYCLES_Pos

#define FCU_FLASH_CTRL_REG_WAIT_CYCLES_Pos (10UL)

WAIT_CYCLES (Bit 10)

◆ FCU_FLASH_PTERASE_REG_PTERASE_Msk

#define FCU_FLASH_PTERASE_REG_PTERASE_Msk (0xffffffUL)

PTERASE (Bitfield-Mask: 0xffffff)

◆ FCU_FLASH_PTERASE_REG_PTERASE_Pos

#define FCU_FLASH_PTERASE_REG_PTERASE_Pos (0UL)

PTERASE (Bit 0)

◆ FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Msk

#define FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Msk (0xffffffUL)

PTERASE_SEG (Bitfield-Mask: 0xffffff)

◆ FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Pos

#define FCU_FLASH_PTERASE_SEG_REG_PTERASE_SEG_Pos (0UL)

PTERASE_SEG (Bit 0)

◆ FCU_FLASH_PTME_REG_PTME_Msk

#define FCU_FLASH_PTME_REG_PTME_Msk (0xffffffUL)

PTME (Bitfield-Mask: 0xffffff)

◆ FCU_FLASH_PTME_REG_PTME_Pos

#define FCU_FLASH_PTME_REG_PTME_Pos (0UL)

PTME (Bit 0)

◆ FCU_FLASH_PTNVH1_REG_PTNVH1_Msk

#define FCU_FLASH_PTNVH1_REG_PTNVH1_Msk (0xffffUL)

PTNVH1 (Bitfield-Mask: 0xffff)

◆ FCU_FLASH_PTNVH1_REG_PTNVH1_Pos

#define FCU_FLASH_PTNVH1_REG_PTNVH1_Pos (0UL)

PTNVH1 (Bit 0)

◆ FCU_FLASH_PTPROG_REG_PTPROG_Msk

#define FCU_FLASH_PTPROG_REG_PTPROG_Msk (0xffffUL)

PTPROG (Bitfield-Mask: 0xffff)

◆ FCU_FLASH_PTPROG_REG_PTPROG_Pos

#define FCU_FLASH_PTPROG_REG_PTPROG_Pos (0UL)

PTPROG (Bit 0)

◆ FCU_FLASH_PTWK_SP_REG_PTWK_SP_Msk

#define FCU_FLASH_PTWK_SP_REG_PTWK_SP_Msk (0xffUL)

PTWK_SP (Bitfield-Mask: 0xff)

◆ FCU_FLASH_PTWK_SP_REG_PTWK_SP_Pos

#define FCU_FLASH_PTWK_SP_REG_PTWK_SP_Pos (0UL)

PTWK_SP (Bit 0)

◆ FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Msk

#define FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Msk (0xffffffUL)

RTERASE_SEG_CNT (Bitfield-Mask: 0xffffff)

◆ FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Pos

#define FCU_FLASH_RTERASE_SEG_CNT_REG_RTERASE_SEG_CNT_Pos (0UL)

RTERASE_SEG_CNT (Bit 0)

◆ FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Msk

#define FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Msk (0xffffffUL)

RTERASE_TOT_CNT (Bitfield-Mask: 0xffffff)

◆ FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Pos

#define FCU_FLASH_RTERASE_TOT_CNT_REG_RTERASE_TOT_CNT_Pos (0UL)

RTERASE_TOT_CNT (Bit 0)

◆ GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk

#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Msk (0xffffUL)

GP_ADC_CLR_INT (Bitfield-Mask: 0xffff)

◆ GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos

#define GPADC_GP_ADC_CLEAR_INT_REG_GP_ADC_CLR_INT_Pos (0UL)

GP_ADC_CLR_INT (Bit 0)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Msk (0x3UL)

GP_ADC_ATTN (Bitfield-Mask: 0x03)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_ATTN_Pos (0UL)

GP_ADC_ATTN (Bit 0)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Msk (0x1c0UL)

GP_ADC_CONV_NRS (Bitfield-Mask: 0x07)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_CONV_NRS_Pos (6UL)

GP_ADC_CONV_NRS (Bit 6)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Msk (0x4UL)

GP_ADC_I20U (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_I20U_Pos (2UL)

GP_ADC_I20U (Bit 2)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Msk (0x1e00UL)

GP_ADC_SMPL_TIME (Bitfield-Mask: 0x0f)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_SMPL_TIME_Pos (9UL)

GP_ADC_SMPL_TIME (Bit 9)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Msk (0xe000UL)

GP_ADC_STORE_DEL (Bitfield-Mask: 0x07)

◆ GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos

#define GPADC_GP_ADC_CTRL2_REG_GP_ADC_STORE_DEL_Pos (13UL)

GP_ADC_STORE_DEL (Bit 13)

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Msk (0xffUL)

GP_ADC_EN_DEL (Bitfield-Mask: 0xff)

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_EN_DEL_Pos (0UL)

GP_ADC_EN_DEL (Bit 0)

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Msk (0xff00UL)

GP_ADC_INTERVAL (Bitfield-Mask: 0xff)

◆ GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos

#define GPADC_GP_ADC_CTRL3_REG_GP_ADC_INTERVAL_Pos (8UL)

GP_ADC_INTERVAL (Bit 8)

◆ GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Msk

#define GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Msk (0x1000UL)

DIE_TEMP_EN (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Pos

#define GPADC_GP_ADC_CTRL_REG_DIE_TEMP_EN_Pos (12UL)

DIE_TEMP_EN (Bit 12)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Msk (0x200UL)

GP_ADC_CHOP (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CHOP_Pos (9UL)

GP_ADC_CHOP (Bit 9)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Msk (0x4UL)

GP_ADC_CONT (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_CONT_Pos (2UL)

GP_ADC_CONT (Bit 2)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Msk (0x8UL)

GP_ADC_DMA_EN (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_DMA_EN_Pos (3UL)

GP_ADC_DMA_EN (Bit 3)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Msk (0x1UL)

GP_ADC_EN (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_EN_Pos (0UL)

GP_ADC_EN (Bit 0)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Msk (0x10UL)

GP_ADC_INT (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_INT_Pos (4UL)

GP_ADC_INT (Bit 4)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Msk (0x400UL)

GP_ADC_LDO_HOLD (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_LDO_HOLD_Pos (10UL)

GP_ADC_LDO_HOLD (Bit 10)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Msk (0x20UL)

GP_ADC_MINT (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MINT_Pos (5UL)

GP_ADC_MINT (Bit 5)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Msk (0x80UL)

GP_ADC_MUTE (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_MUTE_Pos (7UL)

GP_ADC_MUTE (Bit 7)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Msk (0x40UL)

GP_ADC_SE (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SE_Pos (6UL)

GP_ADC_SE (Bit 6)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Msk (0x100UL)

GP_ADC_SIGN (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_SIGN_Pos (8UL)

GP_ADC_SIGN (Bit 8)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Msk (0x2UL)

GP_ADC_START (Bitfield-Mask: 0x01)

◆ GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos

#define GPADC_GP_ADC_CTRL_REG_GP_ADC_START_Pos (1UL)

GP_ADC_START (Bit 1)

◆ GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk

#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Msk (0x3ffUL)

GP_ADC_OFFN (Bitfield-Mask: 0x3ff)

◆ GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos

#define GPADC_GP_ADC_OFFN_REG_GP_ADC_OFFN_Pos (0UL)

GP_ADC_OFFN (Bit 0)

◆ GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk

#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Msk (0x3ffUL)

GP_ADC_OFFP (Bitfield-Mask: 0x3ff)

◆ GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos

#define GPADC_GP_ADC_OFFP_REG_GP_ADC_OFFP_Pos (0UL)

GP_ADC_OFFP (Bit 0)

◆ GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk

#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Msk (0xffffUL)

GP_ADC_VAL (Bitfield-Mask: 0xffff)

◆ GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos

#define GPADC_GP_ADC_RESULT_REG_GP_ADC_VAL_Pos (0UL)

GP_ADC_VAL (Bit 0)

◆ GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Msk

#define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Msk (0xfUL)

GP_ADC_SEL_N (Bitfield-Mask: 0x0f)

◆ GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Pos

#define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_N_Pos (0UL)

GP_ADC_SEL_N (Bit 0)

◆ GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Msk

#define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Msk (0xf0UL)

GP_ADC_SEL_P (Bitfield-Mask: 0x0f)

◆ GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Pos

#define GPADC_GP_ADC_SEL_REG_GP_ADC_SEL_P_Pos (4UL)

GP_ADC_SEL_P (Bit 4)

◆ GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk

#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Msk (0x200UL)

DIVN_OUTPUT_EN (Bitfield-Mask: 0x01)

◆ GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos

#define GPIO_GPIO_CLK_SEL_REG_DIVN_OUTPUT_EN_Pos (9UL)

DIVN_OUTPUT_EN (Bit 9)

◆ GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk

#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Msk (0x8UL)

FUNC_CLOCK_EN (Bitfield-Mask: 0x01)

◆ GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos

#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_EN_Pos (3UL)

FUNC_CLOCK_EN (Bit 3)

◆ GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk

#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Msk (0x7UL)

FUNC_CLOCK_SEL (Bitfield-Mask: 0x07)

◆ GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos

#define GPIO_GPIO_CLK_SEL_REG_FUNC_CLOCK_SEL_Pos (0UL)

FUNC_CLOCK_SEL (Bit 0)

◆ GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk

#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Msk (0x100UL)

RC32M_OUTPUT_EN (Bitfield-Mask: 0x01)

◆ GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos

#define GPIO_GPIO_CLK_SEL_REG_RC32M_OUTPUT_EN_Pos (8UL)

RC32M_OUTPUT_EN (Bit 8)

◆ GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk

#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Msk (0x80UL)

XTAL32M_OUTPUT_EN (Bitfield-Mask: 0x01)

◆ GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos

#define GPIO_GPIO_CLK_SEL_REG_XTAL32M_OUTPUT_EN_Pos (7UL)

XTAL32M_OUTPUT_EN (Bit 7)

◆ GPIO_P0_00_MODE_REG_PID_Msk

#define GPIO_P0_00_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_00_MODE_REG_PID_Pos

#define GPIO_P0_00_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_00_MODE_REG_PPOD_Msk

#define GPIO_P0_00_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_00_MODE_REG_PPOD_Pos

#define GPIO_P0_00_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_00_MODE_REG_PUPD_Msk

#define GPIO_P0_00_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_00_MODE_REG_PUPD_Pos

#define GPIO_P0_00_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_01_MODE_REG_PID_Msk

#define GPIO_P0_01_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_01_MODE_REG_PID_Pos

#define GPIO_P0_01_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_01_MODE_REG_PPOD_Msk

#define GPIO_P0_01_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_01_MODE_REG_PPOD_Pos

#define GPIO_P0_01_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_01_MODE_REG_PUPD_Msk

#define GPIO_P0_01_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_01_MODE_REG_PUPD_Pos

#define GPIO_P0_01_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_02_MODE_REG_PID_Msk

#define GPIO_P0_02_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_02_MODE_REG_PID_Pos

#define GPIO_P0_02_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_02_MODE_REG_PPOD_Msk

#define GPIO_P0_02_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_02_MODE_REG_PPOD_Pos

#define GPIO_P0_02_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_02_MODE_REG_PUPD_Msk

#define GPIO_P0_02_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_02_MODE_REG_PUPD_Pos

#define GPIO_P0_02_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_03_MODE_REG_PID_Msk

#define GPIO_P0_03_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_03_MODE_REG_PID_Pos

#define GPIO_P0_03_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_03_MODE_REG_PPOD_Msk

#define GPIO_P0_03_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_03_MODE_REG_PPOD_Pos

#define GPIO_P0_03_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_03_MODE_REG_PUPD_Msk

#define GPIO_P0_03_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_03_MODE_REG_PUPD_Pos

#define GPIO_P0_03_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_04_MODE_REG_PID_Msk

#define GPIO_P0_04_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_04_MODE_REG_PID_Pos

#define GPIO_P0_04_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_04_MODE_REG_PPOD_Msk

#define GPIO_P0_04_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_04_MODE_REG_PPOD_Pos

#define GPIO_P0_04_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_04_MODE_REG_PUPD_Msk

#define GPIO_P0_04_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_04_MODE_REG_PUPD_Pos

#define GPIO_P0_04_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_05_MODE_REG_PID_Msk

#define GPIO_P0_05_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_05_MODE_REG_PID_Pos

#define GPIO_P0_05_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_05_MODE_REG_PPOD_Msk

#define GPIO_P0_05_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_05_MODE_REG_PPOD_Pos

#define GPIO_P0_05_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_05_MODE_REG_PUPD_Msk

#define GPIO_P0_05_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_05_MODE_REG_PUPD_Pos

#define GPIO_P0_05_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_06_MODE_REG_PID_Msk

#define GPIO_P0_06_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_06_MODE_REG_PID_Pos

#define GPIO_P0_06_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_06_MODE_REG_PPOD_Msk

#define GPIO_P0_06_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_06_MODE_REG_PPOD_Pos

#define GPIO_P0_06_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_06_MODE_REG_PUPD_Msk

#define GPIO_P0_06_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_06_MODE_REG_PUPD_Pos

#define GPIO_P0_06_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_07_MODE_REG_PID_Msk

#define GPIO_P0_07_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_07_MODE_REG_PID_Pos

#define GPIO_P0_07_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_07_MODE_REG_PPOD_Msk

#define GPIO_P0_07_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_07_MODE_REG_PPOD_Pos

#define GPIO_P0_07_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_07_MODE_REG_PUPD_Msk

#define GPIO_P0_07_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_07_MODE_REG_PUPD_Pos

#define GPIO_P0_07_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_08_MODE_REG_PID_Msk

#define GPIO_P0_08_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_08_MODE_REG_PID_Pos

#define GPIO_P0_08_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_08_MODE_REG_PPOD_Msk

#define GPIO_P0_08_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_08_MODE_REG_PPOD_Pos

#define GPIO_P0_08_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_08_MODE_REG_PUPD_Msk

#define GPIO_P0_08_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_08_MODE_REG_PUPD_Pos

#define GPIO_P0_08_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_09_MODE_REG_PID_Msk

#define GPIO_P0_09_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_09_MODE_REG_PID_Pos

#define GPIO_P0_09_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_09_MODE_REG_PPOD_Msk

#define GPIO_P0_09_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_09_MODE_REG_PPOD_Pos

#define GPIO_P0_09_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_09_MODE_REG_PUPD_Msk

#define GPIO_P0_09_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_09_MODE_REG_PUPD_Pos

#define GPIO_P0_09_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_10_MODE_REG_PID_Msk

#define GPIO_P0_10_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_10_MODE_REG_PID_Pos

#define GPIO_P0_10_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_10_MODE_REG_PPOD_Msk

#define GPIO_P0_10_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_10_MODE_REG_PPOD_Pos

#define GPIO_P0_10_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_10_MODE_REG_PUPD_Msk

#define GPIO_P0_10_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_10_MODE_REG_PUPD_Pos

#define GPIO_P0_10_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_11_MODE_REG_PID_Msk

#define GPIO_P0_11_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_11_MODE_REG_PID_Pos

#define GPIO_P0_11_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_11_MODE_REG_PPOD_Msk

#define GPIO_P0_11_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_11_MODE_REG_PPOD_Pos

#define GPIO_P0_11_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_11_MODE_REG_PUPD_Msk

#define GPIO_P0_11_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_11_MODE_REG_PUPD_Pos

#define GPIO_P0_11_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_12_MODE_REG_PID_Msk

#define GPIO_P0_12_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_12_MODE_REG_PID_Pos

#define GPIO_P0_12_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_12_MODE_REG_PPOD_Msk

#define GPIO_P0_12_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_12_MODE_REG_PPOD_Pos

#define GPIO_P0_12_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_12_MODE_REG_PUPD_Msk

#define GPIO_P0_12_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_12_MODE_REG_PUPD_Pos

#define GPIO_P0_12_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_13_MODE_REG_PID_Msk

#define GPIO_P0_13_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_13_MODE_REG_PID_Pos

#define GPIO_P0_13_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_13_MODE_REG_PPOD_Msk

#define GPIO_P0_13_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_13_MODE_REG_PPOD_Pos

#define GPIO_P0_13_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_13_MODE_REG_PUPD_Msk

#define GPIO_P0_13_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_13_MODE_REG_PUPD_Pos

#define GPIO_P0_13_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_14_MODE_REG_PID_Msk

#define GPIO_P0_14_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_14_MODE_REG_PID_Pos

#define GPIO_P0_14_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_14_MODE_REG_PPOD_Msk

#define GPIO_P0_14_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_14_MODE_REG_PPOD_Pos

#define GPIO_P0_14_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_14_MODE_REG_PUPD_Msk

#define GPIO_P0_14_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_14_MODE_REG_PUPD_Pos

#define GPIO_P0_14_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_15_MODE_REG_PID_Msk

#define GPIO_P0_15_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P0_15_MODE_REG_PID_Pos

#define GPIO_P0_15_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P0_15_MODE_REG_PPOD_Msk

#define GPIO_P0_15_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P0_15_MODE_REG_PPOD_Pos

#define GPIO_P0_15_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P0_15_MODE_REG_PUPD_Msk

#define GPIO_P0_15_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P0_15_MODE_REG_PUPD_Pos

#define GPIO_P0_15_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P0_DATA_REG_P0_DATA_Msk

#define GPIO_P0_DATA_REG_P0_DATA_Msk (0xffffUL)

P0_DATA (Bitfield-Mask: 0xffff)

◆ GPIO_P0_DATA_REG_P0_DATA_Pos

#define GPIO_P0_DATA_REG_P0_DATA_Pos (0UL)

P0_DATA (Bit 0)

◆ GPIO_P0_RESET_DATA_REG_P0_RESET_Msk

#define GPIO_P0_RESET_DATA_REG_P0_RESET_Msk (0xffffUL)

P0_RESET (Bitfield-Mask: 0xffff)

◆ GPIO_P0_RESET_DATA_REG_P0_RESET_Pos

#define GPIO_P0_RESET_DATA_REG_P0_RESET_Pos (0UL)

P0_RESET (Bit 0)

◆ GPIO_P0_SET_DATA_REG_P0_SET_Msk

#define GPIO_P0_SET_DATA_REG_P0_SET_Msk (0xffffUL)

P0_SET (Bitfield-Mask: 0xffff)

◆ GPIO_P0_SET_DATA_REG_P0_SET_Pos

#define GPIO_P0_SET_DATA_REG_P0_SET_Pos (0UL)

P0_SET (Bit 0)

◆ GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Msk

#define GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Msk (0xffc0UL)

P0_LOWDRV (Bitfield-Mask: 0x3ff)

◆ GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Pos

#define GPIO_P0_WEAK_CTRL_REG_P0_LOWDRV_Pos (6UL)

P0_LOWDRV (Bit 6)

◆ GPIO_P1_00_MODE_REG_PID_Msk

#define GPIO_P1_00_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_00_MODE_REG_PID_Pos

#define GPIO_P1_00_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_00_MODE_REG_PPOD_Msk

#define GPIO_P1_00_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_00_MODE_REG_PPOD_Pos

#define GPIO_P1_00_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_00_MODE_REG_PUPD_Msk

#define GPIO_P1_00_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_00_MODE_REG_PUPD_Pos

#define GPIO_P1_00_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_01_MODE_REG_PID_Msk

#define GPIO_P1_01_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_01_MODE_REG_PID_Pos

#define GPIO_P1_01_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_01_MODE_REG_PPOD_Msk

#define GPIO_P1_01_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_01_MODE_REG_PPOD_Pos

#define GPIO_P1_01_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_01_MODE_REG_PUPD_Msk

#define GPIO_P1_01_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_01_MODE_REG_PUPD_Pos

#define GPIO_P1_01_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_02_MODE_REG_PID_Msk

#define GPIO_P1_02_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_02_MODE_REG_PID_Pos

#define GPIO_P1_02_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_02_MODE_REG_PPOD_Msk

#define GPIO_P1_02_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_02_MODE_REG_PPOD_Pos

#define GPIO_P1_02_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_02_MODE_REG_PUPD_Msk

#define GPIO_P1_02_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_02_MODE_REG_PUPD_Pos

#define GPIO_P1_02_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_03_MODE_REG_PID_Msk

#define GPIO_P1_03_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_03_MODE_REG_PID_Pos

#define GPIO_P1_03_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_03_MODE_REG_PPOD_Msk

#define GPIO_P1_03_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_03_MODE_REG_PPOD_Pos

#define GPIO_P1_03_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_03_MODE_REG_PUPD_Msk

#define GPIO_P1_03_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_03_MODE_REG_PUPD_Pos

#define GPIO_P1_03_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_04_MODE_REG_PID_Msk

#define GPIO_P1_04_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_04_MODE_REG_PID_Pos

#define GPIO_P1_04_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_04_MODE_REG_PPOD_Msk

#define GPIO_P1_04_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_04_MODE_REG_PPOD_Pos

#define GPIO_P1_04_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_04_MODE_REG_PUPD_Msk

#define GPIO_P1_04_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_04_MODE_REG_PUPD_Pos

#define GPIO_P1_04_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_05_MODE_REG_PID_Msk

#define GPIO_P1_05_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_05_MODE_REG_PID_Pos

#define GPIO_P1_05_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_05_MODE_REG_PPOD_Msk

#define GPIO_P1_05_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_05_MODE_REG_PPOD_Pos

#define GPIO_P1_05_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_05_MODE_REG_PUPD_Msk

#define GPIO_P1_05_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_05_MODE_REG_PUPD_Pos

#define GPIO_P1_05_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_06_MODE_REG_PID_Msk

#define GPIO_P1_06_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_06_MODE_REG_PID_Pos

#define GPIO_P1_06_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_06_MODE_REG_PPOD_Msk

#define GPIO_P1_06_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_06_MODE_REG_PPOD_Pos

#define GPIO_P1_06_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_06_MODE_REG_PUPD_Msk

#define GPIO_P1_06_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_06_MODE_REG_PUPD_Pos

#define GPIO_P1_06_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_07_MODE_REG_PID_Msk

#define GPIO_P1_07_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_07_MODE_REG_PID_Pos

#define GPIO_P1_07_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_07_MODE_REG_PPOD_Msk

#define GPIO_P1_07_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_07_MODE_REG_PPOD_Pos

#define GPIO_P1_07_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_07_MODE_REG_PUPD_Msk

#define GPIO_P1_07_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_07_MODE_REG_PUPD_Pos

#define GPIO_P1_07_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_08_MODE_REG_PID_Msk

#define GPIO_P1_08_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_08_MODE_REG_PID_Pos

#define GPIO_P1_08_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_08_MODE_REG_PPOD_Msk

#define GPIO_P1_08_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_08_MODE_REG_PPOD_Pos

#define GPIO_P1_08_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_08_MODE_REG_PUPD_Msk

#define GPIO_P1_08_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_08_MODE_REG_PUPD_Pos

#define GPIO_P1_08_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_09_MODE_REG_PID_Msk

#define GPIO_P1_09_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_09_MODE_REG_PID_Pos

#define GPIO_P1_09_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_09_MODE_REG_PPOD_Msk

#define GPIO_P1_09_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_09_MODE_REG_PPOD_Pos

#define GPIO_P1_09_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_09_MODE_REG_PUPD_Msk

#define GPIO_P1_09_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_09_MODE_REG_PUPD_Pos

#define GPIO_P1_09_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_10_MODE_REG_PID_Msk

#define GPIO_P1_10_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_10_MODE_REG_PID_Pos

#define GPIO_P1_10_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_10_MODE_REG_PPOD_Msk

#define GPIO_P1_10_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_10_MODE_REG_PPOD_Pos

#define GPIO_P1_10_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_10_MODE_REG_PUPD_Msk

#define GPIO_P1_10_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_10_MODE_REG_PUPD_Pos

#define GPIO_P1_10_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_11_MODE_REG_PID_Msk

#define GPIO_P1_11_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_11_MODE_REG_PID_Pos

#define GPIO_P1_11_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_11_MODE_REG_PPOD_Msk

#define GPIO_P1_11_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_11_MODE_REG_PPOD_Pos

#define GPIO_P1_11_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_11_MODE_REG_PUPD_Msk

#define GPIO_P1_11_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_11_MODE_REG_PUPD_Pos

#define GPIO_P1_11_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_12_MODE_REG_PID_Msk

#define GPIO_P1_12_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_12_MODE_REG_PID_Pos

#define GPIO_P1_12_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_12_MODE_REG_PPOD_Msk

#define GPIO_P1_12_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_12_MODE_REG_PPOD_Pos

#define GPIO_P1_12_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_12_MODE_REG_PUPD_Msk

#define GPIO_P1_12_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_12_MODE_REG_PUPD_Pos

#define GPIO_P1_12_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_13_MODE_REG_PID_Msk

#define GPIO_P1_13_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_13_MODE_REG_PID_Pos

#define GPIO_P1_13_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_13_MODE_REG_PPOD_Msk

#define GPIO_P1_13_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_13_MODE_REG_PPOD_Pos

#define GPIO_P1_13_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_13_MODE_REG_PUPD_Msk

#define GPIO_P1_13_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_13_MODE_REG_PUPD_Pos

#define GPIO_P1_13_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_14_MODE_REG_PID_Msk

#define GPIO_P1_14_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_14_MODE_REG_PID_Pos

#define GPIO_P1_14_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_14_MODE_REG_PPOD_Msk

#define GPIO_P1_14_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_14_MODE_REG_PPOD_Pos

#define GPIO_P1_14_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_14_MODE_REG_PUPD_Msk

#define GPIO_P1_14_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_14_MODE_REG_PUPD_Pos

#define GPIO_P1_14_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_15_MODE_REG_PID_Msk

#define GPIO_P1_15_MODE_REG_PID_Msk (0x3fUL)

PID (Bitfield-Mask: 0x3f)

◆ GPIO_P1_15_MODE_REG_PID_Pos

#define GPIO_P1_15_MODE_REG_PID_Pos (0UL)

PID (Bit 0)

◆ GPIO_P1_15_MODE_REG_PPOD_Msk

#define GPIO_P1_15_MODE_REG_PPOD_Msk (0x400UL)

PPOD (Bitfield-Mask: 0x01)

◆ GPIO_P1_15_MODE_REG_PPOD_Pos

#define GPIO_P1_15_MODE_REG_PPOD_Pos (10UL)

PPOD (Bit 10)

◆ GPIO_P1_15_MODE_REG_PUPD_Msk

#define GPIO_P1_15_MODE_REG_PUPD_Msk (0x300UL)

PUPD (Bitfield-Mask: 0x03)

◆ GPIO_P1_15_MODE_REG_PUPD_Pos

#define GPIO_P1_15_MODE_REG_PUPD_Pos (8UL)

PUPD (Bit 8)

◆ GPIO_P1_DATA_REG_P1_DATA_Msk

#define GPIO_P1_DATA_REG_P1_DATA_Msk (0xffffUL)

P1_DATA (Bitfield-Mask: 0xffff)

◆ GPIO_P1_DATA_REG_P1_DATA_Pos

#define GPIO_P1_DATA_REG_P1_DATA_Pos (0UL)

P1_DATA (Bit 0)

◆ GPIO_P1_RESET_DATA_REG_P1_RESET_Msk

#define GPIO_P1_RESET_DATA_REG_P1_RESET_Msk (0xffffUL)

P1_RESET (Bitfield-Mask: 0xffff)

◆ GPIO_P1_RESET_DATA_REG_P1_RESET_Pos

#define GPIO_P1_RESET_DATA_REG_P1_RESET_Pos (0UL)

P1_RESET (Bit 0)

◆ GPIO_P1_SET_DATA_REG_P1_SET_Msk

#define GPIO_P1_SET_DATA_REG_P1_SET_Msk (0xffffUL)

P1_SET (Bitfield-Mask: 0xffff)

◆ GPIO_P1_SET_DATA_REG_P1_SET_Pos

#define GPIO_P1_SET_DATA_REG_P1_SET_Pos (0UL)

P1_SET (Bit 0)

◆ GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Msk

#define GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Msk (0xffffUL)

P1_LOWDRV (Bitfield-Mask: 0xffff)

◆ GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Pos

#define GPIO_P1_WEAK_CTRL_REG_P1_LOWDRV_Pos (0UL)

P1_LOWDRV (Bit 0)

◆ GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk

#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Msk (0x2UL)

CMAC_CPU_FREEZE_EN (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos

#define GPREG_DEBUG_REG_CMAC_CPU_FREEZE_EN_Pos (1UL)

CMAC_CPU_FREEZE_EN (Bit 1)

◆ GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk

#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Msk (0x20UL)

CMAC_CPU_IS_HALTED (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos

#define GPREG_DEBUG_REG_CMAC_CPU_IS_HALTED_Pos (5UL)

CMAC_CPU_IS_HALTED (Bit 5)

◆ GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk

#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Msk (0x100UL)

CROSS_CPU_HALT_SENSITIVITY (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos

#define GPREG_DEBUG_REG_CROSS_CPU_HALT_SENSITIVITY_Pos (8UL)

CROSS_CPU_HALT_SENSITIVITY (Bit 8)

◆ GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk

#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Msk (0x8UL)

HALT_CMAC_SYS_CPU_EN (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos

#define GPREG_DEBUG_REG_HALT_CMAC_SYS_CPU_EN_Pos (3UL)

HALT_CMAC_SYS_CPU_EN (Bit 3)

◆ GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk

#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Msk (0x4UL)

HALT_SYS_CMAC_CPU_EN (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos

#define GPREG_DEBUG_REG_HALT_SYS_CMAC_CPU_EN_Pos (2UL)

HALT_SYS_CMAC_CPU_EN (Bit 2)

◆ GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk

#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Msk (0x1UL)

SYS_CPU_FREEZE_EN (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos

#define GPREG_DEBUG_REG_SYS_CPU_FREEZE_EN_Pos (0UL)

SYS_CPU_FREEZE_EN (Bit 0)

◆ GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk

#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Msk (0x10UL)

SYS_CPU_IS_HALTED (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos

#define GPREG_DEBUG_REG_SYS_CPU_IS_HALTED_Pos (4UL)

SYS_CPU_IS_HALTED (Bit 4)

◆ GPREG_DEBUG_REG_SYS_CPUWAIT_Msk

#define GPREG_DEBUG_REG_SYS_CPUWAIT_Msk (0x40UL)

SYS_CPUWAIT (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk

#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Msk (0x80UL)

SYS_CPUWAIT_ON_JTAG (Bitfield-Mask: 0x01)

◆ GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos

#define GPREG_DEBUG_REG_SYS_CPUWAIT_ON_JTAG_Pos (7UL)

SYS_CPUWAIT_ON_JTAG (Bit 7)

◆ GPREG_DEBUG_REG_SYS_CPUWAIT_Pos

#define GPREG_DEBUG_REG_SYS_CPUWAIT_Pos (6UL)

SYS_CPUWAIT (Bit 6)

◆ GPREG_GP_STATUS_REG_CAL_PHASE_Msk

#define GPREG_GP_STATUS_REG_CAL_PHASE_Msk (0x1UL)

CAL_PHASE (Bitfield-Mask: 0x01)

◆ GPREG_GP_STATUS_REG_CAL_PHASE_Pos

#define GPREG_GP_STATUS_REG_CAL_PHASE_Pos (0UL)

CAL_PHASE (Bit 0)

◆ GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)

FRZ_CMAC_WDOG (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)

FRZ_CMAC_WDOG (Bit 10)

◆ GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)

FRZ_DMA (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_DMA_Pos (5UL)

FRZ_DMA (Bit 5)

◆ GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)

FRZ_RESERVED (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)

FRZ_RESERVED (Bit 2)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)

FRZ_SWTIM2 (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)

FRZ_SWTIM2 (Bit 6)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)

FRZ_SWTIM3 (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)

FRZ_SWTIM3 (Bit 8)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)

FRZ_SWTIM4 (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)

FRZ_SWTIM4 (Bit 9)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)

FRZ_SWTIM (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)

FRZ_SWTIM (Bit 1)

◆ GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)

FRZ_SYS_WDOG (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)

FRZ_SYS_WDOG (Bit 3)

◆ GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk

#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)

FRZ_WKUPTIM (Bitfield-Mask: 0x01)

◆ GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos

#define GPREG_RESET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)

FRZ_WKUPTIM (Bit 0)

◆ GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Msk

#define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Msk (0x2UL)

SCPU_FCU_TAG_ALL_TRANS (Bitfield-Mask: 0x01)

◆ GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Pos

#define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_ALL_TRANS_Pos (1UL)

SCPU_FCU_TAG_ALL_TRANS (Bit 1)

◆ GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Msk

#define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Msk (0x1UL)

SCPU_FCU_TAG_EN (Bitfield-Mask: 0x01)

◆ GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Pos

#define GPREG_SCPU_FCU_TAG_REG_SCPU_FCU_TAG_EN_Pos (0UL)

SCPU_FCU_TAG_EN (Bit 0)

◆ GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk

#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Msk (0x400UL)

FRZ_CMAC_WDOG (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos

#define GPREG_SET_FREEZE_REG_FRZ_CMAC_WDOG_Pos (10UL)

FRZ_CMAC_WDOG (Bit 10)

◆ GPREG_SET_FREEZE_REG_FRZ_DMA_Msk

#define GPREG_SET_FREEZE_REG_FRZ_DMA_Msk (0x20UL)

FRZ_DMA (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_DMA_Pos

#define GPREG_SET_FREEZE_REG_FRZ_DMA_Pos (5UL)

FRZ_DMA (Bit 5)

◆ GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk

#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Msk (0x4UL)

FRZ_RESERVED (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos

#define GPREG_SET_FREEZE_REG_FRZ_RESERVED_Pos (2UL)

FRZ_RESERVED (Bit 2)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Msk (0x40UL)

FRZ_SWTIM2 (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM2_Pos (6UL)

FRZ_SWTIM2 (Bit 6)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Msk (0x100UL)

FRZ_SWTIM3 (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM3_Pos (8UL)

FRZ_SWTIM3 (Bit 8)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Msk (0x200UL)

FRZ_SWTIM4 (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM4_Pos (9UL)

FRZ_SWTIM4 (Bit 9)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Msk (0x2UL)

FRZ_SWTIM (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SWTIM_Pos (1UL)

FRZ_SWTIM (Bit 1)

◆ GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk

#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Msk (0x8UL)

FRZ_SYS_WDOG (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos

#define GPREG_SET_FREEZE_REG_FRZ_SYS_WDOG_Pos (3UL)

FRZ_SYS_WDOG (Bit 3)

◆ GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk

#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Msk (0x1UL)

FRZ_WKUPTIM (Bitfield-Mask: 0x01)

◆ GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos

#define GPREG_SET_FREEZE_REG_FRZ_WKUPTIM_Pos (0UL)

FRZ_WKUPTIM (Bit 0)

◆ I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk

#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Msk (0x1UL)

ACK_GEN_CALL (Bitfield-Mask: 0x01)

◆ I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos

#define I2C_I2C_ACK_GENERAL_CALL_REG_ACK_GEN_CALL_Pos (0UL)

ACK_GEN_CALL (Bit 0)

◆ I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk

#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Msk (0x1UL)

CLR_ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos

#define I2C_I2C_CLR_ACTIVITY_REG_CLR_ACTIVITY_Pos (0UL)

CLR_ACTIVITY (Bit 0)

◆ I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk

#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Msk (0x1UL)

CLR_GEN_CALL (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos

#define I2C_I2C_CLR_GEN_CALL_REG_CLR_GEN_CALL_Pos (0UL)

CLR_GEN_CALL (Bit 0)

◆ I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk

#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Msk (0x1UL)

CLR_INTR (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos

#define I2C_I2C_CLR_INTR_REG_CLR_INTR_Pos (0UL)

CLR_INTR (Bit 0)

◆ I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk

#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Msk (0x1UL)

CLR_RD_REQ (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos

#define I2C_I2C_CLR_RD_REQ_REG_CLR_RD_REQ_Pos (0UL)

CLR_RD_REQ (Bit 0)

◆ I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk

#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Msk (0x1UL)

CLR_RX_DONE (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos

#define I2C_I2C_CLR_RX_DONE_REG_CLR_RX_DONE_Pos (0UL)

CLR_RX_DONE (Bit 0)

◆ I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk

#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Msk (0x1UL)

CLR_RX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos

#define I2C_I2C_CLR_RX_OVER_REG_CLR_RX_OVER_Pos (0UL)

CLR_RX_OVER (Bit 0)

◆ I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk

#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Msk (0x1UL)

CLR_RX_UNDER (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos

#define I2C_I2C_CLR_RX_UNDER_REG_CLR_RX_UNDER_Pos (0UL)

CLR_RX_UNDER (Bit 0)

◆ I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk

#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Msk (0x1UL)

CLR_START_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos

#define I2C_I2C_CLR_START_DET_REG_CLR_START_DET_Pos (0UL)

CLR_START_DET (Bit 0)

◆ I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk

#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Msk (0x1UL)

CLR_STOP_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos

#define I2C_I2C_CLR_STOP_DET_REG_CLR_STOP_DET_Pos (0UL)

CLR_STOP_DET (Bit 0)

◆ I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk

#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Msk (0x1UL)

CLR_TX_ABRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos

#define I2C_I2C_CLR_TX_ABRT_REG_CLR_TX_ABRT_Pos (0UL)

CLR_TX_ABRT (Bit 0)

◆ I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk

#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Msk (0x1UL)

CLR_TX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos

#define I2C_I2C_CLR_TX_OVER_REG_CLR_TX_OVER_Pos (0UL)

CLR_TX_OVER (Bit 0)

◆ I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk

#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Msk (0x10UL)

I2C_10BITADDR_MASTER (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos

#define I2C_I2C_CON_REG_I2C_10BITADDR_MASTER_Pos (4UL)

I2C_10BITADDR_MASTER (Bit 4)

◆ I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk

#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Msk (0x8UL)

I2C_10BITADDR_SLAVE (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos

#define I2C_I2C_CON_REG_I2C_10BITADDR_SLAVE_Pos (3UL)

I2C_10BITADDR_SLAVE (Bit 3)

◆ I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk

#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Msk (0x1UL)

I2C_MASTER_MODE (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos

#define I2C_I2C_CON_REG_I2C_MASTER_MODE_Pos (0UL)

I2C_MASTER_MODE (Bit 0)

◆ I2C_I2C_CON_REG_I2C_RESTART_EN_Msk

#define I2C_I2C_CON_REG_I2C_RESTART_EN_Msk (0x20UL)

I2C_RESTART_EN (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_RESTART_EN_Pos

#define I2C_I2C_CON_REG_I2C_RESTART_EN_Pos (5UL)

I2C_RESTART_EN (Bit 5)

◆ I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk

#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Msk (0x200UL)

I2C_RX_FIFO_FULL_HLD_CTRL (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos

#define I2C_I2C_CON_REG_I2C_RX_FIFO_FULL_HLD_CTRL_Pos (9UL)

I2C_RX_FIFO_FULL_HLD_CTRL (Bit 9)

◆ I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk

#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Msk (0x40UL)

I2C_SLAVE_DISABLE (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos

#define I2C_I2C_CON_REG_I2C_SLAVE_DISABLE_Pos (6UL)

I2C_SLAVE_DISABLE (Bit 6)

◆ I2C_I2C_CON_REG_I2C_SPEED_Msk

#define I2C_I2C_CON_REG_I2C_SPEED_Msk (0x6UL)

I2C_SPEED (Bitfield-Mask: 0x03)

◆ I2C_I2C_CON_REG_I2C_SPEED_Pos

#define I2C_I2C_CON_REG_I2C_SPEED_Pos (1UL)

I2C_SPEED (Bit 1)

◆ I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk

#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Msk (0x400UL)

I2C_STOP_DET_IF_MASTER_ACTIVE (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos

#define I2C_I2C_CON_REG_I2C_STOP_DET_IF_MASTER_ACTIVE_Pos (10UL)

I2C_STOP_DET_IF_MASTER_ACTIVE (Bit 10)

◆ I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk

#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Msk (0x80UL)

I2C_STOP_DET_IFADDRESSED (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos

#define I2C_I2C_CON_REG_I2C_STOP_DET_IFADDRESSED_Pos (7UL)

I2C_STOP_DET_IFADDRESSED (Bit 7)

◆ I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk

#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Msk (0x100UL)

I2C_TX_EMPTY_CTRL (Bitfield-Mask: 0x01)

◆ I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos

#define I2C_I2C_CON_REG_I2C_TX_EMPTY_CTRL_Pos (8UL)

I2C_TX_EMPTY_CTRL (Bit 8)

◆ I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk

#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Msk (0x100UL)

I2C_CMD (Bitfield-Mask: 0x01)

◆ I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos

#define I2C_I2C_DATA_CMD_REG_I2C_CMD_Pos (8UL)

I2C_CMD (Bit 8)

◆ I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk

#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Msk (0xffUL)

I2C_DAT (Bitfield-Mask: 0xff)

◆ I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos

#define I2C_I2C_DATA_CMD_REG_I2C_DAT_Pos (0UL)

I2C_DAT (Bit 0)

◆ I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk

#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Msk (0x400UL)

I2C_RESTART (Bitfield-Mask: 0x01)

◆ I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos

#define I2C_I2C_DATA_CMD_REG_I2C_RESTART_Pos (10UL)

I2C_RESTART (Bit 10)

◆ I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk

#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Msk (0x200UL)

I2C_STOP (Bitfield-Mask: 0x01)

◆ I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos

#define I2C_I2C_DATA_CMD_REG_I2C_STOP_Pos (9UL)

I2C_STOP (Bit 9)

◆ I2C_I2C_DMA_CR_REG_RDMAE_Msk

#define I2C_I2C_DMA_CR_REG_RDMAE_Msk (0x1UL)

RDMAE (Bitfield-Mask: 0x01)

◆ I2C_I2C_DMA_CR_REG_RDMAE_Pos

#define I2C_I2C_DMA_CR_REG_RDMAE_Pos (0UL)

RDMAE (Bit 0)

◆ I2C_I2C_DMA_CR_REG_TDMAE_Msk

#define I2C_I2C_DMA_CR_REG_TDMAE_Msk (0x2UL)

TDMAE (Bitfield-Mask: 0x01)

◆ I2C_I2C_DMA_CR_REG_TDMAE_Pos

#define I2C_I2C_DMA_CR_REG_TDMAE_Pos (1UL)

TDMAE (Bit 1)

◆ I2C_I2C_DMA_RDLR_REG_DMARDL_Msk

#define I2C_I2C_DMA_RDLR_REG_DMARDL_Msk (0x1fUL)

DMARDL (Bitfield-Mask: 0x1f)

◆ I2C_I2C_DMA_RDLR_REG_DMARDL_Pos

#define I2C_I2C_DMA_RDLR_REG_DMARDL_Pos (0UL)

DMARDL (Bit 0)

◆ I2C_I2C_DMA_TDLR_REG_DMATDL_Msk

#define I2C_I2C_DMA_TDLR_REG_DMATDL_Msk (0x1fUL)

DMATDL (Bitfield-Mask: 0x1f)

◆ I2C_I2C_DMA_TDLR_REG_DMATDL_Pos

#define I2C_I2C_DMA_TDLR_REG_DMATDL_Pos (0UL)

DMATDL (Bit 0)

◆ I2C_I2C_ENABLE_REG_I2C_ABORT_Msk

#define I2C_I2C_ENABLE_REG_I2C_ABORT_Msk (0x2UL)

I2C_ABORT (Bitfield-Mask: 0x01)

◆ I2C_I2C_ENABLE_REG_I2C_ABORT_Pos

#define I2C_I2C_ENABLE_REG_I2C_ABORT_Pos (1UL)

I2C_ABORT (Bit 1)

◆ I2C_I2C_ENABLE_REG_I2C_EN_Msk

#define I2C_I2C_ENABLE_REG_I2C_EN_Msk (0x1UL)

I2C_EN (Bitfield-Mask: 0x01)

◆ I2C_I2C_ENABLE_REG_I2C_EN_Pos

#define I2C_I2C_ENABLE_REG_I2C_EN_Pos (0UL)

I2C_EN (Bit 0)

◆ I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk

#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Msk (0x4UL)

I2C_TX_CMD_BLOCK (Bitfield-Mask: 0x01)

◆ I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos

#define I2C_I2C_ENABLE_REG_I2C_TX_CMD_BLOCK_Pos (2UL)

I2C_TX_CMD_BLOCK (Bit 2)

◆ I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk

#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Msk (0x1UL)

IC_EN (Bitfield-Mask: 0x01)

◆ I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos

#define I2C_I2C_ENABLE_STATUS_REG_IC_EN_Pos (0UL)

IC_EN (Bit 0)

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk

#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Msk (0x2UL)

SLV_DISABLED_WHILE_BUSY (Bitfield-Mask: 0x01)

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos

#define I2C_I2C_ENABLE_STATUS_REG_SLV_DISABLED_WHILE_BUSY_Pos (1UL)

SLV_DISABLED_WHILE_BUSY (Bit 1)

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk

#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Msk (0x4UL)

SLV_RX_DATA_LOST (Bitfield-Mask: 0x01)

◆ I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos

#define I2C_I2C_ENABLE_STATUS_REG_SLV_RX_DATA_LOST_Pos (2UL)

SLV_RX_DATA_LOST (Bit 2)

◆ I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk

#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Msk (0xffffUL)

IC_FS_SCL_HCNT (Bitfield-Mask: 0xffff)

◆ I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos

#define I2C_I2C_FS_SCL_HCNT_REG_IC_FS_SCL_HCNT_Pos (0UL)

IC_FS_SCL_HCNT (Bit 0)

◆ I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk

#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Msk (0xffffUL)

IC_FS_SCL_LCNT (Bitfield-Mask: 0xffff)

◆ I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos

#define I2C_I2C_FS_SCL_LCNT_REG_IC_FS_SCL_LCNT_Pos (0UL)

IC_FS_SCL_LCNT (Bit 0)

◆ I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk

#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Msk (0x7UL)

I2C_IC_HS_MAR (Bitfield-Mask: 0x07)

◆ I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos

#define I2C_I2C_HS_MADDR_REG_I2C_IC_HS_MAR_Pos (0UL)

I2C_IC_HS_MAR (Bit 0)

◆ I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk

#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Msk (0xffffUL)

IC_HS_SCL_HCNT (Bitfield-Mask: 0xffff)

◆ I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos

#define I2C_I2C_HS_SCL_HCNT_REG_IC_HS_SCL_HCNT_Pos (0UL)

IC_HS_SCL_HCNT (Bit 0)

◆ I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk

#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Msk (0xffffUL)

IC_HS_SCL_LCNT (Bitfield-Mask: 0xffff)

◆ I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos

#define I2C_I2C_HS_SCL_LCNT_REG_IC_HS_SCL_LCNT_Pos (0UL)

IC_HS_SCL_LCNT (Bit 0)

◆ I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk

#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Msk (0xffUL)

I2C_FS_SPKLEN (Bitfield-Mask: 0xff)

◆ I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos

#define I2C_I2C_IC_FS_SPKLEN_REG_I2C_FS_SPKLEN_Pos (0UL)

I2C_FS_SPKLEN (Bit 0)

◆ I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk

#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Msk (0xffUL)

I2C_HS_SPKLEN (Bitfield-Mask: 0xff)

◆ I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos

#define I2C_I2C_IC_HS_SPKLEN_REG_I2C_HS_SPKLEN_Pos (0UL)

I2C_HS_SPKLEN (Bit 0)

◆ I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk

#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Msk (0x100UL)

M_ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos

#define I2C_I2C_INTR_MASK_REG_M_ACTIVITY_Pos (8UL)

M_ACTIVITY (Bit 8)

◆ I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk

#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Msk (0x800UL)

M_GEN_CALL (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos

#define I2C_I2C_INTR_MASK_REG_M_GEN_CALL_Pos (11UL)

M_GEN_CALL (Bit 11)

◆ I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk

#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Msk (0x2000UL)

M_MASTER_ON_HOLD (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos

#define I2C_I2C_INTR_MASK_REG_M_MASTER_ON_HOLD_Pos (13UL)

M_MASTER_ON_HOLD (Bit 13)

◆ I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk

#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Msk (0x20UL)

M_RD_REQ (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos

#define I2C_I2C_INTR_MASK_REG_M_RD_REQ_Pos (5UL)

M_RD_REQ (Bit 5)

◆ I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk

#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Msk (0x1000UL)

M_RESTART_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos

#define I2C_I2C_INTR_MASK_REG_M_RESTART_DET_Pos (12UL)

M_RESTART_DET (Bit 12)

◆ I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Msk (0x80UL)

M_RX_DONE (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_DONE_Pos (7UL)

M_RX_DONE (Bit 7)

◆ I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Msk (0x4UL)

M_RX_FULL (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_FULL_Pos (2UL)

M_RX_FULL (Bit 2)

◆ I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Msk (0x2UL)

M_RX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_OVER_Pos (1UL)

M_RX_OVER (Bit 1)

◆ I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk

#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Msk (0x1UL)

M_RX_UNDER (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos

#define I2C_I2C_INTR_MASK_REG_M_RX_UNDER_Pos (0UL)

M_RX_UNDER (Bit 0)

◆ I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk

#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Msk (0x4000UL)

M_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos

#define I2C_I2C_INTR_MASK_REG_M_SCL_STUCK_AT_LOW_Pos (14UL)

M_SCL_STUCK_AT_LOW (Bit 14)

◆ I2C_I2C_INTR_MASK_REG_M_START_DET_Msk

#define I2C_I2C_INTR_MASK_REG_M_START_DET_Msk (0x400UL)

M_START_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_START_DET_Pos

#define I2C_I2C_INTR_MASK_REG_M_START_DET_Pos (10UL)

M_START_DET (Bit 10)

◆ I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk

#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Msk (0x200UL)

M_STOP_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos

#define I2C_I2C_INTR_MASK_REG_M_STOP_DET_Pos (9UL)

M_STOP_DET (Bit 9)

◆ I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk

#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Msk (0x40UL)

M_TX_ABRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos

#define I2C_I2C_INTR_MASK_REG_M_TX_ABRT_Pos (6UL)

M_TX_ABRT (Bit 6)

◆ I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk

#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Msk (0x10UL)

M_TX_EMPTY (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos

#define I2C_I2C_INTR_MASK_REG_M_TX_EMPTY_Pos (4UL)

M_TX_EMPTY (Bit 4)

◆ I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk

#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Msk (0x8UL)

M_TX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos

#define I2C_I2C_INTR_MASK_REG_M_TX_OVER_Pos (3UL)

M_TX_OVER (Bit 3)

◆ I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk

#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Msk (0x100UL)

R_ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos

#define I2C_I2C_INTR_STAT_REG_R_ACTIVITY_Pos (8UL)

R_ACTIVITY (Bit 8)

◆ I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk

#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Msk (0x800UL)

R_GEN_CALL (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos

#define I2C_I2C_INTR_STAT_REG_R_GEN_CALL_Pos (11UL)

R_GEN_CALL (Bit 11)

◆ I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk

#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Msk (0x2000UL)

R_MASTER_ON_HOLD (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos

#define I2C_I2C_INTR_STAT_REG_R_MASTER_ON_HOLD_Pos (13UL)

R_MASTER_ON_HOLD (Bit 13)

◆ I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk

#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Msk (0x20UL)

R_RD_REQ (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos

#define I2C_I2C_INTR_STAT_REG_R_RD_REQ_Pos (5UL)

R_RD_REQ (Bit 5)

◆ I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk

#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Msk (0x1000UL)

R_RESTART_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos

#define I2C_I2C_INTR_STAT_REG_R_RESTART_DET_Pos (12UL)

R_RESTART_DET (Bit 12)

◆ I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Msk (0x80UL)

R_RX_DONE (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_DONE_Pos (7UL)

R_RX_DONE (Bit 7)

◆ I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Msk (0x4UL)

R_RX_FULL (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_FULL_Pos (2UL)

R_RX_FULL (Bit 2)

◆ I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Msk (0x2UL)

R_RX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_OVER_Pos (1UL)

R_RX_OVER (Bit 1)

◆ I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk

#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Msk (0x1UL)

R_RX_UNDER (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos

#define I2C_I2C_INTR_STAT_REG_R_RX_UNDER_Pos (0UL)

R_RX_UNDER (Bit 0)

◆ I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk

#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Msk (0x4000UL)

R_SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos

#define I2C_I2C_INTR_STAT_REG_R_SCL_STUCK_AT_LOW_Pos (14UL)

R_SCL_STUCK_AT_LOW (Bit 14)

◆ I2C_I2C_INTR_STAT_REG_R_START_DET_Msk

#define I2C_I2C_INTR_STAT_REG_R_START_DET_Msk (0x400UL)

R_START_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_START_DET_Pos

#define I2C_I2C_INTR_STAT_REG_R_START_DET_Pos (10UL)

R_START_DET (Bit 10)

◆ I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk

#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Msk (0x200UL)

R_STOP_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos

#define I2C_I2C_INTR_STAT_REG_R_STOP_DET_Pos (9UL)

R_STOP_DET (Bit 9)

◆ I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk

#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Msk (0x40UL)

R_TX_ABRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos

#define I2C_I2C_INTR_STAT_REG_R_TX_ABRT_Pos (6UL)

R_TX_ABRT (Bit 6)

◆ I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk

#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Msk (0x10UL)

R_TX_EMPTY (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos

#define I2C_I2C_INTR_STAT_REG_R_TX_EMPTY_Pos (4UL)

R_TX_EMPTY (Bit 4)

◆ I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk

#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Msk (0x8UL)

R_TX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos

#define I2C_I2C_INTR_STAT_REG_R_TX_OVER_Pos (3UL)

R_TX_OVER (Bit 3)

◆ I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Msk (0x100UL)

ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_ACTIVITY_Pos (8UL)

ACTIVITY (Bit 8)

◆ I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Msk (0x800UL)

GEN_CALL (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_GEN_CALL_Pos (11UL)

GEN_CALL (Bit 11)

◆ I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Msk (0x2000UL)

MASTER_ON_HOLD (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_MASTER_ON_HOLD_Pos (13UL)

MASTER_ON_HOLD (Bit 13)

◆ I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Msk (0x20UL)

RD_REQ (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RD_REQ_Pos (5UL)

RD_REQ (Bit 5)

◆ I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Msk (0x1000UL)

RESTART_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RESTART_DET_Pos (12UL)

RESTART_DET (Bit 12)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Msk (0x80UL)

RX_DONE (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_DONE_Pos (7UL)

RX_DONE (Bit 7)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Msk (0x4UL)

RX_FULL (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_FULL_Pos (2UL)

RX_FULL (Bit 2)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Msk (0x2UL)

RX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_OVER_Pos (1UL)

RX_OVER (Bit 1)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Msk (0x1UL)

RX_UNDER (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_RX_UNDER_Pos (0UL)

RX_UNDER (Bit 0)

◆ I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Msk (0x4000UL)

SCL_STUCK_AT_LOW (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_SCL_STUCK_AT_LOW_Pos (14UL)

SCL_STUCK_AT_LOW (Bit 14)

◆ I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Msk (0x400UL)

START_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_START_DET_Pos (10UL)

START_DET (Bit 10)

◆ I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Msk (0x200UL)

STOP_DET (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_STOP_DET_Pos (9UL)

STOP_DET (Bit 9)

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Msk (0x40UL)

TX_ABRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_TX_ABRT_Pos (6UL)

TX_ABRT (Bit 6)

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Msk (0x10UL)

TX_EMPTY (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_TX_EMPTY_Pos (4UL)

TX_EMPTY (Bit 4)

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk

#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Msk (0x8UL)

TX_OVER (Bitfield-Mask: 0x01)

◆ I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos

#define I2C_I2C_RAW_INTR_STAT_REG_TX_OVER_Pos (3UL)

TX_OVER (Bit 3)

◆ I2C_I2C_RX_TL_REG_RX_TL_Msk

#define I2C_I2C_RX_TL_REG_RX_TL_Msk (0x1fUL)

RX_TL (Bitfield-Mask: 0x1f)

◆ I2C_I2C_RX_TL_REG_RX_TL_Pos

#define I2C_I2C_RX_TL_REG_RX_TL_Pos (0UL)

RX_TL (Bit 0)

◆ I2C_I2C_RXFLR_REG_RXFLR_Msk

#define I2C_I2C_RXFLR_REG_RXFLR_Msk (0x3fUL)

RXFLR (Bitfield-Mask: 0x3f)

◆ I2C_I2C_RXFLR_REG_RXFLR_Pos

#define I2C_I2C_RXFLR_REG_RXFLR_Pos (0UL)

RXFLR (Bit 0)

◆ I2C_I2C_SAR_REG_IC_SAR_Msk

#define I2C_I2C_SAR_REG_IC_SAR_Msk (0x3ffUL)

IC_SAR (Bitfield-Mask: 0x3ff)

◆ I2C_I2C_SAR_REG_IC_SAR_Pos

#define I2C_I2C_SAR_REG_IC_SAR_Pos (0UL)

IC_SAR (Bit 0)

◆ I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk

#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Msk (0xff0000UL)

I2C_SDA_RX_HOLD (Bitfield-Mask: 0xff)

◆ I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos

#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_RX_HOLD_Pos (16UL)

I2C_SDA_RX_HOLD (Bit 16)

◆ I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk

#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Msk (0xffffUL)

I2C_SDA_TX_HOLD (Bitfield-Mask: 0xffff)

◆ I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos

#define I2C_I2C_SDA_HOLD_REG_I2C_SDA_TX_HOLD_Pos (0UL)

I2C_SDA_TX_HOLD (Bit 0)

◆ I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk

#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Msk (0xffUL)

SDA_SETUP (Bitfield-Mask: 0xff)

◆ I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos

#define I2C_I2C_SDA_SETUP_REG_SDA_SETUP_Pos (0UL)

SDA_SETUP (Bit 0)

◆ I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk

#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Msk (0xffffUL)

IC_SS_SCL_HCNT (Bitfield-Mask: 0xffff)

◆ I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos

#define I2C_I2C_SS_SCL_HCNT_REG_IC_SS_SCL_HCNT_Pos (0UL)

IC_SS_SCL_HCNT (Bit 0)

◆ I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk

#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Msk (0xffffUL)

IC_SS_SCL_LCNT (Bitfield-Mask: 0xffff)

◆ I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos

#define I2C_I2C_SS_SCL_LCNT_REG_IC_SS_SCL_LCNT_Pos (0UL)

IC_SS_SCL_LCNT (Bit 0)

◆ I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk

#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Msk (0x1UL)

I2C_ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos

#define I2C_I2C_STATUS_REG_I2C_ACTIVITY_Pos (0UL)

I2C_ACTIVITY (Bit 0)

◆ I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk

#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Msk (0x400UL)

LV_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos

#define I2C_I2C_STATUS_REG_LV_HOLD_RX_FIFO_FULL_Pos (10UL)

LV_HOLD_RX_FIFO_FULL (Bit 10)

◆ I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk

#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Msk (0x20UL)

MST_ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos

#define I2C_I2C_STATUS_REG_MST_ACTIVITY_Pos (5UL)

MST_ACTIVITY (Bit 5)

◆ I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk

#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Msk (0x100UL)

MST_HOLD_RX_FIFO_FULL (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos

#define I2C_I2C_STATUS_REG_MST_HOLD_RX_FIFO_FULL_Pos (8UL)

MST_HOLD_RX_FIFO_FULL (Bit 8)

◆ I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk

#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Msk (0x80UL)

MST_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos

#define I2C_I2C_STATUS_REG_MST_HOLD_TX_FIFO_EMPTY_Pos (7UL)

MST_HOLD_TX_FIFO_EMPTY (Bit 7)

◆ I2C_I2C_STATUS_REG_RFF_Msk

#define I2C_I2C_STATUS_REG_RFF_Msk (0x10UL)

RFF (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_RFF_Pos

#define I2C_I2C_STATUS_REG_RFF_Pos (4UL)

RFF (Bit 4)

◆ I2C_I2C_STATUS_REG_RFNE_Msk

#define I2C_I2C_STATUS_REG_RFNE_Msk (0x8UL)

RFNE (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_RFNE_Pos

#define I2C_I2C_STATUS_REG_RFNE_Pos (3UL)

RFNE (Bit 3)

◆ I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk

#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Msk (0x40UL)

SLV_ACTIVITY (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos

#define I2C_I2C_STATUS_REG_SLV_ACTIVITY_Pos (6UL)

SLV_ACTIVITY (Bit 6)

◆ I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk

#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Msk (0x200UL)

SLV_HOLD_TX_FIFO_EMPTY (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos

#define I2C_I2C_STATUS_REG_SLV_HOLD_TX_FIFO_EMPTY_Pos (9UL)

SLV_HOLD_TX_FIFO_EMPTY (Bit 9)

◆ I2C_I2C_STATUS_REG_TFE_Msk

#define I2C_I2C_STATUS_REG_TFE_Msk (0x4UL)

TFE (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_TFE_Pos

#define I2C_I2C_STATUS_REG_TFE_Pos (2UL)

TFE (Bit 2)

◆ I2C_I2C_STATUS_REG_TFNF_Msk

#define I2C_I2C_STATUS_REG_TFNF_Msk (0x2UL)

TFNF (Bitfield-Mask: 0x01)

◆ I2C_I2C_STATUS_REG_TFNF_Pos

#define I2C_I2C_STATUS_REG_TFNF_Pos (1UL)

TFNF (Bit 1)

◆ I2C_I2C_TAR_REG_GC_OR_START_Msk

#define I2C_I2C_TAR_REG_GC_OR_START_Msk (0x400UL)

GC_OR_START (Bitfield-Mask: 0x01)

◆ I2C_I2C_TAR_REG_GC_OR_START_Pos

#define I2C_I2C_TAR_REG_GC_OR_START_Pos (10UL)

GC_OR_START (Bit 10)

◆ I2C_I2C_TAR_REG_IC_TAR_Msk

#define I2C_I2C_TAR_REG_IC_TAR_Msk (0x3ffUL)

IC_TAR (Bitfield-Mask: 0x3ff)

◆ I2C_I2C_TAR_REG_IC_TAR_Pos

#define I2C_I2C_TAR_REG_IC_TAR_Pos (0UL)

IC_TAR (Bit 0)

◆ I2C_I2C_TAR_REG_SPECIAL_Msk

#define I2C_I2C_TAR_REG_SPECIAL_Msk (0x800UL)

SPECIAL (Bitfield-Mask: 0x01)

◆ I2C_I2C_TAR_REG_SPECIAL_Pos

#define I2C_I2C_TAR_REG_SPECIAL_Pos (11UL)

SPECIAL (Bit 11)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Msk (0x2UL)

ABRT_10ADDR1_NOACK (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR1_NOACK_Pos (1UL)

ABRT_10ADDR1_NOACK (Bit 1)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Msk (0x4UL)

ABRT_10ADDR2_NOACK (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10ADDR2_NOACK_Pos (2UL)

ABRT_10ADDR2_NOACK (Bit 2)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Msk (0x400UL)

ABRT_10B_RD_NORSTRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_10B_RD_NORSTRT_Pos (10UL)

ABRT_10B_RD_NORSTRT (Bit 10)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Msk (0x1UL)

ABRT_7B_ADDR_NOACK (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_7B_ADDR_NOACK_Pos (0UL)

ABRT_7B_ADDR_NOACK (Bit 0)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Msk (0x10UL)

ABRT_GCALL_NOACK (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_NOACK_Pos (4UL)

ABRT_GCALL_NOACK (Bit 4)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Msk (0x20UL)

ABRT_GCALL_READ (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_GCALL_READ_Pos (5UL)

ABRT_GCALL_READ (Bit 5)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Msk (0x40UL)

ABRT_HS_ACKDET (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_ACKDET_Pos (6UL)

ABRT_HS_ACKDET (Bit 6)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Msk (0x100UL)

ABRT_HS_NORSTRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_HS_NORSTRT_Pos (8UL)

ABRT_HS_NORSTRT (Bit 8)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Msk (0x800UL)

ABRT_MASTER_DIS (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_MASTER_DIS_Pos (11UL)

ABRT_MASTER_DIS (Bit 11)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Msk (0x80UL)

ABRT_SBYTE_ACKDET (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_ACKDET_Pos (7UL)

ABRT_SBYTE_ACKDET (Bit 7)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Msk (0x200UL)

ABRT_SBYTE_NORSTRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SBYTE_NORSTRT_Pos (9UL)

ABRT_SBYTE_NORSTRT (Bit 9)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Msk (0x4000UL)

ABRT_SLV_ARBLOST (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLV_ARBLOST_Pos (14UL)

ABRT_SLV_ARBLOST (Bit 14)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Msk (0x2000UL)

ABRT_SLVFLUSH_TXFIFO (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVFLUSH_TXFIFO_Pos (13UL)

ABRT_SLVFLUSH_TXFIFO (Bit 13)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Msk (0x8000UL)

ABRT_SLVRD_INTX (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_SLVRD_INTX_Pos (15UL)

ABRT_SLVRD_INTX (Bit 15)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Msk (0x8UL)

ABRT_TXDATA_NOACK (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_TXDATA_NOACK_Pos (3UL)

ABRT_TXDATA_NOACK (Bit 3)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Msk (0x10000UL)

ABRT_USER_ABRT (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ABRT_USER_ABRT_Pos (16UL)

ABRT_USER_ABRT (Bit 16)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk

#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Msk (0x1000UL)

ARB_LOST (Bitfield-Mask: 0x01)

◆ I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos

#define I2C_I2C_TX_ABRT_SOURCE_REG_ARB_LOST_Pos (12UL)

ARB_LOST (Bit 12)

◆ I2C_I2C_TX_TL_REG_TX_TL_Msk

#define I2C_I2C_TX_TL_REG_TX_TL_Msk (0x1fUL)

TX_TL (Bitfield-Mask: 0x1f)

◆ I2C_I2C_TX_TL_REG_TX_TL_Pos

#define I2C_I2C_TX_TL_REG_TX_TL_Pos (0UL)

TX_TL (Bit 0)

◆ I2C_I2C_TXFLR_REG_TXFLR_Msk

#define I2C_I2C_TXFLR_REG_TXFLR_Msk (0x3fUL)

TXFLR (Bitfield-Mask: 0x3f)

◆ I2C_I2C_TXFLR_REG_TXFLR_Pos

#define I2C_I2C_TXFLR_REG_TXFLR_Pos (0UL)

TXFLR (Bit 0)

◆ MDCT_MDCT_CTRL_REG_CLK_DIV_Msk

#define MDCT_MDCT_CTRL_REG_CLK_DIV_Msk (0xc000000UL)

CLK_DIV (Bitfield-Mask: 0x03)

◆ MDCT_MDCT_CTRL_REG_CLK_DIV_Pos

#define MDCT_MDCT_CTRL_REG_CLK_DIV_Pos (26UL)

CLK_DIV (Bit 26)

◆ MDCT_MDCT_CTRL_REG_DONE_Msk

#define MDCT_MDCT_CTRL_REG_DONE_Msk (0x80000000UL)

DONE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_DONE_Pos

#define MDCT_MDCT_CTRL_REG_DONE_Pos (31UL)

DONE (Bit 31)

◆ MDCT_MDCT_CTRL_REG_EN_Msk

#define MDCT_MDCT_CTRL_REG_EN_Msk (0x1UL)

EN (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_EN_Pos

#define MDCT_MDCT_CTRL_REG_EN_Pos (0UL)

EN (Bit 0)

◆ MDCT_MDCT_CTRL_REG_INVERSE_Msk

#define MDCT_MDCT_CTRL_REG_INVERSE_Msk (0x40UL)

INVERSE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_INVERSE_Pos

#define MDCT_MDCT_CTRL_REG_INVERSE_Pos (6UL)

INVERSE (Bit 6)

◆ MDCT_MDCT_CTRL_REG_IRQ_CLR_Msk

#define MDCT_MDCT_CTRL_REG_IRQ_CLR_Msk (0x10000000UL)

IRQ_CLR (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_IRQ_CLR_Pos

#define MDCT_MDCT_CTRL_REG_IRQ_CLR_Pos (28UL)

IRQ_CLR (Bit 28)

◆ MDCT_MDCT_CTRL_REG_IRQ_EN_Msk

#define MDCT_MDCT_CTRL_REG_IRQ_EN_Msk (0x2UL)

IRQ_EN (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_IRQ_EN_Pos

#define MDCT_MDCT_CTRL_REG_IRQ_EN_Pos (1UL)

IRQ_EN (Bit 1)

◆ MDCT_MDCT_CTRL_REG_N_STAGES_Msk

#define MDCT_MDCT_CTRL_REG_N_STAGES_Msk (0x3cUL)

N_STAGES (Bitfield-Mask: 0x0f)

◆ MDCT_MDCT_CTRL_REG_N_STAGES_Pos

#define MDCT_MDCT_CTRL_REG_N_STAGES_Pos (2UL)

N_STAGES (Bit 2)

◆ MDCT_MDCT_CTRL_REG_USE_CORDIC_Msk

#define MDCT_MDCT_CTRL_REG_USE_CORDIC_Msk (0x20000000UL)

USE_CORDIC (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_USE_CORDIC_Pos

#define MDCT_MDCT_CTRL_REG_USE_CORDIC_Pos (29UL)

USE_CORDIC (Bit 29)

◆ MDCT_MDCT_CTRL_REG_WORD_SIZE_Msk

#define MDCT_MDCT_CTRL_REG_WORD_SIZE_Msk (0x80UL)

WORD_SIZE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_CTRL_REG_WORD_SIZE_Pos

#define MDCT_MDCT_CTRL_REG_WORD_SIZE_Pos (7UL)

WORD_SIZE (Bit 7)

◆ MDCT_MDCT_CTRL_REG_XFORM_SIZE_Msk

#define MDCT_MDCT_CTRL_REG_XFORM_SIZE_Msk (0x3ff0000UL)

XFORM_SIZE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_CTRL_REG_XFORM_SIZE_Pos

#define MDCT_MDCT_CTRL_REG_XFORM_SIZE_Pos (16UL)

XFORM_SIZE (Bit 16)

◆ MDCT_MDCT_CTRL_REG_Y_STRIDE_Msk

#define MDCT_MDCT_CTRL_REG_Y_STRIDE_Msk (0xff00UL)

Y_STRIDE (Bitfield-Mask: 0xff)

◆ MDCT_MDCT_CTRL_REG_Y_STRIDE_Pos

#define MDCT_MDCT_CTRL_REG_Y_STRIDE_Pos (8UL)

Y_STRIDE (Bit 8)

◆ MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Msk

#define MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Msk (0xffffffffUL)

PHASE_INC (Bitfield-Mask: 0xffffffff)

◆ MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Pos

#define MDCT_MDCT_PHASE_INC_REG_PHASE_INC_Pos (0UL)

PHASE_INC (Bit 0)

◆ MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE0_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE0_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE0_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE0_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE0_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE0_REG_M_Msk

#define MDCT_MDCT_STAGE0_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE0_REG_M_Pos

#define MDCT_MDCT_STAGE0_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE0_REG_MODE_Msk

#define MDCT_MDCT_STAGE0_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE0_REG_MODE_Pos

#define MDCT_MDCT_STAGE0_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE0_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE0_REG_RADIX_Msk

#define MDCT_MDCT_STAGE0_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE0_REG_RADIX_Pos

#define MDCT_MDCT_STAGE0_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE0_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE0_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE0_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE0_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE1_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE1_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE1_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE1_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE1_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE1_REG_M_Msk

#define MDCT_MDCT_STAGE1_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE1_REG_M_Pos

#define MDCT_MDCT_STAGE1_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE1_REG_MODE_Msk

#define MDCT_MDCT_STAGE1_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE1_REG_MODE_Pos

#define MDCT_MDCT_STAGE1_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE1_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE1_REG_RADIX_Msk

#define MDCT_MDCT_STAGE1_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE1_REG_RADIX_Pos

#define MDCT_MDCT_STAGE1_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE1_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE1_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE1_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE1_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE2_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE2_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE2_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE2_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE2_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE2_REG_M_Msk

#define MDCT_MDCT_STAGE2_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE2_REG_M_Pos

#define MDCT_MDCT_STAGE2_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE2_REG_MODE_Msk

#define MDCT_MDCT_STAGE2_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE2_REG_MODE_Pos

#define MDCT_MDCT_STAGE2_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE2_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE2_REG_RADIX_Msk

#define MDCT_MDCT_STAGE2_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE2_REG_RADIX_Pos

#define MDCT_MDCT_STAGE2_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE2_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE2_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE2_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE2_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE3_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE3_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE3_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE3_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE3_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE3_REG_M_Msk

#define MDCT_MDCT_STAGE3_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE3_REG_M_Pos

#define MDCT_MDCT_STAGE3_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE3_REG_MODE_Msk

#define MDCT_MDCT_STAGE3_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE3_REG_MODE_Pos

#define MDCT_MDCT_STAGE3_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE3_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE3_REG_RADIX_Msk

#define MDCT_MDCT_STAGE3_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE3_REG_RADIX_Pos

#define MDCT_MDCT_STAGE3_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE3_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE3_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE3_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE3_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE4_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE4_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE4_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE4_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE4_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE4_REG_M_Msk

#define MDCT_MDCT_STAGE4_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE4_REG_M_Pos

#define MDCT_MDCT_STAGE4_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE4_REG_MODE_Msk

#define MDCT_MDCT_STAGE4_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE4_REG_MODE_Pos

#define MDCT_MDCT_STAGE4_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE4_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE4_REG_RADIX_Msk

#define MDCT_MDCT_STAGE4_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE4_REG_RADIX_Pos

#define MDCT_MDCT_STAGE4_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE4_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE4_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE4_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE4_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE5_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE5_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE5_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE5_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE5_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE5_REG_M_Msk

#define MDCT_MDCT_STAGE5_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE5_REG_M_Pos

#define MDCT_MDCT_STAGE5_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE5_REG_MODE_Msk

#define MDCT_MDCT_STAGE5_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE5_REG_MODE_Pos

#define MDCT_MDCT_STAGE5_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE5_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE5_REG_RADIX_Msk

#define MDCT_MDCT_STAGE5_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE5_REG_RADIX_Pos

#define MDCT_MDCT_STAGE5_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE5_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE5_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE5_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE5_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE6_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE6_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE6_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE6_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE6_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE6_REG_M_Msk

#define MDCT_MDCT_STAGE6_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE6_REG_M_Pos

#define MDCT_MDCT_STAGE6_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE6_REG_MODE_Msk

#define MDCT_MDCT_STAGE6_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE6_REG_MODE_Pos

#define MDCT_MDCT_STAGE6_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE6_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE6_REG_RADIX_Msk

#define MDCT_MDCT_STAGE6_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE6_REG_RADIX_Pos

#define MDCT_MDCT_STAGE6_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE6_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE6_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE6_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE6_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Msk

#define MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Msk (0x40UL)

IN_ADDR_MODE (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Pos

#define MDCT_MDCT_STAGE7_REG_IN_ADDR_MODE_Pos (6UL)

IN_ADDR_MODE (Bit 6)

◆ MDCT_MDCT_STAGE7_REG_IN_BUFFER_Msk

#define MDCT_MDCT_STAGE7_REG_IN_BUFFER_Msk (0x10UL)

IN_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE7_REG_IN_BUFFER_Pos

#define MDCT_MDCT_STAGE7_REG_IN_BUFFER_Pos (4UL)

IN_BUFFER (Bit 4)

◆ MDCT_MDCT_STAGE7_REG_M_Msk

#define MDCT_MDCT_STAGE7_REG_M_Msk (0x3ff000UL)

M (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE7_REG_M_Pos

#define MDCT_MDCT_STAGE7_REG_M_Pos (12UL)

M (Bit 12)

◆ MDCT_MDCT_STAGE7_REG_MODE_Msk

#define MDCT_MDCT_STAGE7_REG_MODE_Msk (0x7UL)

MODE (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE7_REG_MODE_Pos

#define MDCT_MDCT_STAGE7_REG_MODE_Pos (0UL)

MODE (Bit 0)

◆ MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Msk

#define MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Msk (0x20UL)

OUT_BUFFER (Bitfield-Mask: 0x01)

◆ MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Pos

#define MDCT_MDCT_STAGE7_REG_OUT_BUFFER_Pos (5UL)

OUT_BUFFER (Bit 5)

◆ MDCT_MDCT_STAGE7_REG_RADIX_Msk

#define MDCT_MDCT_STAGE7_REG_RADIX_Msk (0x700UL)

RADIX (Bitfield-Mask: 0x07)

◆ MDCT_MDCT_STAGE7_REG_RADIX_Pos

#define MDCT_MDCT_STAGE7_REG_RADIX_Pos (8UL)

RADIX (Bit 8)

◆ MDCT_MDCT_STAGE7_REG_STRIDE_Msk

#define MDCT_MDCT_STAGE7_REG_STRIDE_Msk (0xffc00000UL)

STRIDE (Bitfield-Mask: 0x3ff)

◆ MDCT_MDCT_STAGE7_REG_STRIDE_Pos

#define MDCT_MDCT_STAGE7_REG_STRIDE_Pos (22UL)

STRIDE (Bit 22)

◆ MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Msk

#define MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Msk (0xffffffffUL)

XBASE_ADDR (Bitfield-Mask: 0xffffffff)

◆ MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Pos

#define MDCT_MDCT_XBASE_ADDR_REG_XBASE_ADDR_Pos (0UL)

XBASE_ADDR (Bit 0)

◆ MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Msk

#define MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Msk (0xffffffffUL)

YBASE_ADDR (Bitfield-Mask: 0xffffffff)

◆ MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Pos

#define MDCT_MDCT_YBASE_ADDR_REG_YBASE_ADDR_Pos (0UL)

YBASE_ADDR (Bit 0)

◆ MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Msk

#define MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Msk (0xffffffffUL)

ZBASE_ADDR (Bitfield-Mask: 0xffffffff)

◆ MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Pos

#define MDCT_MDCT_ZBASE_ADDR_REG_ZBASE_ADDR_Pos (0UL)

ZBASE_ADDR (Bit 0)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Msk (0x300UL)

BUSY_GPADC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_GPADC_Pos (8UL)

BUSY_GPADC (Bit 8)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Msk (0xc0UL)

BUSY_I2C (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_I2C_Pos (6UL)

BUSY_I2C (Bit 6)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Msk (0x30000UL)

BUSY_PCM (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_PCM_Pos (16UL)

BUSY_PCM (Bit 16)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Msk (0xc0000UL)

BUSY_PDM (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_PDM_Pos (18UL)

BUSY_PDM (Bit 18)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Msk (0xc00UL)

BUSY_SDADC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_SDADC_Pos (10UL)

BUSY_SDADC (Bit 10)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Msk (0x30000000UL)

BUSY_SPARE1 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE1_Pos (28UL)

BUSY_SPARE1 (Bit 28)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Msk (0xc0000000UL)

BUSY_SPARE (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_SPARE_Pos (30UL)

BUSY_SPARE (Bit 30)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Msk (0x30UL)

BUSY_SPI (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_SPI_Pos (4UL)

BUSY_SPI (Bit 4)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Msk (0xc000UL)

BUSY_SRC2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC2_Pos (14UL)

BUSY_SRC2 (Bit 14)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Msk (0x3000UL)

BUSY_SRC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_SRC_Pos (12UL)

BUSY_SRC (Bit 12)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Msk (0xc00000UL)

BUSY_TIMER2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER2_Pos (22UL)

BUSY_TIMER2 (Bit 22)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Msk (0x3000000UL)

BUSY_TIMER3 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER3_Pos (24UL)

BUSY_TIMER3 (Bit 24)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Msk (0xc000000UL)

BUSY_TIMER4 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER4_Pos (26UL)

BUSY_TIMER4 (Bit 26)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Msk (0x300000UL)

BUSY_TIMER (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_TIMER_Pos (20UL)

BUSY_TIMER (Bit 20)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Msk (0xcUL)

BUSY_UART2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_UART2_Pos (2UL)

BUSY_UART2 (Bit 2)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk

#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Msk (0x3UL)

BUSY_UART (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos

#define MEMCTRL_BUSY_RESET_REG_BUSY_UART_Pos (0UL)

BUSY_UART (Bit 0)

◆ MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Msk (0x300UL)

BUSY_GPADC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_GPADC_Pos (8UL)

BUSY_GPADC (Bit 8)

◆ MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Msk (0xc0UL)

BUSY_I2C (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_I2C_Pos (6UL)

BUSY_I2C (Bit 6)

◆ MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Msk (0x30000UL)

BUSY_PCM (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_PCM_Pos (16UL)

BUSY_PCM (Bit 16)

◆ MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Msk (0xc0000UL)

BUSY_PDM (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_PDM_Pos (18UL)

BUSY_PDM (Bit 18)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Msk (0xc00UL)

BUSY_SDADC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_SDADC_Pos (10UL)

BUSY_SDADC (Bit 10)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Msk (0x30000000UL)

BUSY_SPARE1 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE1_Pos (28UL)

BUSY_SPARE1 (Bit 28)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Msk (0xc0000000UL)

BUSY_SPARE (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_SPARE_Pos (30UL)

BUSY_SPARE (Bit 30)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Msk (0x30UL)

BUSY_SPI (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_SPI_Pos (4UL)

BUSY_SPI (Bit 4)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Msk (0xc000UL)

BUSY_SRC2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_SRC2_Pos (14UL)

BUSY_SRC2 (Bit 14)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Msk (0x3000UL)

BUSY_SRC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_SRC_Pos (12UL)

BUSY_SRC (Bit 12)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Msk (0xc00000UL)

BUSY_TIMER2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER2_Pos (22UL)

BUSY_TIMER2 (Bit 22)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Msk (0x3000000UL)

BUSY_TIMER3 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER3_Pos (24UL)

BUSY_TIMER3 (Bit 24)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Msk (0xc000000UL)

BUSY_TIMER4 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER4_Pos (26UL)

BUSY_TIMER4 (Bit 26)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Msk (0x300000UL)

BUSY_TIMER (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_TIMER_Pos (20UL)

BUSY_TIMER (Bit 20)

◆ MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Msk (0xcUL)

BUSY_UART2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_UART2_Pos (2UL)

BUSY_UART2 (Bit 2)

◆ MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk

#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Msk (0x3UL)

BUSY_UART (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos

#define MEMCTRL_BUSY_SET_REG_BUSY_UART_Pos (0UL)

BUSY_UART (Bit 0)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Msk (0x300UL)

BUSY_GPADC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_GPADC_Pos (8UL)

BUSY_GPADC (Bit 8)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Msk (0xc0UL)

BUSY_I2C (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_I2C_Pos (6UL)

BUSY_I2C (Bit 6)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Msk (0x30000UL)

BUSY_PCM (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_PCM_Pos (16UL)

BUSY_PCM (Bit 16)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Msk (0xc0000UL)

BUSY_PDM (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_PDM_Pos (18UL)

BUSY_PDM (Bit 18)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Msk (0xc00UL)

BUSY_SDADC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_SDADC_Pos (10UL)

BUSY_SDADC (Bit 10)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Msk (0x30000000UL)

BUSY_SPARE1 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE1_Pos (28UL)

BUSY_SPARE1 (Bit 28)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Msk (0xc0000000UL)

BUSY_SPARE (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_SPARE_Pos (30UL)

BUSY_SPARE (Bit 30)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Msk (0x30UL)

BUSY_SPI (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_SPI_Pos (4UL)

BUSY_SPI (Bit 4)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Msk (0xc000UL)

BUSY_SRC2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC2_Pos (14UL)

BUSY_SRC2 (Bit 14)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Msk (0x3000UL)

BUSY_SRC (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_SRC_Pos (12UL)

BUSY_SRC (Bit 12)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Msk (0xc00000UL)

BUSY_TIMER2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER2_Pos (22UL)

BUSY_TIMER2 (Bit 22)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Msk (0x3000000UL)

BUSY_TIMER3 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER3_Pos (24UL)

BUSY_TIMER3 (Bit 24)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Msk (0xc000000UL)

BUSY_TIMER4 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER4_Pos (26UL)

BUSY_TIMER4 (Bit 26)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Msk (0x300000UL)

BUSY_TIMER (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_TIMER_Pos (20UL)

BUSY_TIMER (Bit 20)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Msk (0xcUL)

BUSY_UART2 (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_UART2_Pos (2UL)

BUSY_UART2 (Bit 2)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk

#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Msk (0x3UL)

BUSY_UART (Bitfield-Mask: 0x03)

◆ MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos

#define MEMCTRL_BUSY_STAT_REG_BUSY_UART_Pos (0UL)

BUSY_UART (Bit 0)

◆ MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk

#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Msk (0x7ff00UL)

CMI_CODE_BASE_ADDR (Bitfield-Mask: 0x7ff)

◆ MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos

#define MEMCTRL_CMI_CODE_BASE_REG_CMI_CODE_BASE_ADDR_Pos (8UL)

CMI_CODE_BASE_ADDR (Bit 8)

◆ MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk

#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Msk (0x7fffcUL)

CMI_DATA_BASE_ADDR (Bitfield-Mask: 0x1ffff)

◆ MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos

#define MEMCTRL_CMI_DATA_BASE_REG_CMI_DATA_BASE_ADDR_Pos (2UL)

CMI_DATA_BASE_ADDR (Bit 2)

◆ MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk

#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Msk (0x7fffcUL)

CMI_SHARED_BASE_ADDR (Bitfield-Mask: 0x1ffff)

◆ MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos

#define MEMCTRL_CMI_SHARED_BASE_REG_CMI_SHARED_BASE_ADDR_Pos (2UL)

CMI_SHARED_BASE_ADDR (Bit 2)

◆ MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk

#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Msk (0x38UL)

AHB2_PRIO (Bitfield-Mask: 0x07)

◆ MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos

#define MEMCTRL_MEM_PRIO_REG_AHB2_PRIO_Pos (3UL)

AHB2_PRIO (Bit 3)

◆ MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Msk

#define MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Msk (0x1c0UL)

AHB3_PRIO (Bitfield-Mask: 0x07)

◆ MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Pos

#define MEMCTRL_MEM_PRIO_REG_AHB3_PRIO_Pos (6UL)

AHB3_PRIO (Bit 6)

◆ MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk

#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Msk (0x7UL)

AHB_PRIO (Bitfield-Mask: 0x07)

◆ MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos

#define MEMCTRL_MEM_PRIO_REG_AHB_PRIO_Pos (0UL)

AHB_PRIO (Bit 0)

◆ MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk

#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Msk (0xf0UL)

AHB2_MAX_STALL (Bitfield-Mask: 0x0f)

◆ MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos

#define MEMCTRL_MEM_STALL_REG_AHB2_MAX_STALL_Pos (4UL)

AHB2_MAX_STALL (Bit 4)

◆ MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Msk

#define MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Msk (0xf00UL)

AHB3_MAX_STALL (Bitfield-Mask: 0x0f)

◆ MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Pos

#define MEMCTRL_MEM_STALL_REG_AHB3_MAX_STALL_Pos (8UL)

AHB3_MAX_STALL (Bit 8)

◆ MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk

#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Msk (0xfUL)

AHB_MAX_STALL (Bitfield-Mask: 0x0f)

◆ MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos

#define MEMCTRL_MEM_STALL_REG_AHB_MAX_STALL_Pos (0UL)

AHB_MAX_STALL (Bit 0)

◆ MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk

#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Msk (0x1UL)

RAM1_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos

#define MEMCTRL_MEM_STATUS2_REG_RAM1_OFF_BUT_ACCESS_Pos (0UL)

RAM1_OFF_BUT_ACCESS (Bit 0)

◆ MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk

#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Msk (0x2UL)

RAM2_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos

#define MEMCTRL_MEM_STATUS2_REG_RAM2_OFF_BUT_ACCESS_Pos (1UL)

RAM2_OFF_BUT_ACCESS (Bit 1)

◆ MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk

#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Msk (0x4UL)

RAM3_OFF_BUT_ACCESS (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos

#define MEMCTRL_MEM_STATUS2_REG_RAM3_OFF_BUT_ACCESS_Pos (2UL)

RAM3_OFF_BUT_ACCESS (Bit 2)

◆ MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Msk (0x20UL)

AHB2_CLR_WR_BUFF (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB2_CLR_WR_BUFF_Pos (5UL)

AHB2_CLR_WR_BUFF (Bit 5)

◆ MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Msk (0xf000UL)

AHB2_WR_BUFF_CNT (Bitfield-Mask: 0x0f)

◆ MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB2_WR_BUFF_CNT_Pos (12UL)

AHB2_WR_BUFF_CNT (Bit 12)

◆ MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Msk (0x2UL)

AHB2_WRITE_BUFF (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB2_WRITE_BUFF_Pos (1UL)

AHB2_WRITE_BUFF (Bit 1)

◆ MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Msk (0x40UL)

AHB3_CLR_WR_BUFF (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB3_CLR_WR_BUFF_Pos (6UL)

AHB3_CLR_WR_BUFF (Bit 6)

◆ MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Msk (0xf0000UL)

AHB3_WR_BUFF_CNT (Bitfield-Mask: 0x0f)

◆ MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB3_WR_BUFF_CNT_Pos (16UL)

AHB3_WR_BUFF_CNT (Bit 16)

◆ MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Msk (0x4UL)

AHB3_WRITE_BUFF (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB3_WRITE_BUFF_Pos (2UL)

AHB3_WRITE_BUFF (Bit 2)

◆ MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Msk (0x10UL)

AHB_CLR_WR_BUFF (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB_CLR_WR_BUFF_Pos (4UL)

AHB_CLR_WR_BUFF (Bit 4)

◆ MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Msk (0xf00UL)

AHB_WR_BUFF_CNT (Bitfield-Mask: 0x0f)

◆ MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB_WR_BUFF_CNT_Pos (8UL)

AHB_WR_BUFF_CNT (Bit 8)

◆ MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk

#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Msk (0x1UL)

AHB_WRITE_BUFF (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos

#define MEMCTRL_MEM_STATUS_REG_AHB_WRITE_BUFF_Pos (0UL)

AHB_WRITE_BUFF (Bit 0)

◆ MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Msk

#define MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Msk (0x200000UL)

MTB_CLEAR_READY (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Pos

#define MEMCTRL_MEM_STATUS_REG_MTB_CLEAR_READY_Pos (21UL)

MTB_CLEAR_READY (Bit 21)

◆ MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Msk

#define MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Msk (0x100000UL)

MTB_NOT_READY (Bitfield-Mask: 0x01)

◆ MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Pos

#define MEMCTRL_MEM_STATUS_REG_MTB_NOT_READY_Pos (20UL)

MTB_NOT_READY (Bit 20)

◆ PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Msk

#define PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Msk (0xf800UL)

PCM_CH_DEL (Bitfield-Mask: 0x1f)

◆ PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Pos

#define PCM1_PCM1_CTRL_REG_PCM_CH_DEL_Pos (11UL)

PCM_CH_DEL (Bit 11)

◆ PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Msk

#define PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Msk (0x400UL)

PCM_CLK_BIT (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Pos

#define PCM1_PCM1_CTRL_REG_PCM_CLK_BIT_Pos (10UL)

PCM_CLK_BIT (Bit 10)

◆ PCM1_PCM1_CTRL_REG_PCM_CLKINV_Msk

#define PCM1_PCM1_CTRL_REG_PCM_CLKINV_Msk (0x100UL)

PCM_CLKINV (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_CLKINV_Pos

#define PCM1_PCM1_CTRL_REG_PCM_CLKINV_Pos (8UL)

PCM_CLKINV (Bit 8)

◆ PCM1_PCM1_CTRL_REG_PCM_EN_Msk

#define PCM1_PCM1_CTRL_REG_PCM_EN_Msk (0x1UL)

PCM_EN (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_EN_Pos

#define PCM1_PCM1_CTRL_REG_PCM_EN_Pos (0UL)

PCM_EN (Bit 0)

◆ PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Msk

#define PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Msk (0xfff00000UL)

PCM_FSC_DIV (Bitfield-Mask: 0xfff)

◆ PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Pos

#define PCM1_PCM1_CTRL_REG_PCM_FSC_DIV_Pos (20UL)

PCM_FSC_DIV (Bit 20)

◆ PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk

#define PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Msk (0x10000UL)

PCM_FSC_EDGE (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos

#define PCM1_PCM1_CTRL_REG_PCM_FSC_EDGE_Pos (16UL)

PCM_FSC_EDGE (Bit 16)

◆ PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Msk

#define PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Msk (0x40UL)

PCM_FSCDEL (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Pos

#define PCM1_PCM1_CTRL_REG_PCM_FSCDEL_Pos (6UL)

PCM_FSCDEL (Bit 6)

◆ PCM1_PCM1_CTRL_REG_PCM_FSCINV_Msk

#define PCM1_PCM1_CTRL_REG_PCM_FSCINV_Msk (0x200UL)

PCM_FSCINV (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_FSCINV_Pos

#define PCM1_PCM1_CTRL_REG_PCM_FSCINV_Pos (9UL)

PCM_FSCINV (Bit 9)

◆ PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Msk

#define PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Msk (0x3cUL)

PCM_FSCLEN (Bitfield-Mask: 0x0f)

◆ PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Pos

#define PCM1_PCM1_CTRL_REG_PCM_FSCLEN_Pos (2UL)

PCM_FSCLEN (Bit 2)

◆ PCM1_PCM1_CTRL_REG_PCM_MASTER_Msk

#define PCM1_PCM1_CTRL_REG_PCM_MASTER_Msk (0x2UL)

PCM_MASTER (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_MASTER_Pos

#define PCM1_PCM1_CTRL_REG_PCM_MASTER_Pos (1UL)

PCM_MASTER (Bit 1)

◆ PCM1_PCM1_CTRL_REG_PCM_PPOD_Msk

#define PCM1_PCM1_CTRL_REG_PCM_PPOD_Msk (0x80UL)

PCM_PPOD (Bitfield-Mask: 0x01)

◆ PCM1_PCM1_CTRL_REG_PCM_PPOD_Pos

#define PCM1_PCM1_CTRL_REG_PCM_PPOD_Pos (7UL)

PCM_PPOD (Bit 7)

◆ PCM1_PCM1_IN1_REG_PCM_IN_Msk

#define PCM1_PCM1_IN1_REG_PCM_IN_Msk (0xffffffffUL)

PCM_IN (Bitfield-Mask: 0xffffffff)

◆ PCM1_PCM1_IN1_REG_PCM_IN_Pos

#define PCM1_PCM1_IN1_REG_PCM_IN_Pos (0UL)

PCM_IN (Bit 0)

◆ PCM1_PCM1_IN2_REG_PCM_IN_Msk

#define PCM1_PCM1_IN2_REG_PCM_IN_Msk (0xffffffffUL)

PCM_IN (Bitfield-Mask: 0xffffffff)

◆ PCM1_PCM1_IN2_REG_PCM_IN_Pos

#define PCM1_PCM1_IN2_REG_PCM_IN_Pos (0UL)

PCM_IN (Bit 0)

◆ PCM1_PCM1_OUT1_REG_PCM_OUT_Msk

#define PCM1_PCM1_OUT1_REG_PCM_OUT_Msk (0xffffffffUL)

PCM_OUT (Bitfield-Mask: 0xffffffff)

◆ PCM1_PCM1_OUT1_REG_PCM_OUT_Pos

#define PCM1_PCM1_OUT1_REG_PCM_OUT_Pos (0UL)

PCM_OUT (Bit 0)

◆ PCM1_PCM1_OUT2_REG_PCM_OUT_Msk

#define PCM1_PCM1_OUT2_REG_PCM_OUT_Msk (0xffffffffUL)

PCM_OUT (Bitfield-Mask: 0xffffffff)

◆ PCM1_PCM1_OUT2_REG_PCM_OUT_Pos

#define PCM1_PCM1_OUT2_REG_PCM_OUT_Pos (0UL)

PCM_OUT (Bit 0)

◆ PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk

#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Msk (0x1fUL)

PDC_ACKNOWLEDGE (Bitfield-Mask: 0x1f)

◆ PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos

#define PDC_PDC_ACKNOWLEDGE_REG_PDC_ACKNOWLEDGE_Pos (0UL)

PDC_ACKNOWLEDGE (Bit 0)

◆ PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Msk

#define PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Msk (0x2UL)

PD_RAD_WKUP_CONFIG (Bitfield-Mask: 0x01)

◆ PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Pos

#define PDC_PDC_CONFIG_REG_PD_RAD_WKUP_CONFIG_Pos (1UL)

PD_RAD_WKUP_CONFIG (Bit 1)

◆ PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Msk

#define PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Msk (0x1UL)

PD_SYS_WKUP_CONFIG (Bitfield-Mask: 0x01)

◆ PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Pos

#define PDC_PDC_CONFIG_REG_PD_SYS_WKUP_CONFIG_Pos (0UL)

PD_SYS_WKUP_CONFIG (Bit 0)

◆ PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Msk

#define PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Msk (0x4UL)

TRIG_SELECT_CONFIG (Bitfield-Mask: 0x01)

◆ PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Pos

#define PDC_PDC_CONFIG_REG_TRIG_SELECT_CONFIG_Pos (2UL)

TRIG_SELECT_CONFIG (Bit 2)

◆ PDC_PDC_CTRL0_REG_EN_COM_Msk

#define PDC_PDC_CTRL0_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL0_REG_EN_COM_Pos

#define PDC_PDC_CTRL0_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL0_REG_EN_PER_Msk

#define PDC_PDC_CTRL0_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL0_REG_EN_PER_Pos

#define PDC_PDC_CTRL0_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL0_REG_EN_TMR_Msk

#define PDC_PDC_CTRL0_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL0_REG_EN_TMR_Pos

#define PDC_PDC_CTRL0_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL0_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL0_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL0_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL0_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL0_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL0_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL0_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL0_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL0_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL0_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL0_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL0_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL0_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL10_REG_EN_COM_Msk

#define PDC_PDC_CTRL10_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL10_REG_EN_COM_Pos

#define PDC_PDC_CTRL10_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL10_REG_EN_PER_Msk

#define PDC_PDC_CTRL10_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL10_REG_EN_PER_Pos

#define PDC_PDC_CTRL10_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL10_REG_EN_TMR_Msk

#define PDC_PDC_CTRL10_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL10_REG_EN_TMR_Pos

#define PDC_PDC_CTRL10_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL10_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL10_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL10_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL10_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL10_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL10_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL10_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL10_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL10_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL10_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL10_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL10_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL10_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL11_REG_EN_COM_Msk

#define PDC_PDC_CTRL11_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL11_REG_EN_COM_Pos

#define PDC_PDC_CTRL11_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL11_REG_EN_PER_Msk

#define PDC_PDC_CTRL11_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL11_REG_EN_PER_Pos

#define PDC_PDC_CTRL11_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL11_REG_EN_TMR_Msk

#define PDC_PDC_CTRL11_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL11_REG_EN_TMR_Pos

#define PDC_PDC_CTRL11_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL11_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL11_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL11_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL11_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL11_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL11_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL11_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL11_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL11_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL11_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL11_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL11_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL11_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL1_REG_EN_COM_Msk

#define PDC_PDC_CTRL1_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL1_REG_EN_COM_Pos

#define PDC_PDC_CTRL1_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL1_REG_EN_PER_Msk

#define PDC_PDC_CTRL1_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL1_REG_EN_PER_Pos

#define PDC_PDC_CTRL1_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL1_REG_EN_TMR_Msk

#define PDC_PDC_CTRL1_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL1_REG_EN_TMR_Pos

#define PDC_PDC_CTRL1_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL1_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL1_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL1_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL1_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL1_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL1_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL1_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL1_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL1_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL1_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL1_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL1_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL1_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL2_REG_EN_COM_Msk

#define PDC_PDC_CTRL2_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL2_REG_EN_COM_Pos

#define PDC_PDC_CTRL2_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL2_REG_EN_PER_Msk

#define PDC_PDC_CTRL2_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL2_REG_EN_PER_Pos

#define PDC_PDC_CTRL2_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL2_REG_EN_TMR_Msk

#define PDC_PDC_CTRL2_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL2_REG_EN_TMR_Pos

#define PDC_PDC_CTRL2_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL2_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL2_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL2_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL2_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL2_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL2_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL2_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL2_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL2_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL2_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL2_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL2_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL2_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL3_REG_EN_COM_Msk

#define PDC_PDC_CTRL3_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL3_REG_EN_COM_Pos

#define PDC_PDC_CTRL3_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL3_REG_EN_PER_Msk

#define PDC_PDC_CTRL3_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL3_REG_EN_PER_Pos

#define PDC_PDC_CTRL3_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL3_REG_EN_TMR_Msk

#define PDC_PDC_CTRL3_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL3_REG_EN_TMR_Pos

#define PDC_PDC_CTRL3_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL3_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL3_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL3_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL3_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL3_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL3_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL3_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL3_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL3_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL3_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL3_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL3_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL3_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL4_REG_EN_COM_Msk

#define PDC_PDC_CTRL4_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL4_REG_EN_COM_Pos

#define PDC_PDC_CTRL4_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL4_REG_EN_PER_Msk

#define PDC_PDC_CTRL4_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL4_REG_EN_PER_Pos

#define PDC_PDC_CTRL4_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL4_REG_EN_TMR_Msk

#define PDC_PDC_CTRL4_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL4_REG_EN_TMR_Pos

#define PDC_PDC_CTRL4_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL4_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL4_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL4_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL4_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL4_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL4_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL4_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL4_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL4_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL4_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL4_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL4_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL4_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL5_REG_EN_COM_Msk

#define PDC_PDC_CTRL5_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL5_REG_EN_COM_Pos

#define PDC_PDC_CTRL5_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL5_REG_EN_PER_Msk

#define PDC_PDC_CTRL5_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL5_REG_EN_PER_Pos

#define PDC_PDC_CTRL5_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL5_REG_EN_TMR_Msk

#define PDC_PDC_CTRL5_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL5_REG_EN_TMR_Pos

#define PDC_PDC_CTRL5_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL5_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL5_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL5_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL5_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL5_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL5_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL5_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL5_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL5_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL5_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL5_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL5_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL5_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL6_REG_EN_COM_Msk

#define PDC_PDC_CTRL6_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL6_REG_EN_COM_Pos

#define PDC_PDC_CTRL6_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL6_REG_EN_PER_Msk

#define PDC_PDC_CTRL6_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL6_REG_EN_PER_Pos

#define PDC_PDC_CTRL6_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL6_REG_EN_TMR_Msk

#define PDC_PDC_CTRL6_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL6_REG_EN_TMR_Pos

#define PDC_PDC_CTRL6_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL6_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL6_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL6_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL6_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL6_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL6_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL6_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL6_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL6_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL6_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL6_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL6_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL6_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL7_REG_EN_COM_Msk

#define PDC_PDC_CTRL7_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL7_REG_EN_COM_Pos

#define PDC_PDC_CTRL7_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL7_REG_EN_PER_Msk

#define PDC_PDC_CTRL7_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL7_REG_EN_PER_Pos

#define PDC_PDC_CTRL7_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL7_REG_EN_TMR_Msk

#define PDC_PDC_CTRL7_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL7_REG_EN_TMR_Pos

#define PDC_PDC_CTRL7_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL7_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL7_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL7_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL7_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL7_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL7_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL7_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL7_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL7_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL7_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL7_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL7_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL7_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL8_REG_EN_COM_Msk

#define PDC_PDC_CTRL8_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL8_REG_EN_COM_Pos

#define PDC_PDC_CTRL8_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL8_REG_EN_PER_Msk

#define PDC_PDC_CTRL8_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL8_REG_EN_PER_Pos

#define PDC_PDC_CTRL8_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL8_REG_EN_TMR_Msk

#define PDC_PDC_CTRL8_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL8_REG_EN_TMR_Pos

#define PDC_PDC_CTRL8_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL8_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL8_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL8_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL8_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL8_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL8_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL8_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL8_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL8_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL8_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL8_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL8_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL8_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_CTRL9_REG_EN_COM_Msk

#define PDC_PDC_CTRL9_REG_EN_COM_Msk (0x400UL)

EN_COM (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL9_REG_EN_COM_Pos

#define PDC_PDC_CTRL9_REG_EN_COM_Pos (10UL)

EN_COM (Bit 10)

◆ PDC_PDC_CTRL9_REG_EN_PER_Msk

#define PDC_PDC_CTRL9_REG_EN_PER_Msk (0x200UL)

EN_PER (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL9_REG_EN_PER_Pos

#define PDC_PDC_CTRL9_REG_EN_PER_Pos (9UL)

EN_PER (Bit 9)

◆ PDC_PDC_CTRL9_REG_EN_TMR_Msk

#define PDC_PDC_CTRL9_REG_EN_TMR_Msk (0x100UL)

EN_TMR (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL9_REG_EN_TMR_Pos

#define PDC_PDC_CTRL9_REG_EN_TMR_Pos (8UL)

EN_TMR (Bit 8)

◆ PDC_PDC_CTRL9_REG_EN_XTAL_Msk

#define PDC_PDC_CTRL9_REG_EN_XTAL_Msk (0x80UL)

EN_XTAL (Bitfield-Mask: 0x01)

◆ PDC_PDC_CTRL9_REG_EN_XTAL_Pos

#define PDC_PDC_CTRL9_REG_EN_XTAL_Pos (7UL)

EN_XTAL (Bit 7)

◆ PDC_PDC_CTRL9_REG_PDC_MASTER_Msk

#define PDC_PDC_CTRL9_REG_PDC_MASTER_Msk (0x1800UL)

PDC_MASTER (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL9_REG_PDC_MASTER_Pos

#define PDC_PDC_CTRL9_REG_PDC_MASTER_Pos (11UL)

PDC_MASTER (Bit 11)

◆ PDC_PDC_CTRL9_REG_TRIG_ID_Msk

#define PDC_PDC_CTRL9_REG_TRIG_ID_Msk (0x7cUL)

TRIG_ID (Bitfield-Mask: 0x1f)

◆ PDC_PDC_CTRL9_REG_TRIG_ID_Pos

#define PDC_PDC_CTRL9_REG_TRIG_ID_Pos (2UL)

TRIG_ID (Bit 2)

◆ PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk

#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Msk (0x3UL)

TRIG_SELECT (Bitfield-Mask: 0x03)

◆ PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos

#define PDC_PDC_CTRL9_REG_TRIG_SELECT_Pos (0UL)

TRIG_SELECT (Bit 0)

◆ PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk

#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Msk (0xfffUL)

PDC_PENDING (Bitfield-Mask: 0xfff)

◆ PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos

#define PDC_PDC_PENDING_CM33_REG_PDC_PENDING_Pos (0UL)

PDC_PENDING (Bit 0)

◆ PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk

#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Msk (0xfffUL)

PDC_PENDING (Bitfield-Mask: 0xfff)

◆ PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos

#define PDC_PDC_PENDING_CMAC_REG_PDC_PENDING_Pos (0UL)

PDC_PENDING (Bit 0)

◆ PDC_PDC_PENDING_REG_PDC_PENDING_Msk

#define PDC_PDC_PENDING_REG_PDC_PENDING_Msk (0xfffUL)

PDC_PENDING (Bitfield-Mask: 0xfff)

◆ PDC_PDC_PENDING_REG_PDC_PENDING_Pos

#define PDC_PDC_PENDING_REG_PDC_PENDING_Pos (0UL)

PDC_PENDING (Bit 0)

◆ PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk

#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Msk (0x1fUL)

PDC_SET_PENDING (Bitfield-Mask: 0x1f)

◆ PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos

#define PDC_PDC_SET_PENDING_REG_PDC_SET_PENDING_Pos (0UL)

PDC_SET_PENDING (Bit 0)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Msk (0xc00UL)

QSPIC_WR_ADR_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_ADR_TX_MD_Pos (10UL)

QSPIC_WR_ADR_TX_MD (Bit 10)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Msk (0x7c000UL)

QSPIC_WR_CS_HIGH_MIN (Bitfield-Mask: 0x1f)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_CS_HIGH_MIN_Pos (14UL)

QSPIC_WR_CS_HIGH_MIN (Bit 14)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Msk (0x3000UL)

QSPIC_WR_DAT_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_DAT_TX_MD_Pos (12UL)

QSPIC_WR_DAT_TX_MD (Bit 12)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Msk

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Msk (0xffUL)

QSPIC_WR_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Pos

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_Pos (0UL)

QSPIC_WR_INST (Bit 0)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Msk (0x300UL)

QSPIC_WR_INST_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos

#define QSPIC_QSPIC_AWRITECMD_REG_QSPIC_WR_INST_TX_MD_Pos (8UL)

QSPIC_WR_INST_TX_MD (Bit 8)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Msk (0x10000UL)

QSPIC_BRK_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_EN_Pos (16UL)

QSPIC_BRK_EN (Bit 16)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Msk (0x20000UL)

QSPIC_BRK_SZ (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_SZ_Pos (17UL)

QSPIC_BRK_SZ (Bit 17)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Msk (0xc0000UL)

QSPIC_BRK_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_TX_MD_Pos (18UL)

QSPIC_BRK_TX_MD (Bit 18)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Msk (0xffffUL)

QSPIC_BRK_WRD (Bitfield-Mask: 0xffff)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_BRK_WRD_Pos (0UL)

QSPIC_BRK_WRD (Bit 0)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Msk (0x100000UL)

QSPIC_SEC_HF_DS (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos

#define QSPIC_QSPIC_BURSTBRK_REG_QSPIC_SEC_HF_DS_Pos (20UL)

QSPIC_SEC_HF_DS (Bit 20)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Msk (0xc000000UL)

QSPIC_ADR_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_ADR_TX_MD_Pos (26UL)

QSPIC_ADR_TX_MD (Bit 26)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Msk (0xc0000000UL)

QSPIC_DMY_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_DMY_TX_MD_Pos (30UL)

QSPIC_DMY_TX_MD (Bit 30)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Msk (0xff0000UL)

QSPIC_EXT_BYTE (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_BYTE_Pos (16UL)

QSPIC_EXT_BYTE (Bit 16)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Msk (0x30000000UL)

QSPIC_EXT_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_EXT_TX_MD_Pos (28UL)

QSPIC_EXT_TX_MD (Bit 28)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Msk (0xffUL)

QSPIC_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_Pos (0UL)

QSPIC_INST (Bit 0)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Msk (0x3000000UL)

QSPIC_INST_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_TX_MD_Pos (24UL)

QSPIC_INST_TX_MD (Bit 24)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Msk (0xff00UL)

QSPIC_INST_WB (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos

#define QSPIC_QSPIC_BURSTCMDA_REG_QSPIC_INST_WB_Pos (8UL)

QSPIC_INST_WB (Bit 8)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Msk (0x7000UL)

QSPIC_CS_HIGH_MIN (Bitfield-Mask: 0x07)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_CS_HIGH_MIN_Pos (12UL)

QSPIC_CS_HIGH_MIN (Bit 12)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Msk (0x3UL)

QSPIC_DAT_RX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DAT_RX_MD_Pos (0UL)

QSPIC_DAT_RX_MD (Bit 0)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Msk (0x8000UL)

QSPIC_DMY_FORCE (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_FORCE_Pos (15UL)

QSPIC_DMY_FORCE (Bit 15)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Msk (0x30UL)

QSPIC_DMY_NUM (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_DMY_NUM_Pos (4UL)

QSPIC_DMY_NUM (Bit 4)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Msk (0x4UL)

QSPIC_EXT_BYTE_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_BYTE_EN_Pos (2UL)

QSPIC_EXT_BYTE_EN (Bit 2)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Msk (0x8UL)

QSPIC_EXT_HF_DS (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_EXT_HF_DS_Pos (3UL)

QSPIC_EXT_HF_DS (Bit 3)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Msk (0x40UL)

QSPIC_INST_MD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_INST_MD_Pos (6UL)

QSPIC_INST_MD (Bit 6)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Msk (0x300UL)

QSPIC_WRAP_LEN (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_LEN_Pos (8UL)

QSPIC_WRAP_LEN (Bit 8)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Msk (0x80UL)

QSPIC_WRAP_MD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_MD_Pos (7UL)

QSPIC_WRAP_MD (Bit 7)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Msk (0xc00UL)

QSPIC_WRAP_SIZE (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos

#define QSPIC_QSPIC_BURSTCMDB_REG_QSPIC_WRAP_SIZE_Pos (10UL)

QSPIC_WRAP_SIZE (Bit 10)

◆ QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk

#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Msk (0xffffffffUL)

QSPIC_CHCKERASE (Bitfield-Mask: 0xffffffff)

◆ QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos

#define QSPIC_QSPIC_CHCKERASE_REG_QSPIC_CHCKERASE_Pos (0UL)

QSPIC_CHCKERASE (Bit 0)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Msk (0x10UL)

QSPIC_DIS_CS (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_DIS_CS_Pos (4UL)

QSPIC_DIS_CS (Bit 4)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Msk (0x8UL)

QSPIC_EN_CS (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_EN_CS_Pos (3UL)

QSPIC_EN_CS (Bit 3)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Msk (0x2UL)

QSPIC_SET_DUAL (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_DUAL_Pos (1UL)

QSPIC_SET_DUAL (Bit 1)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Msk (0x4UL)

QSPIC_SET_QUAD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_QUAD_Pos (2UL)

QSPIC_SET_QUAD (Bit 2)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Msk (0x1UL)

QSPIC_SET_SINGLE (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos

#define QSPIC_QSPIC_CTRLBUS_REG_QSPIC_SET_SINGLE_Pos (0UL)

QSPIC_SET_SINGLE (Bit 0)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Msk (0x1UL)

QSPIC_AUTO_MD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_AUTO_MD_Pos (0UL)

QSPIC_AUTO_MD (Bit 0)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Msk (0x10000UL)

QSPIC_CLK_FREE_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_FREE_EN_Pos (16UL)

QSPIC_CLK_FREE_EN (Bit 16)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Msk (0x2UL)

QSPIC_CLK_MD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CLK_MD_Pos (1UL)

QSPIC_CLK_MD (Bit 1)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Msk (0x8000UL)

QSPIC_CS_MD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_CS_MD_Pos (15UL)

QSPIC_CS_MD (Bit 15)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Msk (0x1000UL)

QSPIC_FORCENSEQ_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_FORCENSEQ_EN_Pos (12UL)

QSPIC_FORCENSEQ_EN (Bit 12)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Msk (0x40UL)

QSPIC_HRDY_MD (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_HRDY_MD_Pos (6UL)

QSPIC_HRDY_MD (Bit 6)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Msk (0x10UL)

QSPIC_IO2_DAT (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_DAT_Pos (4UL)

QSPIC_IO2_DAT (Bit 4)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Msk (0x4UL)

QSPIC_IO2_OEN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO2_OEN_Pos (2UL)

QSPIC_IO2_OEN (Bit 2)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Msk (0x20UL)

QSPIC_IO3_DAT (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_DAT_Pos (5UL)

QSPIC_IO3_DAT (Bit 5)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Msk (0x8UL)

QSPIC_IO3_OEN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_IO3_OEN_Pos (3UL)

QSPIC_IO3_OEN (Bit 3)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Msk (0xe00UL)

QSPIC_PCLK_MD (Bitfield-Mask: 0x07)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_PCLK_MD_Pos (9UL)

QSPIC_PCLK_MD (Bit 9)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Msk (0x100UL)

QSPIC_RPIPE_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RPIPE_EN_Pos (8UL)

QSPIC_RPIPE_EN (Bit 8)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Msk (0x80UL)

QSPIC_RXD_NEG (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_RXD_NEG_Pos (7UL)

QSPIC_RXD_NEG (Bit 7)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Msk (0x4000UL)

QSPIC_SRAM_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_SRAM_EN_Pos (14UL)

QSPIC_SRAM_EN (Bit 14)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Msk (0x2000UL)

QSPIC_USE_32BA (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos

#define QSPIC_QSPIC_CTRLMODE_REG_QSPIC_USE_32BA_Pos (13UL)

QSPIC_USE_32BA (Bit 13)

◆ QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk

#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Msk (0xffffffffUL)

QSPIC_DUMMYDATA (Bitfield-Mask: 0xffffffff)

◆ QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos

#define QSPIC_QSPIC_DUMMYDATA_REG_QSPIC_DUMMYDATA_Pos (0UL)

QSPIC_DUMMYDATA (Bit 0)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Msk (0xffUL)

QSPIC_ERS_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_ERS_INST_Pos (0UL)

QSPIC_ERS_INST (Bit 0)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Msk (0xff000000UL)

QSPIC_RES_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_RES_INST_Pos (24UL)

QSPIC_RES_INST (Bit 24)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Msk (0xff0000UL)

QSPIC_SUS_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_SUS_INST_Pos (16UL)

QSPIC_SUS_INST (Bit 16)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Msk (0xff00UL)

QSPIC_WEN_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos

#define QSPIC_QSPIC_ERASECMDA_REG_QSPIC_WEN_INST_Pos (8UL)

QSPIC_WEN_INST (Bit 8)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Msk (0x300UL)

QSPIC_EAD_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_EAD_TX_MD_Pos (8UL)

QSPIC_EAD_TX_MD (Bit 8)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Msk (0x7c00UL)

QSPIC_ERS_CS_HI (Bitfield-Mask: 0x1f)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_CS_HI_Pos (10UL)

QSPIC_ERS_CS_HI (Bit 10)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Msk (0x3UL)

QSPIC_ERS_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERS_TX_MD_Pos (0UL)

QSPIC_ERS_TX_MD (Bit 0)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Msk (0xf0000UL)

QSPIC_ERSRES_HLD (Bitfield-Mask: 0x0f)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_ERSRES_HLD_Pos (16UL)

QSPIC_ERSRES_HLD (Bit 16)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Msk (0xc0UL)

QSPIC_RES_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RES_TX_MD_Pos (6UL)

QSPIC_RES_TX_MD (Bit 6)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Msk (0x3f000000UL)

QSPIC_RESSUS_DLY (Bitfield-Mask: 0x3f)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_RESSUS_DLY_Pos (24UL)

QSPIC_RESSUS_DLY (Bit 24)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Msk (0x30UL)

QSPIC_SUS_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_SUS_TX_MD_Pos (4UL)

QSPIC_SUS_TX_MD (Bit 4)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Msk (0xcUL)

QSPIC_WEN_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos

#define QSPIC_QSPIC_ERASECMDB_REG_QSPIC_WEN_TX_MD_Pos (2UL)

QSPIC_WEN_TX_MD (Bit 2)

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Msk (0x1000000UL)

QSPIC_ERASE_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERASE_EN_Pos (24UL)

QSPIC_ERASE_EN (Bit 24)

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Msk (0xfffff0UL)

QSPIC_ERS_ADDR (Bitfield-Mask: 0xfffff)

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_ADDR_Pos (4UL)

QSPIC_ERS_ADDR (Bit 4)

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Msk (0xe000000UL)

QSPIC_ERS_STATE (Bitfield-Mask: 0x07)

◆ QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos

#define QSPIC_QSPIC_ERASECTRL_REG_QSPIC_ERS_STATE_Pos (25UL)

QSPIC_ERS_STATE (Bit 25)

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Msk (0x6UL)

QSPIC_PADS_DRV (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_DRV_Pos (1UL)

QSPIC_PADS_DRV (Bit 1)

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Msk (0x18UL)

QSPIC_PADS_SLEW (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos

#define QSPIC_QSPIC_GP_REG_QSPIC_PADS_SLEW_Pos (3UL)

QSPIC_PADS_SLEW (Bit 3)

◆ QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Msk

#define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Msk (0x7UL)

QSPIC_MEMBLEN (Bitfield-Mask: 0x07)

◆ QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Pos

#define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_MEMBLEN_Pos (0UL)

QSPIC_MEMBLEN (Bit 0)

◆ QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk

#define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Msk (0x3ff0UL)

QSPIC_T_CEM_CC (Bitfield-Mask: 0x3ff)

◆ QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos

#define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_CC_Pos (4UL)

QSPIC_T_CEM_CC (Bit 4)

◆ QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk

#define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Msk (0x8UL)

QSPIC_T_CEM_EN (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos

#define QSPIC_QSPIC_MEMBLEN_REG_QSPIC_T_CEM_EN_Pos (3UL)

QSPIC_T_CEM_EN (Bit 3)

◆ QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk

#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Msk (0xffffffffUL)

QSPIC_READDATA (Bitfield-Mask: 0xffffffff)

◆ QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos

#define QSPIC_QSPIC_READDATA_REG_QSPIC_READDATA_Pos (0UL)

QSPIC_READDATA (Bit 0)

◆ QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk

#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Msk (0xffffffffUL)

QSPIC_RECVDATA (Bitfield-Mask: 0xffffffff)

◆ QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos

#define QSPIC_QSPIC_RECVDATA_REG_QSPIC_RECVDATA_Pos (0UL)

QSPIC_RECVDATA (Bit 0)

◆ QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk

#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Msk (0x1UL)

QSPIC_BUSY (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos

#define QSPIC_QSPIC_STATUS_REG_QSPIC_BUSY_Pos (0UL)

QSPIC_BUSY (Bit 0)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Msk (0x7000UL)

QSPIC_BUSY_POS (Bitfield-Mask: 0x07)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_POS_Pos (12UL)

QSPIC_BUSY_POS (Bit 12)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Msk (0x8000UL)

QSPIC_BUSY_VAL (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_BUSY_VAL_Pos (15UL)

QSPIC_BUSY_VAL (Bit 15)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Msk (0x3f0000UL)

QSPIC_RESSTS_DLY (Bitfield-Mask: 0x3f)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RESSTS_DLY_Pos (16UL)

QSPIC_RESSTS_DLY (Bit 16)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Msk (0xffUL)

QSPIC_RSTAT_INST (Bitfield-Mask: 0xff)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_INST_Pos (0UL)

QSPIC_RSTAT_INST (Bit 0)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Msk (0xc00UL)

QSPIC_RSTAT_RX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_RX_MD_Pos (10UL)

QSPIC_RSTAT_RX_MD (Bit 10)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Msk (0x300UL)

QSPIC_RSTAT_TX_MD (Bitfield-Mask: 0x03)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_RSTAT_TX_MD_Pos (8UL)

QSPIC_RSTAT_TX_MD (Bit 8)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Msk (0x400000UL)

QSPIC_STSDLY_SEL (Bitfield-Mask: 0x01)

◆ QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos

#define QSPIC_QSPIC_STATUSCMD_REG_QSPIC_STSDLY_SEL_Pos (22UL)

QSPIC_STSDLY_SEL (Bit 22)

◆ QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk

#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Msk (0xffffffffUL)

QSPIC_WRITEDATA (Bitfield-Mask: 0xffffffff)

◆ QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos

#define QSPIC_QSPIC_WRITEDATA_REG_QSPIC_WRITEDATA_Pos (0UL)

QSPIC_WRITEDATA (Bit 0)

◆ QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Msk

#define QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Msk (0x3ffUL)

QDEC_CLOCKDIV (Bitfield-Mask: 0x3ff)

◆ QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Pos

#define QUADEC_QDEC_CLOCKDIV_REG_QDEC_CLOCKDIV_Pos (0UL)

QDEC_CLOCKDIV (Bit 0)

◆ QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Msk

#define QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Msk (0x400UL)

QDEC_PRESCALER_EN (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Pos

#define QUADEC_QDEC_CLOCKDIV_REG_QDEC_PRESCALER_EN_Pos (10UL)

QDEC_PRESCALER_EN (Bit 10)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Msk

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Msk (0x1000UL)

QDEC_CHX_EVENT_MODE (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Pos

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_EVENT_MODE_Pos (12UL)

QDEC_CHX_EVENT_MODE (Bit 12)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Msk

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Msk (0xfUL)

QDEC_CHX_PORT_SEL (Bitfield-Mask: 0x0f)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Pos

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHX_PORT_SEL_Pos (0UL)

QDEC_CHX_PORT_SEL (Bit 0)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Msk

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Msk (0x2000UL)

QDEC_CHY_EVENT_MODE (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Pos

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_EVENT_MODE_Pos (13UL)

QDEC_CHY_EVENT_MODE (Bit 13)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Msk

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Msk (0xf0UL)

QDEC_CHY_PORT_SEL (Bitfield-Mask: 0x0f)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Pos

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHY_PORT_SEL_Pos (4UL)

QDEC_CHY_PORT_SEL (Bit 4)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Msk

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Msk (0x4000UL)

QDEC_CHZ_EVENT_MODE (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Pos

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_EVENT_MODE_Pos (14UL)

QDEC_CHZ_EVENT_MODE (Bit 14)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Msk

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Msk (0xf00UL)

QDEC_CHZ_PORT_SEL (Bitfield-Mask: 0x0f)

◆ QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Pos

#define QUADEC_QDEC_CTRL2_REG_QDEC_CHZ_PORT_SEL_Pos (8UL)

QDEC_CHZ_PORT_SEL (Bit 8)

◆ QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Msk

#define QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Msk (0x2UL)

QDEC_EVENT_CNT_CLR (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Pos

#define QUADEC_QDEC_CTRL_REG_QDEC_EVENT_CNT_CLR_Pos (1UL)

QDEC_EVENT_CNT_CLR (Bit 1)

◆ QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Msk

#define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Msk (0x1UL)

QDEC_IRQ_ENABLE (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Pos

#define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_ENABLE_Pos (0UL)

QDEC_IRQ_ENABLE (Bit 0)

◆ QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Msk

#define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Msk (0x4UL)

QDEC_IRQ_STATUS (Bitfield-Mask: 0x01)

◆ QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Pos

#define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_STATUS_Pos (2UL)

QDEC_IRQ_STATUS (Bit 2)

◆ QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Msk

#define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Msk (0x7f8UL)

QDEC_IRQ_THRES (Bitfield-Mask: 0xff)

◆ QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Pos

#define QUADEC_QDEC_CTRL_REG_QDEC_IRQ_THRES_Pos (3UL)

QDEC_IRQ_THRES (Bit 3)

◆ QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Msk

#define QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Msk (0xffUL)

QDEC_EVENT_CNT (Bitfield-Mask: 0xff)

◆ QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Pos

#define QUADEC_QDEC_EVENT_CNT_REG_QDEC_EVENT_CNT_Pos (0UL)

QDEC_EVENT_CNT (Bit 0)

◆ QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Msk

#define QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Msk (0xffffUL)

QDEC_X_CNT (Bitfield-Mask: 0xffff)

◆ QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Pos

#define QUADEC_QDEC_XCNT_REG_QDEC_X_CNT_Pos (0UL)

QDEC_X_CNT (Bit 0)

◆ QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Msk

#define QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Msk (0xffffUL)

QDEC_Y_CNT (Bitfield-Mask: 0xffff)

◆ QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Pos

#define QUADEC_QDEC_YCNT_REG_QDEC_Y_CNT_Pos (0UL)

QDEC_Y_CNT (Bit 0)

◆ QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Msk

#define QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Msk (0xffffUL)

QDEC_Z_CNT (Bitfield-Mask: 0xffff)

◆ QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Pos

#define QUADEC_QDEC_ZCNT_REG_QDEC_Z_CNT_Pos (0UL)

QDEC_Z_CNT (Bit 0)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Msk (0x10UL)

RTC_ALARM_DATE_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_DATE_EN_Pos (4UL)

RTC_ALARM_DATE_EN (Bit 4)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Msk (0x1UL)

RTC_ALARM_HOS_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOS_EN_Pos (0UL)

RTC_ALARM_HOS_EN (Bit 0)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Msk (0x8UL)

RTC_ALARM_HOUR_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_HOUR_EN_Pos (3UL)

RTC_ALARM_HOUR_EN (Bit 3)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Msk (0x4UL)

RTC_ALARM_MIN_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MIN_EN_Pos (2UL)

RTC_ALARM_MIN_EN (Bit 2)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Msk (0x20UL)

RTC_ALARM_MNTH_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_MNTH_EN_Pos (5UL)

RTC_ALARM_MNTH_EN (Bit 5)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Msk (0x2UL)

RTC_ALARM_SEC_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos

#define RTC_RTC_ALARM_ENABLE_REG_RTC_ALARM_SEC_EN_Pos (1UL)

RTC_ALARM_SEC_EN (Bit 1)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Msk (0x3000UL)

RTC_CAL_D_T (Bitfield-Mask: 0x03)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_T_Pos (12UL)

RTC_CAL_D_T (Bit 12)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Msk (0xf00UL)

RTC_CAL_D_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_D_U_Pos (8UL)

RTC_CAL_D_U (Bit 8)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Msk (0x80UL)

RTC_CAL_M_T (Bitfield-Mask: 0x01)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_T_Pos (7UL)

RTC_CAL_M_T (Bit 7)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Msk (0x78UL)

RTC_CAL_M_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos

#define RTC_RTC_CALENDAR_ALARM_REG_RTC_CAL_M_U_Pos (3UL)

RTC_CAL_M_U (Bit 3)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Msk (0x30000000UL)

RTC_CAL_C_T (Bitfield-Mask: 0x03)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_T_Pos (28UL)

RTC_CAL_C_T (Bit 28)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Msk (0xf000000UL)

RTC_CAL_C_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_C_U_Pos (24UL)

RTC_CAL_C_U (Bit 24)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Msk (0x80000000UL)

RTC_CAL_CH (Bitfield-Mask: 0x01)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_CH_Pos (31UL)

RTC_CAL_CH (Bit 31)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Msk (0x3000UL)

RTC_CAL_D_T (Bitfield-Mask: 0x03)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_T_Pos (12UL)

RTC_CAL_D_T (Bit 12)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Msk (0xf00UL)

RTC_CAL_D_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_D_U_Pos (8UL)

RTC_CAL_D_U (Bit 8)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Msk (0x80UL)

RTC_CAL_M_T (Bitfield-Mask: 0x01)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_T_Pos (7UL)

RTC_CAL_M_T (Bit 7)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Msk (0x78UL)

RTC_CAL_M_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_M_U_Pos (3UL)

RTC_CAL_M_U (Bit 3)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Msk (0xf00000UL)

RTC_CAL_Y_T (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_T_Pos (20UL)

RTC_CAL_Y_T (Bit 20)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk

#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Msk (0xf0000UL)

RTC_CAL_Y_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos

#define RTC_RTC_CALENDAR_REG_RTC_CAL_Y_U_Pos (16UL)

RTC_CAL_Y_U (Bit 16)

◆ RTC_RTC_CALENDAR_REG_RTC_DAY_Msk

#define RTC_RTC_CALENDAR_REG_RTC_DAY_Msk (0x7UL)

RTC_DAY (Bitfield-Mask: 0x07)

◆ RTC_RTC_CALENDAR_REG_RTC_DAY_Pos

#define RTC_RTC_CALENDAR_REG_RTC_DAY_Pos (0UL)

RTC_DAY (Bit 0)

◆ RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk

#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Msk (0x2UL)

RTC_CAL_DISABLE (Bitfield-Mask: 0x01)

◆ RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos

#define RTC_RTC_CONTROL_REG_RTC_CAL_DISABLE_Pos (1UL)

RTC_CAL_DISABLE (Bit 1)

◆ RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk

#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Msk (0x1UL)

RTC_TIME_DISABLE (Bitfield-Mask: 0x01)

◆ RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos

#define RTC_RTC_CONTROL_REG_RTC_TIME_DISABLE_Pos (0UL)

RTC_TIME_DISABLE (Bit 0)

◆ RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk

#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Msk (0x2UL)

RTC_PDC_EVENT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos

#define RTC_RTC_EVENT_CTRL_REG_RTC_PDC_EVENT_EN_Pos (1UL)

RTC_PDC_EVENT_EN (Bit 1)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Msk (0x40UL)

RTC_EVENT_ALRM (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_ALRM_Pos (6UL)

RTC_EVENT_ALRM (Bit 6)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Msk (0x10UL)

RTC_EVENT_DATE (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_DATE_Pos (4UL)

RTC_EVENT_DATE (Bit 4)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Msk (0x1UL)

RTC_EVENT_HOS (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOS_Pos (0UL)

RTC_EVENT_HOS (Bit 0)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Msk (0x8UL)

RTC_EVENT_HOUR (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_HOUR_Pos (3UL)

RTC_EVENT_HOUR (Bit 3)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Msk (0x4UL)

RTC_EVENT_MIN (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MIN_Pos (2UL)

RTC_EVENT_MIN (Bit 2)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Msk (0x20UL)

RTC_EVENT_MNTH (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_MNTH_Pos (5UL)

RTC_EVENT_MNTH (Bit 5)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Msk (0x2UL)

RTC_EVENT_SEC (Bitfield-Mask: 0x01)

◆ RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos

#define RTC_RTC_EVENT_FLAGS_REG_RTC_EVENT_SEC_Pos (1UL)

RTC_EVENT_SEC (Bit 1)

◆ RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk

#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Msk (0x1UL)

RTC_HMS (Bitfield-Mask: 0x01)

◆ RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos

#define RTC_RTC_HOUR_MODE_REG_RTC_HMS_Pos (0UL)

RTC_HMS (Bit 0)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Msk (0x40UL)

RTC_ALRM_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_ALRM_INT_DIS_Pos (6UL)

RTC_ALRM_INT_DIS (Bit 6)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Msk (0x10UL)

RTC_DATE_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_DATE_INT_DIS_Pos (4UL)

RTC_DATE_INT_DIS (Bit 4)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Msk (0x1UL)

RTC_HOS_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOS_INT_DIS_Pos (0UL)

RTC_HOS_INT_DIS (Bit 0)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Msk (0x8UL)

RTC_HOUR_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_HOUR_INT_DIS_Pos (3UL)

RTC_HOUR_INT_DIS (Bit 3)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Msk (0x4UL)

RTC_MIN_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MIN_INT_DIS_Pos (2UL)

RTC_MIN_INT_DIS (Bit 2)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Msk (0x20UL)

RTC_MNTH_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_MNTH_INT_DIS_Pos (5UL)

RTC_MNTH_INT_DIS (Bit 5)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Msk (0x2UL)

RTC_SEC_INT_DIS (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos

#define RTC_RTC_INTERRUPT_DISABLE_REG_RTC_SEC_INT_DIS_Pos (1UL)

RTC_SEC_INT_DIS (Bit 1)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Msk (0x40UL)

RTC_ALRM_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_ALRM_INT_EN_Pos (6UL)

RTC_ALRM_INT_EN (Bit 6)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Msk (0x10UL)

RTC_DATE_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_DATE_INT_EN_Pos (4UL)

RTC_DATE_INT_EN (Bit 4)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Msk (0x1UL)

RTC_HOS_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOS_INT_EN_Pos (0UL)

RTC_HOS_INT_EN (Bit 0)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Msk (0x8UL)

RTC_HOUR_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_HOUR_INT_EN_Pos (3UL)

RTC_HOUR_INT_EN (Bit 3)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Msk (0x4UL)

RTC_MIN_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MIN_INT_EN_Pos (2UL)

RTC_MIN_INT_EN (Bit 2)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Msk (0x20UL)

RTC_MNTH_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_MNTH_INT_EN_Pos (5UL)

RTC_MNTH_INT_EN (Bit 5)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Msk (0x2UL)

RTC_SEC_INT_EN (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos

#define RTC_RTC_INTERRUPT_ENABLE_REG_RTC_SEC_INT_EN_Pos (1UL)

RTC_SEC_INT_EN (Bit 1)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Msk (0x40UL)

RTC_ALRM_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_ALRM_INT_MSK_Pos (6UL)

RTC_ALRM_INT_MSK (Bit 6)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Msk (0x10UL)

RTC_DATE_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_DATE_INT_MSK_Pos (4UL)

RTC_DATE_INT_MSK (Bit 4)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Msk (0x1UL)

RTC_HOS_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOS_INT_MSK_Pos (0UL)

RTC_HOS_INT_MSK (Bit 0)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Msk (0x8UL)

RTC_HOUR_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_HOUR_INT_MSK_Pos (3UL)

RTC_HOUR_INT_MSK (Bit 3)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Msk (0x4UL)

RTC_MIN_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MIN_INT_MSK_Pos (2UL)

RTC_MIN_INT_MSK (Bit 2)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Msk (0x20UL)

RTC_MNTH_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_MNTH_INT_MSK_Pos (5UL)

RTC_MNTH_INT_MSK (Bit 5)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Msk (0x2UL)

RTC_SEC_INT_MSK (Bitfield-Mask: 0x01)

◆ RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos

#define RTC_RTC_INTERRUPT_MASK_REG_RTC_SEC_INT_MSK_Pos (1UL)

RTC_SEC_INT_MSK (Bit 1)

◆ RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk

#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Msk (0x1UL)

RTC_KEEP (Bitfield-Mask: 0x01)

◆ RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos

#define RTC_RTC_KEEP_RTC_REG_RTC_KEEP_Pos (0UL)

RTC_KEEP (Bit 0)

◆ RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk

#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Msk (0x1UL)

PDC_EVENT_CLEAR (Bitfield-Mask: 0x01)

◆ RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos

#define RTC_RTC_PDC_EVENT_CLEAR_REG_PDC_EVENT_CLEAR_Pos (0UL)

PDC_EVENT_CLEAR (Bit 0)

◆ RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk

#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Msk (0x1fffUL)

RTC_PDC_EVENT_CNT (Bitfield-Mask: 0x1fff)

◆ RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos

#define RTC_RTC_PDC_EVENT_CNT_REG_RTC_PDC_EVENT_CNT_Pos (0UL)

RTC_PDC_EVENT_CNT (Bit 0)

◆ RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk

#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Msk (0x1fffUL)

RTC_PDC_EVENT_PERIOD (Bitfield-Mask: 0x1fff)

◆ RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos

#define RTC_RTC_PDC_EVENT_PERIOD_REG_RTC_PDC_EVENT_PERIOD_Pos (0UL)

RTC_PDC_EVENT_PERIOD (Bit 0)

◆ RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk

#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Msk (0x8UL)

RTC_VALID_CAL_ALM (Bitfield-Mask: 0x01)

◆ RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos

#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_ALM_Pos (3UL)

RTC_VALID_CAL_ALM (Bit 3)

◆ RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk

#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Msk (0x2UL)

RTC_VALID_CAL (Bitfield-Mask: 0x01)

◆ RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos

#define RTC_RTC_STATUS_REG_RTC_VALID_CAL_Pos (1UL)

RTC_VALID_CAL (Bit 1)

◆ RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk

#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Msk (0x4UL)

RTC_VALID_TIME_ALM (Bitfield-Mask: 0x01)

◆ RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos

#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_ALM_Pos (2UL)

RTC_VALID_TIME_ALM (Bit 2)

◆ RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk

#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Msk (0x1UL)

RTC_VALID_TIME (Bitfield-Mask: 0x01)

◆ RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos

#define RTC_RTC_STATUS_REG_RTC_VALID_TIME_Pos (0UL)

RTC_VALID_TIME (Bit 0)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Msk (0xf0UL)

RTC_TIME_H_T (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_T_Pos (4UL)

RTC_TIME_H_T (Bit 4)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Msk (0xfUL)

RTC_TIME_H_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_H_U_Pos (0UL)

RTC_TIME_H_U (Bit 0)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Msk (0x30000000UL)

RTC_TIME_HR_T (Bitfield-Mask: 0x03)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_T_Pos (28UL)

RTC_TIME_HR_T (Bit 28)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Msk (0xf000000UL)

RTC_TIME_HR_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_HR_U_Pos (24UL)

RTC_TIME_HR_U (Bit 24)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Msk (0x700000UL)

RTC_TIME_M_T (Bitfield-Mask: 0x07)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_T_Pos (20UL)

RTC_TIME_M_T (Bit 20)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Msk (0xf0000UL)

RTC_TIME_M_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_M_U_Pos (16UL)

RTC_TIME_M_U (Bit 16)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Msk (0x40000000UL)

RTC_TIME_PM (Bitfield-Mask: 0x01)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_PM_Pos (30UL)

RTC_TIME_PM (Bit 30)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Msk (0x7000UL)

RTC_TIME_S_T (Bitfield-Mask: 0x07)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_T_Pos (12UL)

RTC_TIME_S_T (Bit 12)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Msk (0xf00UL)

RTC_TIME_S_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos

#define RTC_RTC_TIME_ALARM_REG_RTC_TIME_S_U_Pos (8UL)

RTC_TIME_S_U (Bit 8)

◆ RTC_RTC_TIME_REG_RTC_TIME_CH_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_CH_Msk (0x80000000UL)

RTC_TIME_CH (Bitfield-Mask: 0x01)

◆ RTC_RTC_TIME_REG_RTC_TIME_CH_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_CH_Pos (31UL)

RTC_TIME_CH (Bit 31)

◆ RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Msk (0xf0UL)

RTC_TIME_H_T (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_H_T_Pos (4UL)

RTC_TIME_H_T (Bit 4)

◆ RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Msk (0xfUL)

RTC_TIME_H_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_H_U_Pos (0UL)

RTC_TIME_H_U (Bit 0)

◆ RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Msk (0x30000000UL)

RTC_TIME_HR_T (Bitfield-Mask: 0x03)

◆ RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_HR_T_Pos (28UL)

RTC_TIME_HR_T (Bit 28)

◆ RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Msk (0xf000000UL)

RTC_TIME_HR_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_HR_U_Pos (24UL)

RTC_TIME_HR_U (Bit 24)

◆ RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Msk (0x700000UL)

RTC_TIME_M_T (Bitfield-Mask: 0x07)

◆ RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_M_T_Pos (20UL)

RTC_TIME_M_T (Bit 20)

◆ RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Msk (0xf0000UL)

RTC_TIME_M_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_M_U_Pos (16UL)

RTC_TIME_M_U (Bit 16)

◆ RTC_RTC_TIME_REG_RTC_TIME_PM_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_PM_Msk (0x40000000UL)

RTC_TIME_PM (Bitfield-Mask: 0x01)

◆ RTC_RTC_TIME_REG_RTC_TIME_PM_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_PM_Pos (30UL)

RTC_TIME_PM (Bit 30)

◆ RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Msk (0x7000UL)

RTC_TIME_S_T (Bitfield-Mask: 0x07)

◆ RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_S_T_Pos (12UL)

RTC_TIME_S_T (Bit 12)

◆ RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk

#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Msk (0xf00UL)

RTC_TIME_S_U (Bitfield-Mask: 0x0f)

◆ RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos

#define RTC_RTC_TIME_REG_RTC_TIME_S_U_Pos (8UL)

RTC_TIME_S_U (Bit 8)

◆ SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Msk

#define SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Msk (0x1fffffUL)

SDADC_CIC_OFFSET (Bitfield-Mask: 0x1fffff)

◆ SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Pos

#define SDADC_SDADC_AUDIO_FILT_REG_SDADC_CIC_OFFSET_Pos (0UL)

SDADC_CIC_OFFSET (Bit 0)

◆ SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk

#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Msk (0xffffffffUL)

SDADC_CLR_INT (Bitfield-Mask: 0xffffffff)

◆ SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos

#define SDADC_SDADC_CLEAR_INT_REG_SDADC_CLR_INT_Pos (0UL)

SDADC_CLR_INT (Bit 0)

◆ SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Msk (0x1000UL)

SDADC_CONT (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_CONT_Pos (12UL)

SDADC_CONT (Bit 12)

◆ SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Msk (0x40000UL)

SDADC_DMA_EN (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_DMA_EN_Pos (18UL)

SDADC_DMA_EN (Bit 18)

◆ SDADC_SDADC_CTRL_REG_SDADC_EN_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_EN_Msk (0x1UL)

SDADC_EN (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_EN_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_EN_Pos (0UL)

SDADC_EN (Bit 0)

◆ SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Msk (0x1c0UL)

SDADC_INN_SEL (Bitfield-Mask: 0x07)

◆ SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_INN_SEL_Pos (6UL)

SDADC_INN_SEL (Bit 6)

◆ SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Msk (0x3cUL)

SDADC_INP_SEL (Bitfield-Mask: 0x0f)

◆ SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_INP_SEL_Pos (2UL)

SDADC_INP_SEL (Bit 2)

◆ SDADC_SDADC_CTRL_REG_SDADC_INT_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_INT_Msk (0x10000UL)

SDADC_INT (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_INT_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_INT_Pos (16UL)

SDADC_INT (Bit 16)

◆ SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Msk (0x8000UL)

SDADC_LDO_OK (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_LDO_OK_Pos (15UL)

SDADC_LDO_OK (Bit 15)

◆ SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Msk (0x20000UL)

SDADC_MINT (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_MINT_Pos (17UL)

SDADC_MINT (Bit 17)

◆ SDADC_SDADC_CTRL_REG_SDADC_MODE_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_MODE_Msk (0x80000UL)

SDADC_MODE (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_MODE_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_MODE_Pos (19UL)

SDADC_MODE (Bit 19)

◆ SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Msk (0xc00UL)

SDADC_OSR (Bitfield-Mask: 0x03)

◆ SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_OSR_Pos (10UL)

SDADC_OSR (Bit 10)

◆ SDADC_SDADC_CTRL_REG_SDADC_SE_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_SE_Msk (0x200UL)

SDADC_SE (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_SE_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_SE_Pos (9UL)

SDADC_SE (Bit 9)

◆ SDADC_SDADC_CTRL_REG_SDADC_START_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_START_Msk (0x2UL)

SDADC_START (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_START_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_START_Pos (1UL)

SDADC_START (Bit 1)

◆ SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Msk (0x6000UL)

SDADC_VREF_SEL (Bitfield-Mask: 0x03)

◆ SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_VREF_SEL_Pos (13UL)

SDADC_VREF_SEL (Bit 13)

◆ SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Msk

#define SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Msk (0x100000UL)

SDADC_VREF_TO_PAD (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Pos

#define SDADC_SDADC_CTRL_REG_SDADC_VREF_TO_PAD_Pos (20UL)

SDADC_VREF_TO_PAD (Bit 20)

◆ SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk

#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Msk (0x3ffUL)

SDADC_GAIN_CORR (Bitfield-Mask: 0x3ff)

◆ SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos

#define SDADC_SDADC_GAIN_CORR_REG_SDADC_GAIN_CORR_Pos (0UL)

SDADC_GAIN_CORR (Bit 0)

◆ SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk

#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Msk (0x3ffUL)

SDADC_OFFS_CORR (Bitfield-Mask: 0x3ff)

◆ SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos

#define SDADC_SDADC_OFFS_CORR_REG_SDADC_OFFS_CORR_Pos (0UL)

SDADC_OFFS_CORR (Bit 0)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Msk

#define SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Msk (0x38UL)

PGA_BIAS (Bitfield-Mask: 0x07)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Pos

#define SDADC_SDADC_PGA_CTRL_REG_PGA_BIAS_Pos (3UL)

PGA_BIAS (Bit 3)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Msk

#define SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Msk (0x3UL)

PGA_EN (Bitfield-Mask: 0x03)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Pos

#define SDADC_SDADC_PGA_CTRL_REG_PGA_EN_Pos (0UL)

PGA_EN (Bit 0)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Msk

#define SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Msk (0xe00UL)

PGA_GAIN (Bitfield-Mask: 0x07)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Pos

#define SDADC_SDADC_PGA_CTRL_REG_PGA_GAIN_Pos (9UL)

PGA_GAIN (Bit 9)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Msk

#define SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Msk (0x40UL)

PGA_MUTE (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Pos

#define SDADC_SDADC_PGA_CTRL_REG_PGA_MUTE_Pos (6UL)

PGA_MUTE (Bit 6)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Msk

#define SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Msk (0x4UL)

PGA_SHORTIN (Bitfield-Mask: 0x01)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Pos

#define SDADC_SDADC_PGA_CTRL_REG_PGA_SHORTIN_Pos (2UL)

PGA_SHORTIN (Bit 2)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Msk

#define SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Msk (0x180UL)

PGA_SINGLE (Bitfield-Mask: 0x03)

◆ SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Pos

#define SDADC_SDADC_PGA_CTRL_REG_PGA_SINGLE_Pos (7UL)

PGA_SINGLE (Bit 7)

◆ SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk

#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Msk (0xffffUL)

SDADC_VAL (Bitfield-Mask: 0xffff)

◆ SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos

#define SDADC_SDADC_RESULT_REG_SDADC_VAL_Pos (0UL)

SDADC_VAL (Bit 0)

◆ SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Msk

#define SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Msk (0x7fUL)

SPI_CLK_DIV (Bitfield-Mask: 0x7f)

◆ SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Pos

#define SPI_SPI_CLOCK_REG_SPI_CLK_DIV_Pos (0UL)

SPI_CLK_DIV (Bit 0)

◆ SPI_SPI_CONFIG_REG_SPI_MODE_Msk

#define SPI_SPI_CONFIG_REG_SPI_MODE_Msk (0x3UL)

SPI_MODE (Bitfield-Mask: 0x03)

◆ SPI_SPI_CONFIG_REG_SPI_MODE_Pos

#define SPI_SPI_CONFIG_REG_SPI_MODE_Pos (0UL)

SPI_MODE (Bit 0)

◆ SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Msk

#define SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Msk (0x80UL)

SPI_SLAVE_EN (Bitfield-Mask: 0x01)

◆ SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Pos

#define SPI_SPI_CONFIG_REG_SPI_SLAVE_EN_Pos (7UL)

SPI_SLAVE_EN (Bit 7)

◆ SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Msk

#define SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Msk (0x7cUL)

SPI_WORD_LENGTH (Bitfield-Mask: 0x1f)

◆ SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Pos

#define SPI_SPI_CONFIG_REG_SPI_WORD_LENGTH_Pos (2UL)

SPI_WORD_LENGTH (Bit 2)

◆ SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Msk

#define SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Msk (0x7UL)

SPI_CS_SELECT (Bitfield-Mask: 0x07)

◆ SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Pos

#define SPI_SPI_CS_CONFIG_REG_SPI_CS_SELECT_Pos (0UL)

SPI_CS_SELECT (Bit 0)

◆ SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Msk

#define SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Msk (0x40UL)

SPI_CAPTURE_AT_NEXT_EDGE (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos

#define SPI_SPI_CTRL_REG_SPI_CAPTURE_AT_NEXT_EDGE_Pos (6UL)

SPI_CAPTURE_AT_NEXT_EDGE (Bit 6)

◆ SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Msk

#define SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Msk (0x10UL)

SPI_DMA_RX_EN (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Pos

#define SPI_SPI_CTRL_REG_SPI_DMA_RX_EN_Pos (4UL)

SPI_DMA_RX_EN (Bit 4)

◆ SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Msk

#define SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Msk (0x8UL)

SPI_DMA_TX_EN (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Pos

#define SPI_SPI_CTRL_REG_SPI_DMA_TX_EN_Pos (3UL)

SPI_DMA_TX_EN (Bit 3)

◆ SPI_SPI_CTRL_REG_SPI_EN_Msk

#define SPI_SPI_CTRL_REG_SPI_EN_Msk (0x1UL)

SPI_EN (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_EN_Pos

#define SPI_SPI_CTRL_REG_SPI_EN_Pos (0UL)

SPI_EN (Bit 0)

◆ SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Msk

#define SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Msk (0x20UL)

SPI_FIFO_RESET (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Pos

#define SPI_SPI_CTRL_REG_SPI_FIFO_RESET_Pos (5UL)

SPI_FIFO_RESET (Bit 5)

◆ SPI_SPI_CTRL_REG_SPI_RX_EN_Msk

#define SPI_SPI_CTRL_REG_SPI_RX_EN_Msk (0x4UL)

SPI_RX_EN (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_RX_EN_Pos

#define SPI_SPI_CTRL_REG_SPI_RX_EN_Pos (2UL)

SPI_RX_EN (Bit 2)

◆ SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Msk

#define SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Msk (0x80UL)

SPI_SWAP_BYTES (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Pos

#define SPI_SPI_CTRL_REG_SPI_SWAP_BYTES_Pos (7UL)

SPI_SWAP_BYTES (Bit 7)

◆ SPI_SPI_CTRL_REG_SPI_TX_EN_Msk

#define SPI_SPI_CTRL_REG_SPI_TX_EN_Msk (0x2UL)

SPI_TX_EN (Bitfield-Mask: 0x01)

◆ SPI_SPI_CTRL_REG_SPI_TX_EN_Pos

#define SPI_SPI_CTRL_REG_SPI_TX_EN_Pos (1UL)

SPI_TX_EN (Bit 1)

◆ SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Msk

#define SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Msk (0xf0UL)

SPI_RX_TL (Bitfield-Mask: 0x0f)

◆ SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Pos

#define SPI_SPI_FIFO_CONFIG_REG_SPI_RX_TL_Pos (4UL)

SPI_RX_TL (Bit 4)

◆ SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Msk

#define SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Msk (0xfUL)

SPI_TX_TL (Bitfield-Mask: 0x0f)

◆ SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Pos

#define SPI_SPI_FIFO_CONFIG_REG_SPI_TX_TL_Pos (0UL)

SPI_TX_TL (Bit 0)

◆ SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Msk

#define SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Msk (0xffffffffUL)

SPI_FIFO_READ (Bitfield-Mask: 0xffffffff)

◆ SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Pos

#define SPI_SPI_FIFO_READ_REG_SPI_FIFO_READ_Pos (0UL)

SPI_FIFO_READ (Bit 0)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Msk

#define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Msk (0x3fUL)

SPI_RX_FIFO_LEVEL (Bitfield-Mask: 0x3f)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Pos

#define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_LEVEL_Pos (0UL)

SPI_RX_FIFO_LEVEL (Bit 0)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Msk

#define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Msk (0x4000UL)

SPI_RX_FIFO_OVFL (Bitfield-Mask: 0x01)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Pos

#define SPI_SPI_FIFO_STATUS_REG_SPI_RX_FIFO_OVFL_Pos (14UL)

SPI_RX_FIFO_OVFL (Bit 14)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Msk

#define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Msk (0x1000UL)

SPI_STATUS_RX_EMPTY (Bitfield-Mask: 0x01)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Pos

#define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_RX_EMPTY_Pos (12UL)

SPI_STATUS_RX_EMPTY (Bit 12)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Msk

#define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Msk (0x2000UL)

SPI_STATUS_TX_FULL (Bitfield-Mask: 0x01)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Pos

#define SPI_SPI_FIFO_STATUS_REG_SPI_STATUS_TX_FULL_Pos (13UL)

SPI_STATUS_TX_FULL (Bit 13)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Msk

#define SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Msk (0x8000UL)

SPI_TRANSACTION_ACTIVE (Bitfield-Mask: 0x01)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Pos

#define SPI_SPI_FIFO_STATUS_REG_SPI_TRANSACTION_ACTIVE_Pos (15UL)

SPI_TRANSACTION_ACTIVE (Bit 15)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Msk

#define SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Msk (0xfc0UL)

SPI_TX_FIFO_LEVEL (Bitfield-Mask: 0x3f)

◆ SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Pos

#define SPI_SPI_FIFO_STATUS_REG_SPI_TX_FIFO_LEVEL_Pos (6UL)

SPI_TX_FIFO_LEVEL (Bit 6)

◆ SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Msk

#define SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Msk (0xffffffffUL)

SPI_FIFO_WRITE (Bitfield-Mask: 0xffffffff)

◆ SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Pos

#define SPI_SPI_FIFO_WRITE_REG_SPI_FIFO_WRITE_Pos (0UL)

SPI_FIFO_WRITE (Bit 0)

◆ SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk

#define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Msk (0x2UL)

SPI_IRQ_MASK_RX_FULL (Bitfield-Mask: 0x01)

◆ SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Pos

#define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_RX_FULL_Pos (1UL)

SPI_IRQ_MASK_RX_FULL (Bit 1)

◆ SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk

#define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Msk (0x1UL)

SPI_IRQ_MASK_TX_EMPTY (Bitfield-Mask: 0x01)

◆ SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Pos

#define SPI_SPI_IRQ_MASK_REG_SPI_IRQ_MASK_TX_EMPTY_Pos (0UL)

SPI_IRQ_MASK_TX_EMPTY (Bit 0)

◆ SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Msk

#define SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Msk (0x2UL)

SPI_STATUS_RX_FULL (Bitfield-Mask: 0x01)

◆ SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Pos

#define SPI_SPI_STATUS_REG_SPI_STATUS_RX_FULL_Pos (1UL)

SPI_STATUS_RX_FULL (Bit 1)

◆ SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk

#define SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Msk (0x1UL)

SPI_STATUS_TX_EMPTY (Bitfield-Mask: 0x01)

◆ SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Pos

#define SPI_SPI_STATUS_REG_SPI_STATUS_TX_EMPTY_Pos (0UL)

SPI_STATUS_TX_EMPTY (Bit 0)

◆ SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Msk

#define SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Msk (0xffffffffUL)

SPI_TXBUFFER_FORCE (Bitfield-Mask: 0xffffffff)

◆ SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Pos

#define SPI_SPI_TXBUFFER_FORCE_REG_SPI_TXBUFFER_FORCE_Pos (0UL)

SPI_TXBUFFER_FORCE (Bit 0)

◆ SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Msk

#define SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)

SRC_COEF10 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Pos

#define SRC1_SRC1_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)

SRC_COEF10 (Bit 0)

◆ SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Msk

#define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)

SRC_COEF0 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Pos

#define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)

SRC_COEF0 (Bit 0)

◆ SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Msk

#define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)

SRC_COEF1 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Pos

#define SRC1_SRC1_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)

SRC_COEF1 (Bit 16)

◆ SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Msk

#define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)

SRC_COEF2 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Pos

#define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)

SRC_COEF2 (Bit 0)

◆ SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Msk

#define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)

SRC_COEF3 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Pos

#define SRC1_SRC1_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)

SRC_COEF3 (Bit 16)

◆ SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Msk

#define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)

SRC_COEF4 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Pos

#define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)

SRC_COEF4 (Bit 0)

◆ SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Msk

#define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)

SRC_COEF5 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Pos

#define SRC1_SRC1_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)

SRC_COEF5 (Bit 16)

◆ SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Msk

#define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)

SRC_COEF6 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Pos

#define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)

SRC_COEF6 (Bit 0)

◆ SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Msk

#define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)

SRC_COEF7 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Pos

#define SRC1_SRC1_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)

SRC_COEF7 (Bit 16)

◆ SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Msk

#define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)

SRC_COEF8 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Pos

#define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)

SRC_COEF8 (Bit 0)

◆ SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Msk

#define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)

SRC_COEF9 (Bitfield-Mask: 0xffff)

◆ SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Pos

#define SRC1_SRC1_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)

SRC_COEF9 (Bit 16)

◆ SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)

SRC_DITHER_DISABLE (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)

SRC_DITHER_DISABLE (Bit 7)

◆ SRC1_SRC1_CTRL_REG_SRC_EN_Msk

#define SRC1_SRC1_CTRL_REG_SRC_EN_Msk (0x1UL)

SRC_EN (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_EN_Pos

#define SRC1_SRC1_CTRL_REG_SRC_EN_Pos (0UL)

SRC_EN (Bit 0)

◆ SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk

#define SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)

SRC_FIFO_DIRECTION (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos

#define SRC1_SRC1_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)

SRC_FIFO_DIRECTION (Bit 11)

◆ SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)

SRC_FIFO_ENABLE (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)

SRC_FIFO_ENABLE (Bit 10)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)

SRC_IN_AMODE (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_AMODE_Pos (1UL)

SRC_IN_AMODE (Bit 1)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)

SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)

SRC_IN_CAL_BYPASS (Bit 2)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_DS_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_DS_Msk (0x30UL)

SRC_IN_DS (Bitfield-Mask: 0x03)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_DS_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_DS_Pos (4UL)

SRC_IN_DS (Bit 4)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)

SRC_IN_DSD_MODE (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)

SRC_IN_DSD_MODE (Bit 8)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)

SRC_IN_FLOWCLR (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)

SRC_IN_FLOWCLR (Bit 24)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_OK_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_OK_Msk (0x40UL)

SRC_IN_OK (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_OK_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_OK_Pos (6UL)

SRC_IN_OK (Bit 6)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)

SRC_IN_OVFLOW (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)

SRC_IN_OVFLOW (Bit 20)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk

#define SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)

SRC_IN_UNFLOW (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos

#define SRC1_SRC1_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)

SRC_IN_UNFLOW (Bit 21)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)

SRC_OUT_AMODE (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)

SRC_OUT_AMODE (Bit 13)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)

SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)

SRC_OUT_CAL_BYPASS (Bit 14)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)

SRC_OUT_DSD_MODE (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)

SRC_OUT_DSD_MODE (Bit 9)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)

SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)

SRC_OUT_FLOWCLR (Bit 25)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL)

SRC_OUT_OK (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_OK_Pos (18UL)

SRC_OUT_OK (Bit 18)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)

SRC_OUT_OVFLOW (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)

SRC_OUT_OVFLOW (Bit 22)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)

SRC_OUT_UNFLOW (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)

SRC_OUT_UNFLOW (Bit 23)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_US_Msk

#define SRC1_SRC1_CTRL_REG_SRC_OUT_US_Msk (0x30000UL)

SRC_OUT_US (Bitfield-Mask: 0x03)

◆ SRC1_SRC1_CTRL_REG_SRC_OUT_US_Pos

#define SRC1_SRC1_CTRL_REG_SRC_OUT_US_Pos (16UL)

SRC_OUT_US (Bit 16)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk

#define SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Msk (0xc000000UL)

SRC_PDM_DI_DEL (Bitfield-Mask: 0x03)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos

#define SRC1_SRC1_CTRL_REG_SRC_PDM_DI_DEL_Pos (26UL)

SRC_PDM_DI_DEL (Bit 26)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk

#define SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Msk (0xc0000000UL)

SRC_PDM_DO_DEL (Bitfield-Mask: 0x03)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos

#define SRC1_SRC1_CTRL_REG_SRC_PDM_DO_DEL_Pos (30UL)

SRC_PDM_DO_DEL (Bit 30)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk

#define SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)

SRC_PDM_IN_INV (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos

#define SRC1_SRC1_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)

SRC_PDM_IN_INV (Bit 3)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Msk

#define SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)

SRC_PDM_MODE (Bitfield-Mask: 0x03)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Pos

#define SRC1_SRC1_CTRL_REG_SRC_PDM_MODE_Pos (28UL)

SRC_PDM_MODE (Bit 28)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk

#define SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)

SRC_PDM_OUT_INV (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos

#define SRC1_SRC1_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)

SRC_PDM_OUT_INV (Bit 12)

◆ SRC1_SRC1_CTRL_REG_SRC_RESYNC_Msk

#define SRC1_SRC1_CTRL_REG_SRC_RESYNC_Msk (0x80000UL)

SRC_RESYNC (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_CTRL_REG_SRC_RESYNC_Pos

#define SRC1_SRC1_CTRL_REG_SRC_RESYNC_Pos (19UL)

SRC_RESYNC (Bit 19)

◆ SRC1_SRC1_IN1_REG_SRC_IN_Msk

#define SRC1_SRC1_IN1_REG_SRC_IN_Msk (0xffffffffUL)

SRC_IN (Bitfield-Mask: 0xffffffff)

◆ SRC1_SRC1_IN1_REG_SRC_IN_Pos

#define SRC1_SRC1_IN1_REG_SRC_IN_Pos (0UL)

SRC_IN (Bit 0)

◆ SRC1_SRC1_IN2_REG_SRC_IN_Msk

#define SRC1_SRC1_IN2_REG_SRC_IN_Msk (0xffffffffUL)

SRC_IN (Bitfield-Mask: 0xffffffff)

◆ SRC1_SRC1_IN2_REG_SRC_IN_Pos

#define SRC1_SRC1_IN2_REG_SRC_IN_Pos (0UL)

SRC_IN (Bit 0)

◆ SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Msk

#define SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL)

SRC_IN_FS (Bitfield-Mask: 0xffffff)

◆ SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Pos

#define SRC1_SRC1_IN_FS_REG_SRC_IN_FS_Pos (0UL)

SRC_IN_FS (Bit 0)

◆ SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Msk

#define SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Msk (0x38UL)

PCM1_MUX_IN (Bitfield-Mask: 0x07)

◆ SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Pos

#define SRC1_SRC1_MUX_REG_PCM1_MUX_IN_Pos (3UL)

PCM1_MUX_IN (Bit 3)

◆ SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Msk

#define SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Msk (0x40UL)

PDM1_MUX_IN (Bitfield-Mask: 0x01)

◆ SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Pos

#define SRC1_SRC1_MUX_REG_PDM1_MUX_IN_Pos (6UL)

PDM1_MUX_IN (Bit 6)

◆ SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Msk

#define SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Msk (0x7UL)

SRC1_MUX_IN (Bitfield-Mask: 0x07)

◆ SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Pos

#define SRC1_SRC1_MUX_REG_SRC1_MUX_IN_Pos (0UL)

SRC1_MUX_IN (Bit 0)

◆ SRC1_SRC1_OUT1_REG_SRC_OUT_Msk

#define SRC1_SRC1_OUT1_REG_SRC_OUT_Msk (0xffffffffUL)

SRC_OUT (Bitfield-Mask: 0xffffffff)

◆ SRC1_SRC1_OUT1_REG_SRC_OUT_Pos

#define SRC1_SRC1_OUT1_REG_SRC_OUT_Pos (0UL)

SRC_OUT (Bit 0)

◆ SRC1_SRC1_OUT2_REG_SRC_OUT_Msk

#define SRC1_SRC1_OUT2_REG_SRC_OUT_Msk (0xffffffffUL)

SRC_OUT (Bitfield-Mask: 0xffffffff)

◆ SRC1_SRC1_OUT2_REG_SRC_OUT_Pos

#define SRC1_SRC1_OUT2_REG_SRC_OUT_Pos (0UL)

SRC_OUT (Bit 0)

◆ SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk

#define SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)

SRC_OUT_FS (Bitfield-Mask: 0xffffff)

◆ SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos

#define SRC1_SRC1_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)

SRC_OUT_FS (Bit 0)

◆ SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Msk

#define SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Msk (0xffffUL)

SRC_COEF10 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Pos

#define SRC2_SRC2_COEF0A_SET1_REG_SRC_COEF10_Pos (0UL)

SRC_COEF10 (Bit 0)

◆ SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Msk

#define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Msk (0xffffUL)

SRC_COEF0 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Pos

#define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF0_Pos (0UL)

SRC_COEF0 (Bit 0)

◆ SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Msk

#define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Msk (0xffff0000UL)

SRC_COEF1 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Pos

#define SRC2_SRC2_COEF10_SET1_REG_SRC_COEF1_Pos (16UL)

SRC_COEF1 (Bit 16)

◆ SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Msk

#define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Msk (0xffffUL)

SRC_COEF2 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Pos

#define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF2_Pos (0UL)

SRC_COEF2 (Bit 0)

◆ SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Msk

#define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Msk (0xffff0000UL)

SRC_COEF3 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Pos

#define SRC2_SRC2_COEF32_SET1_REG_SRC_COEF3_Pos (16UL)

SRC_COEF3 (Bit 16)

◆ SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Msk

#define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Msk (0xffffUL)

SRC_COEF4 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Pos

#define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF4_Pos (0UL)

SRC_COEF4 (Bit 0)

◆ SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Msk

#define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Msk (0xffff0000UL)

SRC_COEF5 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Pos

#define SRC2_SRC2_COEF54_SET1_REG_SRC_COEF5_Pos (16UL)

SRC_COEF5 (Bit 16)

◆ SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Msk

#define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Msk (0xffffUL)

SRC_COEF6 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Pos

#define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF6_Pos (0UL)

SRC_COEF6 (Bit 0)

◆ SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Msk

#define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Msk (0xffff0000UL)

SRC_COEF7 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Pos

#define SRC2_SRC2_COEF76_SET1_REG_SRC_COEF7_Pos (16UL)

SRC_COEF7 (Bit 16)

◆ SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Msk

#define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Msk (0xffffUL)

SRC_COEF8 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Pos

#define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF8_Pos (0UL)

SRC_COEF8 (Bit 0)

◆ SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Msk

#define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Msk (0xffff0000UL)

SRC_COEF9 (Bitfield-Mask: 0xffff)

◆ SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Pos

#define SRC2_SRC2_COEF98_SET1_REG_SRC_COEF9_Pos (16UL)

SRC_COEF9 (Bit 16)

◆ SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Msk (0x80UL)

SRC_DITHER_DISABLE (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_DITHER_DISABLE_Pos (7UL)

SRC_DITHER_DISABLE (Bit 7)

◆ SRC2_SRC2_CTRL_REG_SRC_EN_Msk

#define SRC2_SRC2_CTRL_REG_SRC_EN_Msk (0x1UL)

SRC_EN (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_EN_Pos

#define SRC2_SRC2_CTRL_REG_SRC_EN_Pos (0UL)

SRC_EN (Bit 0)

◆ SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Msk

#define SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Msk (0x800UL)

SRC_FIFO_DIRECTION (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Pos

#define SRC2_SRC2_CTRL_REG_SRC_FIFO_DIRECTION_Pos (11UL)

SRC_FIFO_DIRECTION (Bit 11)

◆ SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Msk (0x400UL)

SRC_FIFO_ENABLE (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_FIFO_ENABLE_Pos (10UL)

SRC_FIFO_ENABLE (Bit 10)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Msk (0x2UL)

SRC_IN_AMODE (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_AMODE_Pos (1UL)

SRC_IN_AMODE (Bit 1)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Msk (0x4UL)

SRC_IN_CAL_BYPASS (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_CAL_BYPASS_Pos (2UL)

SRC_IN_CAL_BYPASS (Bit 2)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_DS_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_DS_Msk (0x30UL)

SRC_IN_DS (Bitfield-Mask: 0x03)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_DS_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_DS_Pos (4UL)

SRC_IN_DS (Bit 4)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Msk (0x100UL)

SRC_IN_DSD_MODE (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_DSD_MODE_Pos (8UL)

SRC_IN_DSD_MODE (Bit 8)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Msk (0x1000000UL)

SRC_IN_FLOWCLR (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_FLOWCLR_Pos (24UL)

SRC_IN_FLOWCLR (Bit 24)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_OK_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_OK_Msk (0x40UL)

SRC_IN_OK (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_OK_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_OK_Pos (6UL)

SRC_IN_OK (Bit 6)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Msk (0x100000UL)

SRC_IN_OVFLOW (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_OVFLOW_Pos (20UL)

SRC_IN_OVFLOW (Bit 20)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Msk

#define SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Msk (0x200000UL)

SRC_IN_UNFLOW (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Pos

#define SRC2_SRC2_CTRL_REG_SRC_IN_UNFLOW_Pos (21UL)

SRC_IN_UNFLOW (Bit 21)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Msk (0x2000UL)

SRC_OUT_AMODE (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_AMODE_Pos (13UL)

SRC_OUT_AMODE (Bit 13)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Msk (0x4000UL)

SRC_OUT_CAL_BYPASS (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_CAL_BYPASS_Pos (14UL)

SRC_OUT_CAL_BYPASS (Bit 14)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Msk (0x200UL)

SRC_OUT_DSD_MODE (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_DSD_MODE_Pos (9UL)

SRC_OUT_DSD_MODE (Bit 9)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Msk (0x2000000UL)

SRC_OUT_FLOWCLR (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_FLOWCLR_Pos (25UL)

SRC_OUT_FLOWCLR (Bit 25)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Msk (0x40000UL)

SRC_OUT_OK (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_OK_Pos (18UL)

SRC_OUT_OK (Bit 18)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Msk (0x400000UL)

SRC_OUT_OVFLOW (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_OVFLOW_Pos (22UL)

SRC_OUT_OVFLOW (Bit 22)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Msk (0x800000UL)

SRC_OUT_UNFLOW (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_UNFLOW_Pos (23UL)

SRC_OUT_UNFLOW (Bit 23)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_US_Msk

#define SRC2_SRC2_CTRL_REG_SRC_OUT_US_Msk (0x30000UL)

SRC_OUT_US (Bitfield-Mask: 0x03)

◆ SRC2_SRC2_CTRL_REG_SRC_OUT_US_Pos

#define SRC2_SRC2_CTRL_REG_SRC_OUT_US_Pos (16UL)

SRC_OUT_US (Bit 16)

◆ SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Msk

#define SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Msk (0x8UL)

SRC_PDM_IN_INV (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Pos

#define SRC2_SRC2_CTRL_REG_SRC_PDM_IN_INV_Pos (3UL)

SRC_PDM_IN_INV (Bit 3)

◆ SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Msk

#define SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Msk (0x30000000UL)

SRC_PDM_MODE (Bitfield-Mask: 0x03)

◆ SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Pos

#define SRC2_SRC2_CTRL_REG_SRC_PDM_MODE_Pos (28UL)

SRC_PDM_MODE (Bit 28)

◆ SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Msk

#define SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Msk (0x1000UL)

SRC_PDM_OUT_INV (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Pos

#define SRC2_SRC2_CTRL_REG_SRC_PDM_OUT_INV_Pos (12UL)

SRC_PDM_OUT_INV (Bit 12)

◆ SRC2_SRC2_CTRL_REG_SRC_RESYNC_Msk

#define SRC2_SRC2_CTRL_REG_SRC_RESYNC_Msk (0x80000UL)

SRC_RESYNC (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_CTRL_REG_SRC_RESYNC_Pos

#define SRC2_SRC2_CTRL_REG_SRC_RESYNC_Pos (19UL)

SRC_RESYNC (Bit 19)

◆ SRC2_SRC2_IN1_REG_SRC_IN_Msk

#define SRC2_SRC2_IN1_REG_SRC_IN_Msk (0xffffffffUL)

SRC_IN (Bitfield-Mask: 0xffffffff)

◆ SRC2_SRC2_IN1_REG_SRC_IN_Pos

#define SRC2_SRC2_IN1_REG_SRC_IN_Pos (0UL)

SRC_IN (Bit 0)

◆ SRC2_SRC2_IN2_REG_SRC_IN_Msk

#define SRC2_SRC2_IN2_REG_SRC_IN_Msk (0xffffffffUL)

SRC_IN (Bitfield-Mask: 0xffffffff)

◆ SRC2_SRC2_IN2_REG_SRC_IN_Pos

#define SRC2_SRC2_IN2_REG_SRC_IN_Pos (0UL)

SRC_IN (Bit 0)

◆ SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Msk

#define SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Msk (0xffffffUL)

SRC_IN_FS (Bitfield-Mask: 0xffffff)

◆ SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Pos

#define SRC2_SRC2_IN_FS_REG_SRC_IN_FS_Pos (0UL)

SRC_IN_FS (Bit 0)

◆ SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Msk

#define SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Msk (0x40UL)

PDM1_MUX_IN (Bitfield-Mask: 0x01)

◆ SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Pos

#define SRC2_SRC2_MUX_REG_PDM1_MUX_IN_Pos (6UL)

PDM1_MUX_IN (Bit 6)

◆ SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Msk

#define SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Msk (0x38UL)

PDM_MUX_OUT (Bitfield-Mask: 0x07)

◆ SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Pos

#define SRC2_SRC2_MUX_REG_PDM_MUX_OUT_Pos (3UL)

PDM_MUX_OUT (Bit 3)

◆ SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Msk

#define SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Msk (0x7UL)

SRC2_MUX_IN (Bitfield-Mask: 0x07)

◆ SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Pos

#define SRC2_SRC2_MUX_REG_SRC2_MUX_IN_Pos (0UL)

SRC2_MUX_IN (Bit 0)

◆ SRC2_SRC2_OUT1_REG_SRC_OUT_Msk

#define SRC2_SRC2_OUT1_REG_SRC_OUT_Msk (0xffffffffUL)

SRC_OUT (Bitfield-Mask: 0xffffffff)

◆ SRC2_SRC2_OUT1_REG_SRC_OUT_Pos

#define SRC2_SRC2_OUT1_REG_SRC_OUT_Pos (0UL)

SRC_OUT (Bit 0)

◆ SRC2_SRC2_OUT2_REG_SRC_OUT_Msk

#define SRC2_SRC2_OUT2_REG_SRC_OUT_Msk (0xffffffffUL)

SRC_OUT (Bitfield-Mask: 0xffffffff)

◆ SRC2_SRC2_OUT2_REG_SRC_OUT_Pos

#define SRC2_SRC2_OUT2_REG_SRC_OUT_Pos (0UL)

SRC_OUT (Bit 0)

◆ SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Msk

#define SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Msk (0xffffffUL)

SRC_OUT_FS (Bitfield-Mask: 0xffffff)

◆ SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Pos

#define SRC2_SRC2_OUT_FS_REG_SRC_OUT_FS_Pos (0UL)

SRC_OUT_FS (Bit 0)

◆ SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk

#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Msk (0x1UL)

NMI_RST (Bitfield-Mask: 0x01)

◆ SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos

#define SYS_WDOG_WATCHDOG_CTRL_REG_NMI_RST_Pos (0UL)

NMI_RST (Bit 0)

◆ SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk

#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Msk (0x4UL)

WDOG_FREEZE_EN (Bitfield-Mask: 0x01)

◆ SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos

#define SYS_WDOG_WATCHDOG_CTRL_REG_WDOG_FREEZE_EN_Pos (2UL)

WDOG_FREEZE_EN (Bit 2)

◆ SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk

#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Msk (0x8UL)

WRITE_BUSY (Bitfield-Mask: 0x01)

◆ SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos

#define SYS_WDOG_WATCHDOG_CTRL_REG_WRITE_BUSY_Pos (3UL)

WRITE_BUSY (Bit 3)

◆ SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk

#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Msk (0x1fffUL)

WDOG_VAL (Bitfield-Mask: 0x1fff)

◆ SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk

#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Msk (0x2000UL)

WDOG_VAL_NEG (Bitfield-Mask: 0x01)

◆ SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos

#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_NEG_Pos (13UL)

WDOG_VAL_NEG (Bit 13)

◆ SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos

#define SYS_WDOG_WATCHDOG_REG_WDOG_VAL_Pos (0UL)

WDOG_VAL (Bit 0)

◆ SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk

#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Msk (0xffffc000UL)

WDOG_WEN (Bitfield-Mask: 0x3ffff)

◆ SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos

#define SYS_WDOG_WATCHDOG_REG_WDOG_WEN_Pos (14UL)

WDOG_WEN (Bit 14)

◆ SYSB_BRIDGE_REG_BRIDGE_BYPASS_Msk

#define SYSB_BRIDGE_REG_BRIDGE_BYPASS_Msk (0x1UL)

BRIDGE_BYPASS (Bitfield-Mask: 0x01)

◆ SYSB_BRIDGE_REG_BRIDGE_BYPASS_Pos

#define SYSB_BRIDGE_REG_BRIDGE_BYPASS_Pos (0UL)

BRIDGE_BYPASS (Bit 0)

◆ SYSB_BRIDGE_REG_SYNC_BYPASS_Msk

#define SYSB_BRIDGE_REG_SYNC_BYPASS_Msk (0x2UL)

SYNC_BYPASS (Bitfield-Mask: 0x01)

◆ SYSB_BRIDGE_REG_SYNC_BYPASS_Pos

#define SYSB_BRIDGE_REG_SYNC_BYPASS_Pos (1UL)

SYNC_BYPASS (Bit 1)

◆ SYSB_FLASH_ARB_REG_ENABLE_SEQ_Msk

#define SYSB_FLASH_ARB_REG_ENABLE_SEQ_Msk (0x1UL)

ENABLE_SEQ (Bitfield-Mask: 0x01)

◆ SYSB_FLASH_ARB_REG_ENABLE_SEQ_Pos

#define SYSB_FLASH_ARB_REG_ENABLE_SEQ_Pos (0UL)

ENABLE_SEQ (Bit 0)

◆ SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Msk

#define SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Msk (0x3UL)

AHB_CMAC_PRIO (Bitfield-Mask: 0x03)

◆ SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Pos

#define SYSB_QSPI_ARB_REG_AHB_CMAC_PRIO_Pos (0UL)

AHB_CMAC_PRIO (Bit 0)

◆ SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Msk

#define SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Msk (0x30UL)

AHB_CPUC_PRIO (Bitfield-Mask: 0x03)

◆ SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Pos

#define SYSB_QSPI_ARB_REG_AHB_CPUC_PRIO_Pos (4UL)

AHB_CPUC_PRIO (Bit 4)

◆ SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Msk

#define SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Msk (0xcUL)

AHB_CPUS_PRIO (Bitfield-Mask: 0x03)

◆ SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Pos

#define SYSB_QSPI_ARB_REG_AHB_CPUS_PRIO_Pos (2UL)

AHB_CPUS_PRIO (Bit 2)

◆ SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Msk

#define SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Msk (0xc0UL)

AHB_DMA_PRIO (Bitfield-Mask: 0x03)

◆ SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Pos

#define SYSB_QSPI_ARB_REG_AHB_DMA_PRIO_Pos (6UL)

AHB_DMA_PRIO (Bit 6)

◆ TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk

#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)

◆ TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos

#define TIMER2_TIMER2_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

TIM_CAPTURE_GPIO1 (Bit 0)

◆ TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk

#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)

◆ TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos

#define TIMER2_TIMER2_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

TIM_CAPTURE_GPIO2 (Bit 0)

◆ TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk

#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos

#define TIMER2_TIMER2_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

TIM_CLEAR_IRQ (Bit 0)

◆ TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

TIM_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_CLK_EN_Pos (8UL)

TIM_CLK_EN (Bit 8)

◆ TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

TIM_COUNT_DOWN_EN (Bit 2)

◆ TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Msk (0x1UL)

TIM_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_EN_Pos (0UL)

TIM_EN (Bit 0)

◆ TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

TIM_FREE_RUN_MODE_EN (Bit 6)

◆ TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

TIM_IN1_EVENT_FALL_EN (Bit 3)

◆ TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

TIM_IN2_EVENT_FALL_EN (Bit 4)

◆ TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

TIM_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

TIM_IRQ_EN (Bit 5)

◆ TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)

TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)

TIM_ONESHOT_MODE_EN (Bit 1)

◆ TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk

#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos

#define TIMER2_TIMER2_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

TIM_SYS_CLK_EN (Bit 7)

◆ TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk

#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)

◆ TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos

#define TIMER2_TIMER2_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

TIM_GPIO1_CONF (Bit 0)

◆ TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk

#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)

◆ TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos

#define TIMER2_TIMER2_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

TIM_GPIO2_CONF (Bit 0)

◆ TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk

#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)

◆ TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos

#define TIMER2_TIMER2_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

TIM_PRESCALER_VAL (Bit 0)

◆ TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Msk

#define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

TIM_PWM_DC (Bitfield-Mask: 0xffff)

◆ TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Pos

#define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

TIM_PWM_DC (Bit 16)

◆ TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Msk

#define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

TIM_PWM_FREQ (Bitfield-Mask: 0xffff)

◆ TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Pos

#define TIMER2_TIMER2_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

TIM_PWM_FREQ (Bit 0)

◆ TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Msk

#define TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

TIM_PRESCALER (Bitfield-Mask: 0x1f)

◆ TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Pos

#define TIMER2_TIMER2_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

TIM_PRESCALER (Bit 24)

◆ TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Msk

#define TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

TIM_RELOAD (Bitfield-Mask: 0xffffff)

◆ TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Pos

#define TIMER2_TIMER2_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

TIM_RELOAD (Bit 0)

◆ TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk

#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)

TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff)

◆ TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos

#define TIMER2_TIMER2_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)

TIM_SHOTWIDTH (Bit 0)

◆ TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

TIM_IN1_STATE (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

TIM_IN1_STATE (Bit 0)

◆ TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

TIM_IN2_STATE (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

TIM_IN2_STATE (Bit 1)

◆ TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

TIM_IRQ_STATUS (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

TIM_IRQ_STATUS (Bit 8)

◆ TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)

◆ TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

TIM_ONESHOT_PHASE (Bit 2)

◆ TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

TIM_PWM_BUSY (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

TIM_PWM_BUSY (Bit 10)

◆ TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

TIM_SWITCHED_TO_DIVN_CLK (Bit 11)

◆ TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Msk

#define TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

TIM_TIMER_BUSY (Bitfield-Mask: 0x01)

◆ TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Pos

#define TIMER2_TIMER2_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

TIM_TIMER_BUSY (Bit 9)

◆ TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk

#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)

◆ TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos

#define TIMER2_TIMER2_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

TIM_TIMER_VALUE (Bit 0)

◆ TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk

#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)

◆ TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos

#define TIMER3_TIMER3_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

TIM_CAPTURE_GPIO1 (Bit 0)

◆ TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk

#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)

◆ TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos

#define TIMER3_TIMER3_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

TIM_CAPTURE_GPIO2 (Bit 0)

◆ TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk

#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos

#define TIMER3_TIMER3_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

TIM_CLEAR_IRQ (Bit 0)

◆ TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

TIM_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_CLK_EN_Pos (8UL)

TIM_CLK_EN (Bit 8)

◆ TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

TIM_COUNT_DOWN_EN (Bit 2)

◆ TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Msk (0x1UL)

TIM_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_EN_Pos (0UL)

TIM_EN (Bit 0)

◆ TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

TIM_FREE_RUN_MODE_EN (Bit 6)

◆ TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

TIM_IN1_EVENT_FALL_EN (Bit 3)

◆ TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

TIM_IN2_EVENT_FALL_EN (Bit 4)

◆ TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

TIM_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

TIM_IRQ_EN (Bit 5)

◆ TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk

#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos

#define TIMER3_TIMER3_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

TIM_SYS_CLK_EN (Bit 7)

◆ TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk

#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)

◆ TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos

#define TIMER3_TIMER3_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

TIM_GPIO1_CONF (Bit 0)

◆ TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk

#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)

◆ TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos

#define TIMER3_TIMER3_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

TIM_GPIO2_CONF (Bit 0)

◆ TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk

#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)

◆ TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos

#define TIMER3_TIMER3_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

TIM_PRESCALER_VAL (Bit 0)

◆ TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Msk

#define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

TIM_PWM_DC (Bitfield-Mask: 0xffff)

◆ TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Pos

#define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

TIM_PWM_DC (Bit 16)

◆ TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Msk

#define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

TIM_PWM_FREQ (Bitfield-Mask: 0xffff)

◆ TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Pos

#define TIMER3_TIMER3_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

TIM_PWM_FREQ (Bit 0)

◆ TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Msk

#define TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

TIM_PRESCALER (Bitfield-Mask: 0x1f)

◆ TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Pos

#define TIMER3_TIMER3_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

TIM_PRESCALER (Bit 24)

◆ TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Msk

#define TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

TIM_RELOAD (Bitfield-Mask: 0xffffff)

◆ TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Pos

#define TIMER3_TIMER3_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

TIM_RELOAD (Bit 0)

◆ TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

TIM_IN1_STATE (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

TIM_IN1_STATE (Bit 0)

◆ TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

TIM_IN2_STATE (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

TIM_IN2_STATE (Bit 1)

◆ TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

TIM_IRQ_STATUS (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

TIM_IRQ_STATUS (Bit 8)

◆ TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)

◆ TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

TIM_ONESHOT_PHASE (Bit 2)

◆ TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

TIM_PWM_BUSY (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

TIM_PWM_BUSY (Bit 10)

◆ TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

TIM_SWITCHED_TO_DIVN_CLK (Bit 11)

◆ TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Msk

#define TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

TIM_TIMER_BUSY (Bitfield-Mask: 0x01)

◆ TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Pos

#define TIMER3_TIMER3_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

TIM_TIMER_BUSY (Bit 9)

◆ TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk

#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)

◆ TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos

#define TIMER3_TIMER3_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

TIM_TIMER_VALUE (Bit 0)

◆ TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk

#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)

◆ TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos

#define TIMER4_TIMER4_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

TIM_CAPTURE_GPIO1 (Bit 0)

◆ TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk

#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)

◆ TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos

#define TIMER4_TIMER4_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

TIM_CAPTURE_GPIO2 (Bit 0)

◆ TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk

#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos

#define TIMER4_TIMER4_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

TIM_CLEAR_IRQ (Bit 0)

◆ TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

TIM_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_CLK_EN_Pos (8UL)

TIM_CLK_EN (Bit 8)

◆ TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

TIM_COUNT_DOWN_EN (Bit 2)

◆ TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Msk (0x1UL)

TIM_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_EN_Pos (0UL)

TIM_EN (Bit 0)

◆ TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

TIM_FREE_RUN_MODE_EN (Bit 6)

◆ TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

TIM_IN1_EVENT_FALL_EN (Bit 3)

◆ TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

TIM_IN2_EVENT_FALL_EN (Bit 4)

◆ TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

TIM_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

TIM_IRQ_EN (Bit 5)

◆ TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk

#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos

#define TIMER4_TIMER4_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

TIM_SYS_CLK_EN (Bit 7)

◆ TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk

#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)

◆ TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos

#define TIMER4_TIMER4_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

TIM_GPIO1_CONF (Bit 0)

◆ TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk

#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)

◆ TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos

#define TIMER4_TIMER4_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

TIM_GPIO2_CONF (Bit 0)

◆ TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk

#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)

◆ TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos

#define TIMER4_TIMER4_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

TIM_PRESCALER_VAL (Bit 0)

◆ TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Msk

#define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

TIM_PWM_DC (Bitfield-Mask: 0xffff)

◆ TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Pos

#define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

TIM_PWM_DC (Bit 16)

◆ TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Msk

#define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

TIM_PWM_FREQ (Bitfield-Mask: 0xffff)

◆ TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Pos

#define TIMER4_TIMER4_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

TIM_PWM_FREQ (Bit 0)

◆ TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Msk

#define TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

TIM_PRESCALER (Bitfield-Mask: 0x1f)

◆ TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Pos

#define TIMER4_TIMER4_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

TIM_PRESCALER (Bit 24)

◆ TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Msk

#define TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

TIM_RELOAD (Bitfield-Mask: 0xffffff)

◆ TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Pos

#define TIMER4_TIMER4_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

TIM_RELOAD (Bit 0)

◆ TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

TIM_IN1_STATE (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

TIM_IN1_STATE (Bit 0)

◆ TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

TIM_IN2_STATE (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

TIM_IN2_STATE (Bit 1)

◆ TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

TIM_IRQ_STATUS (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

TIM_IRQ_STATUS (Bit 8)

◆ TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)

◆ TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

TIM_ONESHOT_PHASE (Bit 2)

◆ TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

TIM_PWM_BUSY (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

TIM_PWM_BUSY (Bit 10)

◆ TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

TIM_SWITCHED_TO_DIVN_CLK (Bit 11)

◆ TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Msk

#define TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

TIM_TIMER_BUSY (Bitfield-Mask: 0x01)

◆ TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Pos

#define TIMER4_TIMER4_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

TIM_TIMER_BUSY (Bit 9)

◆ TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk

#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)

◆ TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos

#define TIMER4_TIMER4_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

TIM_TIMER_VALUE (Bit 0)

◆ TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk

#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Msk (0xffffffUL)

TIM_CAPTURE_GPIO1 (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos

#define TIMER_TIMER_CAPTURE_GPIO1_REG_TIM_CAPTURE_GPIO1_Pos (0UL)

TIM_CAPTURE_GPIO1 (Bit 0)

◆ TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk

#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Msk (0xffffffUL)

TIM_CAPTURE_GPIO2 (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos

#define TIMER_TIMER_CAPTURE_GPIO2_REG_TIM_CAPTURE_GPIO2_Pos (0UL)

TIM_CAPTURE_GPIO2 (Bit 0)

◆ TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk

#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Msk (0xffffffUL)

TIM_CAPTURE_GPIO3 (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos

#define TIMER_TIMER_CAPTURE_GPIO3_REG_TIM_CAPTURE_GPIO3_Pos (0UL)

TIM_CAPTURE_GPIO3 (Bit 0)

◆ TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk

#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Msk (0xffffffUL)

TIM_CAPTURE_GPIO4 (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos

#define TIMER_TIMER_CAPTURE_GPIO4_REG_TIM_CAPTURE_GPIO4_Pos (0UL)

TIM_CAPTURE_GPIO4 (Bit 0)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Msk (0x1UL)

TIM_CLEAR_GPIO1_EVENT (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO1_EVENT_Pos (0UL)

TIM_CLEAR_GPIO1_EVENT (Bit 0)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Msk (0x2UL)

TIM_CLEAR_GPIO2_EVENT (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO2_EVENT_Pos (1UL)

TIM_CLEAR_GPIO2_EVENT (Bit 1)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Msk (0x4UL)

TIM_CLEAR_GPIO3_EVENT (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO3_EVENT_Pos (2UL)

TIM_CLEAR_GPIO3_EVENT (Bit 2)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Msk (0x8UL)

TIM_CLEAR_GPIO4_EVENT (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos

#define TIMER_TIMER_CLEAR_GPIO_EVENT_REG_TIM_CLEAR_GPIO4_EVENT_Pos (3UL)

TIM_CLEAR_GPIO4_EVENT (Bit 3)

◆ TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk

#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Msk (0x1UL)

TIM_CLEAR_IRQ (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos

#define TIMER_TIMER_CLEAR_IRQ_REG_TIM_CLEAR_IRQ_Pos (0UL)

TIM_CLEAR_IRQ (Bit 0)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Msk (0x800UL)

TIM_CAP_GPIO1_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO1_IRQ_EN_Pos (11UL)

TIM_CAP_GPIO1_IRQ_EN (Bit 11)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Msk (0x1000UL)

TIM_CAP_GPIO2_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO2_IRQ_EN_Pos (12UL)

TIM_CAP_GPIO2_IRQ_EN (Bit 12)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Msk (0x2000UL)

TIM_CAP_GPIO3_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO3_IRQ_EN_Pos (13UL)

TIM_CAP_GPIO3_IRQ_EN (Bit 13)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Msk (0x4000UL)

TIM_CAP_GPIO4_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_CAP_GPIO4_IRQ_EN_Pos (14UL)

TIM_CAP_GPIO4_IRQ_EN (Bit 14)

◆ TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Msk (0x100UL)

TIM_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_CLK_EN_Pos (8UL)

TIM_CLK_EN (Bit 8)

◆ TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Msk (0x4UL)

TIM_COUNT_DOWN_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_COUNT_DOWN_EN_Pos (2UL)

TIM_COUNT_DOWN_EN (Bit 2)

◆ TIMER_TIMER_CTRL_REG_TIM_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_EN_Msk (0x1UL)

TIM_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_EN_Pos (0UL)

TIM_EN (Bit 0)

◆ TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Msk (0x40UL)

TIM_FREE_RUN_MODE_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_FREE_RUN_MODE_EN_Pos (6UL)

TIM_FREE_RUN_MODE_EN (Bit 6)

◆ TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Msk (0x8UL)

TIM_IN1_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_IN1_EVENT_FALL_EN_Pos (3UL)

TIM_IN1_EVENT_FALL_EN (Bit 3)

◆ TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Msk (0x10UL)

TIM_IN2_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_IN2_EVENT_FALL_EN_Pos (4UL)

TIM_IN2_EVENT_FALL_EN (Bit 4)

◆ TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Msk (0x200UL)

TIM_IN3_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_IN3_EVENT_FALL_EN_Pos (9UL)

TIM_IN3_EVENT_FALL_EN (Bit 9)

◆ TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Msk (0x400UL)

TIM_IN4_EVENT_FALL_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_IN4_EVENT_FALL_EN_Pos (10UL)

TIM_IN4_EVENT_FALL_EN (Bit 10)

◆ TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Msk (0x20UL)

TIM_IRQ_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_IRQ_EN_Pos (5UL)

TIM_IRQ_EN (Bit 5)

◆ TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Msk (0x2UL)

TIM_ONESHOT_MODE_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_ONESHOT_MODE_EN_Pos (1UL)

TIM_ONESHOT_MODE_EN (Bit 1)

◆ TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk

#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Msk (0x80UL)

TIM_SYS_CLK_EN (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos

#define TIMER_TIMER_CTRL_REG_TIM_SYS_CLK_EN_Pos (7UL)

TIM_SYS_CLK_EN (Bit 7)

◆ TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk

#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Msk (0x3fUL)

TIM_GPIO1_CONF (Bitfield-Mask: 0x3f)

◆ TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos

#define TIMER_TIMER_GPIO1_CONF_REG_TIM_GPIO1_CONF_Pos (0UL)

TIM_GPIO1_CONF (Bit 0)

◆ TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk

#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Msk (0x3fUL)

TIM_GPIO2_CONF (Bitfield-Mask: 0x3f)

◆ TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos

#define TIMER_TIMER_GPIO2_CONF_REG_TIM_GPIO2_CONF_Pos (0UL)

TIM_GPIO2_CONF (Bit 0)

◆ TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk

#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Msk (0x3fUL)

TIM_GPIO3_CONF (Bitfield-Mask: 0x3f)

◆ TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos

#define TIMER_TIMER_GPIO3_CONF_REG_TIM_GPIO3_CONF_Pos (0UL)

TIM_GPIO3_CONF (Bit 0)

◆ TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk

#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Msk (0x3fUL)

TIM_GPIO4_CONF (Bitfield-Mask: 0x3f)

◆ TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos

#define TIMER_TIMER_GPIO4_CONF_REG_TIM_GPIO4_CONF_Pos (0UL)

TIM_GPIO4_CONF (Bit 0)

◆ TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk

#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Msk (0x1fUL)

TIM_PRESCALER_VAL (Bitfield-Mask: 0x1f)

◆ TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos

#define TIMER_TIMER_PRESCALER_VAL_REG_TIM_PRESCALER_VAL_Pos (0UL)

TIM_PRESCALER_VAL (Bit 0)

◆ TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk

#define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Msk (0xffff0000UL)

TIM_PWM_DC (Bitfield-Mask: 0xffff)

◆ TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Pos

#define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_DC_Pos (16UL)

TIM_PWM_DC (Bit 16)

◆ TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk

#define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Msk (0xffffUL)

TIM_PWM_FREQ (Bitfield-Mask: 0xffff)

◆ TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Pos

#define TIMER_TIMER_PWM_CTRL_REG_TIM_PWM_FREQ_Pos (0UL)

TIM_PWM_FREQ (Bit 0)

◆ TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Msk

#define TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Msk (0x1f000000UL)

TIM_PRESCALER (Bitfield-Mask: 0x1f)

◆ TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Pos

#define TIMER_TIMER_SETTINGS_REG_TIM_PRESCALER_Pos (24UL)

TIM_PRESCALER (Bit 24)

◆ TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Msk

#define TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Msk (0xffffffUL)

TIM_RELOAD (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Pos

#define TIMER_TIMER_SETTINGS_REG_TIM_RELOAD_Pos (0UL)

TIM_RELOAD (Bit 0)

◆ TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk

#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Msk (0xffffffUL)

TIM_SHOTWIDTH (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos

#define TIMER_TIMER_SHOTWIDTH_REG_TIM_SHOTWIDTH_Pos (0UL)

TIM_SHOTWIDTH (Bit 0)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk

#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Msk (0x10UL)

TIM_GPIO1_EVENT_PENDING (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos

#define TIMER_TIMER_STATUS_REG_TIM_GPIO1_EVENT_PENDING_Pos (4UL)

TIM_GPIO1_EVENT_PENDING (Bit 4)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk

#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Msk (0x20UL)

TIM_GPIO2_EVENT_PENDING (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos

#define TIMER_TIMER_STATUS_REG_TIM_GPIO2_EVENT_PENDING_Pos (5UL)

TIM_GPIO2_EVENT_PENDING (Bit 5)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk

#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Msk (0x40UL)

TIM_GPIO3_EVENT_PENDING (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos

#define TIMER_TIMER_STATUS_REG_TIM_GPIO3_EVENT_PENDING_Pos (6UL)

TIM_GPIO3_EVENT_PENDING (Bit 6)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk

#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Msk (0x80UL)

TIM_GPIO4_EVENT_PENDING (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos

#define TIMER_TIMER_STATUS_REG_TIM_GPIO4_EVENT_PENDING_Pos (7UL)

TIM_GPIO4_EVENT_PENDING (Bit 7)

◆ TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk

#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Msk (0x1UL)

TIM_IN1_STATE (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos

#define TIMER_TIMER_STATUS_REG_TIM_IN1_STATE_Pos (0UL)

TIM_IN1_STATE (Bit 0)

◆ TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk

#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Msk (0x2UL)

TIM_IN2_STATE (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos

#define TIMER_TIMER_STATUS_REG_TIM_IN2_STATE_Pos (1UL)

TIM_IN2_STATE (Bit 1)

◆ TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Msk

#define TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Msk (0x1000UL)

TIM_IN3_STATE (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Pos

#define TIMER_TIMER_STATUS_REG_TIM_IN3_STATE_Pos (12UL)

TIM_IN3_STATE (Bit 12)

◆ TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Msk

#define TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Msk (0x2000UL)

TIM_IN4_STATE (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Pos

#define TIMER_TIMER_STATUS_REG_TIM_IN4_STATE_Pos (13UL)

TIM_IN4_STATE (Bit 13)

◆ TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Msk

#define TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Msk (0x100UL)

TIM_IRQ_STATUS (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Pos

#define TIMER_TIMER_STATUS_REG_TIM_IRQ_STATUS_Pos (8UL)

TIM_IRQ_STATUS (Bit 8)

◆ TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk

#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Msk (0xcUL)

TIM_ONESHOT_PHASE (Bitfield-Mask: 0x03)

◆ TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos

#define TIMER_TIMER_STATUS_REG_TIM_ONESHOT_PHASE_Pos (2UL)

TIM_ONESHOT_PHASE (Bit 2)

◆ TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Msk

#define TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Msk (0x400UL)

TIM_PWM_BUSY (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Pos

#define TIMER_TIMER_STATUS_REG_TIM_PWM_BUSY_Pos (10UL)

TIM_PWM_BUSY (Bit 10)

◆ TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk

#define TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Msk (0x800UL)

TIM_SWITCHED_TO_DIVN_CLK (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos

#define TIMER_TIMER_STATUS_REG_TIM_SWITCHED_TO_DIVN_CLK_Pos (11UL)

TIM_SWITCHED_TO_DIVN_CLK (Bit 11)

◆ TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Msk

#define TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Msk (0x200UL)

TIM_TIMER_BUSY (Bitfield-Mask: 0x01)

◆ TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Pos

#define TIMER_TIMER_STATUS_REG_TIM_TIMER_BUSY_Pos (9UL)

TIM_TIMER_BUSY (Bit 9)

◆ TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk

#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Msk (0xffffffUL)

TIM_TIMER_VALUE (Bitfield-Mask: 0xffffff)

◆ TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos

#define TIMER_TIMER_TIMER_VAL_REG_TIM_TIMER_VALUE_Pos (0UL)

TIM_TIMER_VALUE (Bit 0)

◆ UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Msk

#define UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Msk (0x1UL)

ISO7816_CONVENTION (Bitfield-Mask: 0x01)

◆ UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Pos

#define UART2_UART2_CONFIG_REG_ISO7816_CONVENTION_Pos (0UL)

ISO7816_CONVENTION (Bit 0)

◆ UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Msk

#define UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Msk (0x4UL)

ISO7816_ENABLE (Bitfield-Mask: 0x01)

◆ UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Pos

#define UART2_UART2_CONFIG_REG_ISO7816_ENABLE_Pos (2UL)

ISO7816_ENABLE (Bit 2)

◆ UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk

#define UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Msk (0x2UL)

ISO7816_ERR_SIG_EN (Bitfield-Mask: 0x01)

◆ UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos

#define UART2_UART2_CONFIG_REG_ISO7816_ERR_SIG_EN_Pos (1UL)

ISO7816_ERR_SIG_EN (Bit 1)

◆ UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk

#define UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Msk (0xf8UL)

ISO7816_SCRATCH_PAD (Bitfield-Mask: 0x1f)

◆ UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos

#define UART2_UART2_CONFIG_REG_ISO7816_SCRATCH_PAD_Pos (3UL)

ISO7816_SCRATCH_PAD (Bit 3)

◆ UART2_UART2_CTR_REG_UART_CTR_Msk

#define UART2_UART2_CTR_REG_UART_CTR_Msk (0xffffffffUL)

UART_CTR (Bitfield-Mask: 0xffffffff)

◆ UART2_UART2_CTR_REG_UART_CTR_Pos

#define UART2_UART2_CTR_REG_UART_CTR_Pos (0UL)

UART_CTR (Bit 0)

◆ UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Msk

#define UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Msk (0x800UL)

ISO7816_AUTO_GT (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Pos

#define UART2_UART2_CTRL_REG_ISO7816_AUTO_GT_Pos (11UL)

ISO7816_AUTO_GT (Bit 11)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Msk

#define UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Msk (0x1fUL)

ISO7816_CLK_DIV (Bitfield-Mask: 0x1f)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Pos

#define UART2_UART2_CTRL_REG_ISO7816_CLK_DIV_Pos (0UL)

ISO7816_CLK_DIV (Bit 0)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Msk

#define UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Msk (0x20UL)

ISO7816_CLK_EN (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Pos

#define UART2_UART2_CTRL_REG_ISO7816_CLK_EN_Pos (5UL)

ISO7816_CLK_EN (Bit 5)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Msk

#define UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Msk (0x40UL)

ISO7816_CLK_LEVEL (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Pos

#define UART2_UART2_CTRL_REG_ISO7816_CLK_LEVEL_Pos (6UL)

ISO7816_CLK_LEVEL (Bit 6)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Msk

#define UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Msk (0x80UL)

ISO7816_CLK_STATUS (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Pos

#define UART2_UART2_CTRL_REG_ISO7816_CLK_STATUS_Pos (7UL)

ISO7816_CLK_STATUS (Bit 7)

◆ UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk

#define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Msk (0x200UL)

ISO7816_ERR_TX_TIME_IRQMASK (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos

#define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_TIME_IRQMASK_Pos (9UL)

ISO7816_ERR_TX_TIME_IRQMASK (Bit 9)

◆ UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk

#define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Msk (0x400UL)

ISO7816_ERR_TX_VALUE_IRQMASK (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos

#define UART2_UART2_CTRL_REG_ISO7816_ERR_TX_VALUE_IRQMASK_Pos (10UL)

ISO7816_ERR_TX_VALUE_IRQMASK (Bit 10)

◆ UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk

#define UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Msk (0x100UL)

ISO7816_TIM_EXPIRED_IRQMASK (Bitfield-Mask: 0x01)

◆ UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos

#define UART2_UART2_CTRL_REG_ISO7816_TIM_EXPIRED_IRQMASK_Pos (8UL)

ISO7816_TIM_EXPIRED_IRQMASK (Bit 8)

◆ UART2_UART2_DLF_REG_UART_DLF_Msk

#define UART2_UART2_DLF_REG_UART_DLF_Msk (0xfUL)

UART_DLF (Bitfield-Mask: 0x0f)

◆ UART2_UART2_DLF_REG_UART_DLF_Pos

#define UART2_UART2_DLF_REG_UART_DLF_Pos (0UL)

UART_DLF (Bit 0)

◆ UART2_UART2_DMASA_REG_UART_DMASA_Msk

#define UART2_UART2_DMASA_REG_UART_DMASA_Msk (0x1UL)

UART_DMASA (Bitfield-Mask: 0x01)

◆ UART2_UART2_DMASA_REG_UART_DMASA_Pos

#define UART2_UART2_DMASA_REG_UART_DMASA_Pos (0UL)

UART_DMASA (Bit 0)

◆ UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk

#define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Msk (0xfUL)

ISO7816_ERR_PULSE_OFFSET (Bitfield-Mask: 0x0f)

◆ UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos

#define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_OFFSET_Pos (0UL)

ISO7816_ERR_PULSE_OFFSET (Bit 0)

◆ UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk

#define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Msk (0x1f0UL)

ISO7816_ERR_PULSE_WIDTH (Bitfield-Mask: 0x1f)

◆ UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos

#define UART2_UART2_ERR_CTRL_REG_ISO7816_ERR_PULSE_WIDTH_Pos (4UL)

ISO7816_ERR_PULSE_WIDTH (Bit 4)

◆ UART2_UART2_HTX_REG_UART_HALT_TX_Msk

#define UART2_UART2_HTX_REG_UART_HALT_TX_Msk (0x1UL)

UART_HALT_TX (Bitfield-Mask: 0x01)

◆ UART2_UART2_HTX_REG_UART_HALT_TX_Pos

#define UART2_UART2_HTX_REG_UART_HALT_TX_Pos (0UL)

UART_HALT_TX (Bit 0)

◆ UART2_UART2_IER_DLH_REG_DLH6_5_Msk

#define UART2_UART2_IER_DLH_REG_DLH6_5_Msk (0x60UL)

DLH6_5 (Bitfield-Mask: 0x03)

◆ UART2_UART2_IER_DLH_REG_DLH6_5_Pos

#define UART2_UART2_IER_DLH_REG_DLH6_5_Pos (5UL)

DLH6_5 (Bit 5)

◆ UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk

#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)

EDSSI_DLH3 (Bitfield-Mask: 0x01)

◆ UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos

#define UART2_UART2_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)

EDSSI_DLH3 (Bit 3)

◆ UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk

#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)

ELCOLR_DLH4 (Bitfield-Mask: 0x01)

◆ UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos

#define UART2_UART2_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)

ELCOLR_DLH4 (Bit 4)

◆ UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk

#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)

ELSI_DLH2 (Bitfield-Mask: 0x01)

◆ UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos

#define UART2_UART2_IER_DLH_REG_ELSI_DLH2_Pos (2UL)

ELSI_DLH2 (Bit 2)

◆ UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk

#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)

ERBFI_DLH0 (Bitfield-Mask: 0x01)

◆ UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos

#define UART2_UART2_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)

ERBFI_DLH0 (Bit 0)

◆ UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk

#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)

ETBEI_DLH1 (Bitfield-Mask: 0x01)

◆ UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos

#define UART2_UART2_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)

ETBEI_DLH1 (Bit 1)

◆ UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk

#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)

PTIME_DLH7 (Bitfield-Mask: 0x01)

◆ UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos

#define UART2_UART2_IER_DLH_REG_PTIME_DLH7_Pos (7UL)

PTIME_DLH7 (Bit 7)

◆ UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk

#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)

IIR_FCR (Bitfield-Mask: 0xff)

◆ UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos

#define UART2_UART2_IIR_FCR_REG_IIR_FCR_Pos (0UL)

IIR_FCR (Bit 0)

◆ UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk

#define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Msk (0x2UL)

ISO7816_ERR_TX_TIME_IRQ (Bitfield-Mask: 0x01)

◆ UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos

#define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_TIME_IRQ_Pos (1UL)

ISO7816_ERR_TX_TIME_IRQ (Bit 1)

◆ UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk

#define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Msk (0x4UL)

ISO7816_ERR_TX_VALUE_IRQ (Bitfield-Mask: 0x01)

◆ UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos

#define UART2_UART2_IRQ_STATUS_REG_ISO7816_ERR_TX_VALUE_IRQ_Pos (2UL)

ISO7816_ERR_TX_VALUE_IRQ (Bit 2)

◆ UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk

#define UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Msk (0x1UL)

ISO7816_TIM_EXPIRED_IRQ (Bitfield-Mask: 0x01)

◆ UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos

#define UART2_UART2_IRQ_STATUS_REG_ISO7816_TIM_EXPIRED_IRQ_Pos (0UL)

ISO7816_TIM_EXPIRED_IRQ (Bit 0)

◆ UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk

#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Msk (0x2UL)

UART_ADDR_MATCH (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos

#define UART2_UART2_LCR_EXT_UART_ADDR_MATCH_Pos (1UL)

UART_ADDR_MATCH (Bit 1)

◆ UART2_UART2_LCR_EXT_UART_DLS_E_Msk

#define UART2_UART2_LCR_EXT_UART_DLS_E_Msk (0x1UL)

UART_DLS_E (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_EXT_UART_DLS_E_Pos

#define UART2_UART2_LCR_EXT_UART_DLS_E_Pos (0UL)

UART_DLS_E (Bit 0)

◆ UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk

#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Msk (0x4UL)

UART_SEND_ADDR (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos

#define UART2_UART2_LCR_EXT_UART_SEND_ADDR_Pos (2UL)

UART_SEND_ADDR (Bit 2)

◆ UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk

#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Msk (0x8UL)

UART_TRANSMIT_MODE (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos

#define UART2_UART2_LCR_EXT_UART_TRANSMIT_MODE_Pos (3UL)

UART_TRANSMIT_MODE (Bit 3)

◆ UART2_UART2_LCR_REG_UART_BC_Msk

#define UART2_UART2_LCR_REG_UART_BC_Msk (0x40UL)

UART_BC (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_REG_UART_BC_Pos

#define UART2_UART2_LCR_REG_UART_BC_Pos (6UL)

UART_BC (Bit 6)

◆ UART2_UART2_LCR_REG_UART_DLAB_Msk

#define UART2_UART2_LCR_REG_UART_DLAB_Msk (0x80UL)

UART_DLAB (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_REG_UART_DLAB_Pos

#define UART2_UART2_LCR_REG_UART_DLAB_Pos (7UL)

UART_DLAB (Bit 7)

◆ UART2_UART2_LCR_REG_UART_DLS_Msk

#define UART2_UART2_LCR_REG_UART_DLS_Msk (0x3UL)

UART_DLS (Bitfield-Mask: 0x03)

◆ UART2_UART2_LCR_REG_UART_DLS_Pos

#define UART2_UART2_LCR_REG_UART_DLS_Pos (0UL)

UART_DLS (Bit 0)

◆ UART2_UART2_LCR_REG_UART_EPS_Msk

#define UART2_UART2_LCR_REG_UART_EPS_Msk (0x10UL)

UART_EPS (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_REG_UART_EPS_Pos

#define UART2_UART2_LCR_REG_UART_EPS_Pos (4UL)

UART_EPS (Bit 4)

◆ UART2_UART2_LCR_REG_UART_PEN_Msk

#define UART2_UART2_LCR_REG_UART_PEN_Msk (0x8UL)

UART_PEN (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_REG_UART_PEN_Pos

#define UART2_UART2_LCR_REG_UART_PEN_Pos (3UL)

UART_PEN (Bit 3)

◆ UART2_UART2_LCR_REG_UART_SP_Msk

#define UART2_UART2_LCR_REG_UART_SP_Msk (0x20UL)

UART_SP (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_REG_UART_SP_Pos

#define UART2_UART2_LCR_REG_UART_SP_Pos (5UL)

UART_SP (Bit 5)

◆ UART2_UART2_LCR_REG_UART_STOP_Msk

#define UART2_UART2_LCR_REG_UART_STOP_Msk (0x4UL)

UART_STOP (Bitfield-Mask: 0x01)

◆ UART2_UART2_LCR_REG_UART_STOP_Pos

#define UART2_UART2_LCR_REG_UART_STOP_Pos (2UL)

UART_STOP (Bit 2)

◆ UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk

#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Msk (0x100UL)

UART_ADDR_RCVD (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos

#define UART2_UART2_LSR_REG_UART_ADDR_RCVD_Pos (8UL)

UART_ADDR_RCVD (Bit 8)

◆ UART2_UART2_LSR_REG_UART_BI_Msk

#define UART2_UART2_LSR_REG_UART_BI_Msk (0x10UL)

UART_BI (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_BI_Pos

#define UART2_UART2_LSR_REG_UART_BI_Pos (4UL)

UART_BI (Bit 4)

◆ UART2_UART2_LSR_REG_UART_DR_Msk

#define UART2_UART2_LSR_REG_UART_DR_Msk (0x1UL)

UART_DR (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_DR_Pos

#define UART2_UART2_LSR_REG_UART_DR_Pos (0UL)

UART_DR (Bit 0)

◆ UART2_UART2_LSR_REG_UART_FE_Msk

#define UART2_UART2_LSR_REG_UART_FE_Msk (0x8UL)

UART_FE (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_FE_Pos

#define UART2_UART2_LSR_REG_UART_FE_Pos (3UL)

UART_FE (Bit 3)

◆ UART2_UART2_LSR_REG_UART_OE_Msk

#define UART2_UART2_LSR_REG_UART_OE_Msk (0x2UL)

UART_OE (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_OE_Pos

#define UART2_UART2_LSR_REG_UART_OE_Pos (1UL)

UART_OE (Bit 1)

◆ UART2_UART2_LSR_REG_UART_PE_Msk

#define UART2_UART2_LSR_REG_UART_PE_Msk (0x4UL)

UART_PE (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_PE_Pos

#define UART2_UART2_LSR_REG_UART_PE_Pos (2UL)

UART_PE (Bit 2)

◆ UART2_UART2_LSR_REG_UART_RFE_Msk

#define UART2_UART2_LSR_REG_UART_RFE_Msk (0x80UL)

UART_RFE (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_RFE_Pos

#define UART2_UART2_LSR_REG_UART_RFE_Pos (7UL)

UART_RFE (Bit 7)

◆ UART2_UART2_LSR_REG_UART_TEMT_Msk

#define UART2_UART2_LSR_REG_UART_TEMT_Msk (0x40UL)

UART_TEMT (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_TEMT_Pos

#define UART2_UART2_LSR_REG_UART_TEMT_Pos (6UL)

UART_TEMT (Bit 6)

◆ UART2_UART2_LSR_REG_UART_THRE_Msk

#define UART2_UART2_LSR_REG_UART_THRE_Msk (0x20UL)

UART_THRE (Bitfield-Mask: 0x01)

◆ UART2_UART2_LSR_REG_UART_THRE_Pos

#define UART2_UART2_LSR_REG_UART_THRE_Pos (5UL)

UART_THRE (Bit 5)

◆ UART2_UART2_MCR_REG_UART_AFCE_Msk

#define UART2_UART2_MCR_REG_UART_AFCE_Msk (0x20UL)

UART_AFCE (Bitfield-Mask: 0x01)

◆ UART2_UART2_MCR_REG_UART_AFCE_Pos

#define UART2_UART2_MCR_REG_UART_AFCE_Pos (5UL)

UART_AFCE (Bit 5)

◆ UART2_UART2_MCR_REG_UART_LB_Msk

#define UART2_UART2_MCR_REG_UART_LB_Msk (0x10UL)

UART_LB (Bitfield-Mask: 0x01)

◆ UART2_UART2_MCR_REG_UART_LB_Pos

#define UART2_UART2_MCR_REG_UART_LB_Pos (4UL)

UART_LB (Bit 4)

◆ UART2_UART2_MCR_REG_UART_RTS_Msk

#define UART2_UART2_MCR_REG_UART_RTS_Msk (0x2UL)

UART_RTS (Bitfield-Mask: 0x01)

◆ UART2_UART2_MCR_REG_UART_RTS_Pos

#define UART2_UART2_MCR_REG_UART_RTS_Pos (1UL)

UART_RTS (Bit 1)

◆ UART2_UART2_MSR_REG_UART_CTS_Msk

#define UART2_UART2_MSR_REG_UART_CTS_Msk (0x10UL)

UART_CTS (Bitfield-Mask: 0x01)

◆ UART2_UART2_MSR_REG_UART_CTS_Pos

#define UART2_UART2_MSR_REG_UART_CTS_Pos (4UL)

UART_CTS (Bit 4)

◆ UART2_UART2_MSR_REG_UART_DCTS_Msk

#define UART2_UART2_MSR_REG_UART_DCTS_Msk (0x1UL)

UART_DCTS (Bitfield-Mask: 0x01)

◆ UART2_UART2_MSR_REG_UART_DCTS_Pos

#define UART2_UART2_MSR_REG_UART_DCTS_Pos (0UL)

UART_DCTS (Bit 0)

◆ UART2_UART2_RAR_REG_UART_RAR_Msk

#define UART2_UART2_RAR_REG_UART_RAR_Msk (0xffUL)

UART_RAR (Bitfield-Mask: 0xff)

◆ UART2_UART2_RAR_REG_UART_RAR_Pos

#define UART2_UART2_RAR_REG_UART_RAR_Pos (0UL)

UART_RAR (Bit 0)

◆ UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk

#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Msk (0x100UL)

RBR_THR_9BIT (Bitfield-Mask: 0x01)

◆ UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos

#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_9BIT_Pos (8UL)

RBR_THR_9BIT (Bit 8)

◆ UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk

#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)

RBR_THR_DLL (Bitfield-Mask: 0xff)

◆ UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos

#define UART2_UART2_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)

RBR_THR_DLL (Bit 0)

◆ UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk

#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)

UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f)

◆ UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos

#define UART2_UART2_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)

UART_RECEIVE_FIFO_LEVEL (Bit 0)

◆ UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk

#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)

UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)

◆ UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos

#define UART2_UART2_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)

UART_SHADOW_BREAK_CONTROL (Bit 0)

◆ UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk

#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)

UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01)

◆ UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos

#define UART2_UART2_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)

UART_SHADOW_DMA_MODE (Bit 0)

◆ UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk

#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)

UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01)

◆ UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos

#define UART2_UART2_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)

UART_SHADOW_FIFO_ENABLE (Bit 0)

◆ UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk

#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos

#define UART2_UART2_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART2_UART2_SRR_REG_UART_RFR_Msk

#define UART2_UART2_SRR_REG_UART_RFR_Msk (0x2UL)

UART_RFR (Bitfield-Mask: 0x01)

◆ UART2_UART2_SRR_REG_UART_RFR_Pos

#define UART2_UART2_SRR_REG_UART_RFR_Pos (1UL)

UART_RFR (Bit 1)

◆ UART2_UART2_SRR_REG_UART_UR_Msk

#define UART2_UART2_SRR_REG_UART_UR_Msk (0x1UL)

UART_UR (Bitfield-Mask: 0x01)

◆ UART2_UART2_SRR_REG_UART_UR_Pos

#define UART2_UART2_SRR_REG_UART_UR_Pos (0UL)

UART_UR (Bit 0)

◆ UART2_UART2_SRR_REG_UART_XFR_Msk

#define UART2_UART2_SRR_REG_UART_XFR_Msk (0x4UL)

UART_XFR (Bitfield-Mask: 0x01)

◆ UART2_UART2_SRR_REG_UART_XFR_Pos

#define UART2_UART2_SRR_REG_UART_XFR_Pos (2UL)

UART_XFR (Bit 2)

◆ UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk

#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)

UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03)

◆ UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos

#define UART2_UART2_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)

UART_SHADOW_RCVR_TRIGGER (Bit 0)

◆ UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk

#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Msk (0x1UL)

UART_SHADOW_REQUEST_TO_SEND (Bitfield-Mask: 0x01)

◆ UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos

#define UART2_UART2_SRTS_REG_UART_SHADOW_REQUEST_TO_SEND_Pos (0UL)

UART_SHADOW_REQUEST_TO_SEND (Bit 0)

◆ UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk

#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)

UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03)

◆ UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos

#define UART2_UART2_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)

UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)

◆ UART2_UART2_TAR_REG_UART_TAR_Msk

#define UART2_UART2_TAR_REG_UART_TAR_Msk (0xffUL)

UART_TAR (Bitfield-Mask: 0xff)

◆ UART2_UART2_TAR_REG_UART_TAR_Pos

#define UART2_UART2_TAR_REG_UART_TAR_Pos (0UL)

UART_TAR (Bit 0)

◆ UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk

#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)

UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f)

◆ UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos

#define UART2_UART2_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)

UART_TRANSMIT_FIFO_LEVEL (Bit 0)

◆ UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Msk

#define UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Msk (0x10000UL)

ISO7816_TIM_EN (Bitfield-Mask: 0x01)

◆ UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Pos

#define UART2_UART2_TIMER_REG_ISO7816_TIM_EN_Pos (16UL)

ISO7816_TIM_EN (Bit 16)

◆ UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Msk

#define UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Msk (0xffffUL)

ISO7816_TIM_MAX (Bitfield-Mask: 0xffff)

◆ UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Pos

#define UART2_UART2_TIMER_REG_ISO7816_TIM_MAX_Pos (0UL)

ISO7816_TIM_MAX (Bit 0)

◆ UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Msk

#define UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Msk (0x20000UL)

ISO7816_TIM_MODE (Bitfield-Mask: 0x01)

◆ UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Pos

#define UART2_UART2_TIMER_REG_ISO7816_TIM_MODE_Pos (17UL)

ISO7816_TIM_MODE (Bit 17)

◆ UART2_UART2_UCV_REG_UART_UCV_Msk

#define UART2_UART2_UCV_REG_UART_UCV_Msk (0xffffffffUL)

UART_UCV (Bitfield-Mask: 0xffffffff)

◆ UART2_UART2_UCV_REG_UART_UCV_Pos

#define UART2_UART2_UCV_REG_UART_UCV_Pos (0UL)

UART_UCV (Bit 0)

◆ UART2_UART2_USR_REG_UART_BUSY_Msk

#define UART2_UART2_USR_REG_UART_BUSY_Msk (0x1UL)

UART_BUSY (Bitfield-Mask: 0x01)

◆ UART2_UART2_USR_REG_UART_BUSY_Pos

#define UART2_UART2_USR_REG_UART_BUSY_Pos (0UL)

UART_BUSY (Bit 0)

◆ UART2_UART2_USR_REG_UART_RFF_Msk

#define UART2_UART2_USR_REG_UART_RFF_Msk (0x10UL)

UART_RFF (Bitfield-Mask: 0x01)

◆ UART2_UART2_USR_REG_UART_RFF_Pos

#define UART2_UART2_USR_REG_UART_RFF_Pos (4UL)

UART_RFF (Bit 4)

◆ UART2_UART2_USR_REG_UART_RFNE_Msk

#define UART2_UART2_USR_REG_UART_RFNE_Msk (0x8UL)

UART_RFNE (Bitfield-Mask: 0x01)

◆ UART2_UART2_USR_REG_UART_RFNE_Pos

#define UART2_UART2_USR_REG_UART_RFNE_Pos (3UL)

UART_RFNE (Bit 3)

◆ UART2_UART2_USR_REG_UART_TFE_Msk

#define UART2_UART2_USR_REG_UART_TFE_Msk (0x4UL)

UART_TFE (Bitfield-Mask: 0x01)

◆ UART2_UART2_USR_REG_UART_TFE_Pos

#define UART2_UART2_USR_REG_UART_TFE_Pos (2UL)

UART_TFE (Bit 2)

◆ UART2_UART2_USR_REG_UART_TFNF_Msk

#define UART2_UART2_USR_REG_UART_TFNF_Msk (0x2UL)

UART_TFNF (Bitfield-Mask: 0x01)

◆ UART2_UART2_USR_REG_UART_TFNF_Pos

#define UART2_UART2_USR_REG_UART_TFNF_Pos (1UL)

UART_TFNF (Bit 1)

◆ UART_UART_CTR_REG_UART_CTR_Msk

#define UART_UART_CTR_REG_UART_CTR_Msk (0xffffffffUL)

UART_CTR (Bitfield-Mask: 0xffffffff)

◆ UART_UART_CTR_REG_UART_CTR_Pos

#define UART_UART_CTR_REG_UART_CTR_Pos (0UL)

UART_CTR (Bit 0)

◆ UART_UART_DLF_REG_UART_DLF_Msk

#define UART_UART_DLF_REG_UART_DLF_Msk (0xfUL)

UART_DLF (Bitfield-Mask: 0x0f)

◆ UART_UART_DLF_REG_UART_DLF_Pos

#define UART_UART_DLF_REG_UART_DLF_Pos (0UL)

UART_DLF (Bit 0)

◆ UART_UART_DMASA_REG_UART_DMASA_Msk

#define UART_UART_DMASA_REG_UART_DMASA_Msk (0x1UL)

UART_DMASA (Bitfield-Mask: 0x01)

◆ UART_UART_DMASA_REG_UART_DMASA_Pos

#define UART_UART_DMASA_REG_UART_DMASA_Pos (0UL)

UART_DMASA (Bit 0)

◆ UART_UART_HTX_REG_UART_HALT_TX_Msk

#define UART_UART_HTX_REG_UART_HALT_TX_Msk (0x1UL)

UART_HALT_TX (Bitfield-Mask: 0x01)

◆ UART_UART_HTX_REG_UART_HALT_TX_Pos

#define UART_UART_HTX_REG_UART_HALT_TX_Pos (0UL)

UART_HALT_TX (Bit 0)

◆ UART_UART_IER_DLH_REG_DLH6_5_Msk

#define UART_UART_IER_DLH_REG_DLH6_5_Msk (0x60UL)

DLH6_5 (Bitfield-Mask: 0x03)

◆ UART_UART_IER_DLH_REG_DLH6_5_Pos

#define UART_UART_IER_DLH_REG_DLH6_5_Pos (5UL)

DLH6_5 (Bit 5)

◆ UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk

#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Msk (0x8UL)

EDSSI_DLH3 (Bitfield-Mask: 0x01)

◆ UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos

#define UART_UART_IER_DLH_REG_EDSSI_DLH3_Pos (3UL)

EDSSI_DLH3 (Bit 3)

◆ UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk

#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Msk (0x10UL)

ELCOLR_DLH4 (Bitfield-Mask: 0x01)

◆ UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos

#define UART_UART_IER_DLH_REG_ELCOLR_DLH4_Pos (4UL)

ELCOLR_DLH4 (Bit 4)

◆ UART_UART_IER_DLH_REG_ELSI_DLH2_Msk

#define UART_UART_IER_DLH_REG_ELSI_DLH2_Msk (0x4UL)

ELSI_DLH2 (Bitfield-Mask: 0x01)

◆ UART_UART_IER_DLH_REG_ELSI_DLH2_Pos

#define UART_UART_IER_DLH_REG_ELSI_DLH2_Pos (2UL)

ELSI_DLH2 (Bit 2)

◆ UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk

#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Msk (0x1UL)

ERBFI_DLH0 (Bitfield-Mask: 0x01)

◆ UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos

#define UART_UART_IER_DLH_REG_ERBFI_DLH0_Pos (0UL)

ERBFI_DLH0 (Bit 0)

◆ UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk

#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Msk (0x2UL)

ETBEI_DLH1 (Bitfield-Mask: 0x01)

◆ UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos

#define UART_UART_IER_DLH_REG_ETBEI_DLH1_Pos (1UL)

ETBEI_DLH1 (Bit 1)

◆ UART_UART_IER_DLH_REG_PTIME_DLH7_Msk

#define UART_UART_IER_DLH_REG_PTIME_DLH7_Msk (0x80UL)

PTIME_DLH7 (Bitfield-Mask: 0x01)

◆ UART_UART_IER_DLH_REG_PTIME_DLH7_Pos

#define UART_UART_IER_DLH_REG_PTIME_DLH7_Pos (7UL)

PTIME_DLH7 (Bit 7)

◆ UART_UART_IIR_FCR_REG_IIR_FCR_Msk

#define UART_UART_IIR_FCR_REG_IIR_FCR_Msk (0xffUL)

IIR_FCR (Bitfield-Mask: 0xff)

◆ UART_UART_IIR_FCR_REG_IIR_FCR_Pos

#define UART_UART_IIR_FCR_REG_IIR_FCR_Pos (0UL)

IIR_FCR (Bit 0)

◆ UART_UART_LCR_REG_UART_BC_Msk

#define UART_UART_LCR_REG_UART_BC_Msk (0x40UL)

UART_BC (Bitfield-Mask: 0x01)

◆ UART_UART_LCR_REG_UART_BC_Pos

#define UART_UART_LCR_REG_UART_BC_Pos (6UL)

UART_BC (Bit 6)

◆ UART_UART_LCR_REG_UART_DLAB_Msk

#define UART_UART_LCR_REG_UART_DLAB_Msk (0x80UL)

UART_DLAB (Bitfield-Mask: 0x01)

◆ UART_UART_LCR_REG_UART_DLAB_Pos

#define UART_UART_LCR_REG_UART_DLAB_Pos (7UL)

UART_DLAB (Bit 7)

◆ UART_UART_LCR_REG_UART_DLS_Msk

#define UART_UART_LCR_REG_UART_DLS_Msk (0x3UL)

UART_DLS (Bitfield-Mask: 0x03)

◆ UART_UART_LCR_REG_UART_DLS_Pos

#define UART_UART_LCR_REG_UART_DLS_Pos (0UL)

UART_DLS (Bit 0)

◆ UART_UART_LCR_REG_UART_EPS_Msk

#define UART_UART_LCR_REG_UART_EPS_Msk (0x10UL)

UART_EPS (Bitfield-Mask: 0x01)

◆ UART_UART_LCR_REG_UART_EPS_Pos

#define UART_UART_LCR_REG_UART_EPS_Pos (4UL)

UART_EPS (Bit 4)

◆ UART_UART_LCR_REG_UART_PEN_Msk

#define UART_UART_LCR_REG_UART_PEN_Msk (0x8UL)

UART_PEN (Bitfield-Mask: 0x01)

◆ UART_UART_LCR_REG_UART_PEN_Pos

#define UART_UART_LCR_REG_UART_PEN_Pos (3UL)

UART_PEN (Bit 3)

◆ UART_UART_LCR_REG_UART_STOP_Msk

#define UART_UART_LCR_REG_UART_STOP_Msk (0x4UL)

UART_STOP (Bitfield-Mask: 0x01)

◆ UART_UART_LCR_REG_UART_STOP_Pos

#define UART_UART_LCR_REG_UART_STOP_Pos (2UL)

UART_STOP (Bit 2)

◆ UART_UART_LSR_REG_UART_BI_Msk

#define UART_UART_LSR_REG_UART_BI_Msk (0x10UL)

UART_BI (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_BI_Pos

#define UART_UART_LSR_REG_UART_BI_Pos (4UL)

UART_BI (Bit 4)

◆ UART_UART_LSR_REG_UART_DR_Msk

#define UART_UART_LSR_REG_UART_DR_Msk (0x1UL)

UART_DR (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_DR_Pos

#define UART_UART_LSR_REG_UART_DR_Pos (0UL)

UART_DR (Bit 0)

◆ UART_UART_LSR_REG_UART_FE_Msk

#define UART_UART_LSR_REG_UART_FE_Msk (0x8UL)

UART_FE (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_FE_Pos

#define UART_UART_LSR_REG_UART_FE_Pos (3UL)

UART_FE (Bit 3)

◆ UART_UART_LSR_REG_UART_OE_Msk

#define UART_UART_LSR_REG_UART_OE_Msk (0x2UL)

UART_OE (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_OE_Pos

#define UART_UART_LSR_REG_UART_OE_Pos (1UL)

UART_OE (Bit 1)

◆ UART_UART_LSR_REG_UART_PE_Msk

#define UART_UART_LSR_REG_UART_PE_Msk (0x4UL)

UART_PE (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_PE_Pos

#define UART_UART_LSR_REG_UART_PE_Pos (2UL)

UART_PE (Bit 2)

◆ UART_UART_LSR_REG_UART_RFE_Msk

#define UART_UART_LSR_REG_UART_RFE_Msk (0x80UL)

UART_RFE (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_RFE_Pos

#define UART_UART_LSR_REG_UART_RFE_Pos (7UL)

UART_RFE (Bit 7)

◆ UART_UART_LSR_REG_UART_TEMT_Msk

#define UART_UART_LSR_REG_UART_TEMT_Msk (0x40UL)

UART_TEMT (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_TEMT_Pos

#define UART_UART_LSR_REG_UART_TEMT_Pos (6UL)

UART_TEMT (Bit 6)

◆ UART_UART_LSR_REG_UART_THRE_Msk

#define UART_UART_LSR_REG_UART_THRE_Msk (0x20UL)

UART_THRE (Bitfield-Mask: 0x01)

◆ UART_UART_LSR_REG_UART_THRE_Pos

#define UART_UART_LSR_REG_UART_THRE_Pos (5UL)

UART_THRE (Bit 5)

◆ UART_UART_MCR_REG_UART_LB_Msk

#define UART_UART_MCR_REG_UART_LB_Msk (0x10UL)

UART_LB (Bitfield-Mask: 0x01)

◆ UART_UART_MCR_REG_UART_LB_Pos

#define UART_UART_MCR_REG_UART_LB_Pos (4UL)

UART_LB (Bit 4)

◆ UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk

#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Msk (0xffUL)

RBR_THR_DLL (Bitfield-Mask: 0xff)

◆ UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos

#define UART_UART_RBR_THR_DLL_REG_RBR_THR_DLL_Pos (0UL)

RBR_THR_DLL (Bit 0)

◆ UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk

#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Msk (0x1fUL)

UART_RECEIVE_FIFO_LEVEL (Bitfield-Mask: 0x1f)

◆ UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos

#define UART_UART_RFL_REG_UART_RECEIVE_FIFO_LEVEL_Pos (0UL)

UART_RECEIVE_FIFO_LEVEL (Bit 0)

◆ UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk

#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Msk (0x1UL)

UART_SHADOW_BREAK_CONTROL (Bitfield-Mask: 0x01)

◆ UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos

#define UART_UART_SBCR_REG_UART_SHADOW_BREAK_CONTROL_Pos (0UL)

UART_SHADOW_BREAK_CONTROL (Bit 0)

◆ UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk

#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Msk (0xffUL)

UART_SCRATCH_PAD (Bitfield-Mask: 0xff)

◆ UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos

#define UART_UART_SCR_REG_UART_SCRATCH_PAD_Pos (0UL)

UART_SCRATCH_PAD (Bit 0)

◆ UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk

#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Msk (0x1UL)

UART_SHADOW_DMA_MODE (Bitfield-Mask: 0x01)

◆ UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos

#define UART_UART_SDMAM_REG_UART_SHADOW_DMA_MODE_Pos (0UL)

UART_SHADOW_DMA_MODE (Bit 0)

◆ UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk

#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Msk (0x1UL)

UART_SHADOW_FIFO_ENABLE (Bitfield-Mask: 0x01)

◆ UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos

#define UART_UART_SFE_REG_UART_SHADOW_FIFO_ENABLE_Pos (0UL)

UART_SHADOW_FIFO_ENABLE (Bit 0)

◆ UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR0_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR10_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR11_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR12_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR13_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR14_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR15_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR1_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR2_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR3_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR4_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR5_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR6_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR7_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR8_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk

#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Msk (0xffUL)

SRBR_STHRx (Bitfield-Mask: 0xff)

◆ UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos

#define UART_UART_SRBR_STHR9_REG_SRBR_STHRx_Pos (0UL)

SRBR_STHRx (Bit 0)

◆ UART_UART_SRR_REG_UART_RFR_Msk

#define UART_UART_SRR_REG_UART_RFR_Msk (0x2UL)

UART_RFR (Bitfield-Mask: 0x01)

◆ UART_UART_SRR_REG_UART_RFR_Pos

#define UART_UART_SRR_REG_UART_RFR_Pos (1UL)

UART_RFR (Bit 1)

◆ UART_UART_SRR_REG_UART_UR_Msk

#define UART_UART_SRR_REG_UART_UR_Msk (0x1UL)

UART_UR (Bitfield-Mask: 0x01)

◆ UART_UART_SRR_REG_UART_UR_Pos

#define UART_UART_SRR_REG_UART_UR_Pos (0UL)

UART_UR (Bit 0)

◆ UART_UART_SRR_REG_UART_XFR_Msk

#define UART_UART_SRR_REG_UART_XFR_Msk (0x4UL)

UART_XFR (Bitfield-Mask: 0x01)

◆ UART_UART_SRR_REG_UART_XFR_Pos

#define UART_UART_SRR_REG_UART_XFR_Pos (2UL)

UART_XFR (Bit 2)

◆ UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk

#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Msk (0x3UL)

UART_SHADOW_RCVR_TRIGGER (Bitfield-Mask: 0x03)

◆ UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos

#define UART_UART_SRT_REG_UART_SHADOW_RCVR_TRIGGER_Pos (0UL)

UART_SHADOW_RCVR_TRIGGER (Bit 0)

◆ UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk

#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Msk (0x3UL)

UART_SHADOW_TX_EMPTY_TRIGGER (Bitfield-Mask: 0x03)

◆ UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos

#define UART_UART_STET_REG_UART_SHADOW_TX_EMPTY_TRIGGER_Pos (0UL)

UART_SHADOW_TX_EMPTY_TRIGGER (Bit 0)

◆ UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk

#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Msk (0x1fUL)

UART_TRANSMIT_FIFO_LEVEL (Bitfield-Mask: 0x1f)

◆ UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos

#define UART_UART_TFL_REG_UART_TRANSMIT_FIFO_LEVEL_Pos (0UL)

UART_TRANSMIT_FIFO_LEVEL (Bit 0)

◆ UART_UART_UCV_REG_UART_UCV_Msk

#define UART_UART_UCV_REG_UART_UCV_Msk (0xffffffffUL)

UART_UCV (Bitfield-Mask: 0xffffffff)

◆ UART_UART_UCV_REG_UART_UCV_Pos

#define UART_UART_UCV_REG_UART_UCV_Pos (0UL)

UART_UCV (Bit 0)

◆ UART_UART_USR_REG_UART_BUSY_Msk

#define UART_UART_USR_REG_UART_BUSY_Msk (0x1UL)

UART_BUSY (Bitfield-Mask: 0x01)

◆ UART_UART_USR_REG_UART_BUSY_Pos

#define UART_UART_USR_REG_UART_BUSY_Pos (0UL)

UART_BUSY (Bit 0)

◆ UART_UART_USR_REG_UART_RFF_Msk

#define UART_UART_USR_REG_UART_RFF_Msk (0x10UL)

UART_RFF (Bitfield-Mask: 0x01)

◆ UART_UART_USR_REG_UART_RFF_Pos

#define UART_UART_USR_REG_UART_RFF_Pos (4UL)

UART_RFF (Bit 4)

◆ UART_UART_USR_REG_UART_RFNE_Msk

#define UART_UART_USR_REG_UART_RFNE_Msk (0x8UL)

UART_RFNE (Bitfield-Mask: 0x01)

◆ UART_UART_USR_REG_UART_RFNE_Pos

#define UART_UART_USR_REG_UART_RFNE_Pos (3UL)

UART_RFNE (Bit 3)

◆ UART_UART_USR_REG_UART_TFE_Msk

#define UART_UART_USR_REG_UART_TFE_Msk (0x4UL)

UART_TFE (Bitfield-Mask: 0x01)

◆ UART_UART_USR_REG_UART_TFE_Pos

#define UART_UART_USR_REG_UART_TFE_Pos (2UL)

UART_TFE (Bit 2)

◆ UART_UART_USR_REG_UART_TFNF_Msk

#define UART_UART_USR_REG_UART_TFNF_Msk (0x2UL)

UART_TFNF (Bitfield-Mask: 0x01)

◆ UART_UART_USR_REG_UART_TFNF_Pos

#define UART_UART_USR_REG_UART_TFNF_Pos (1UL)

UART_TFNF (Bit 1)

◆ WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk

#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Msk (0xffffUL)

WKUP_CLEAR_P0 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos

#define WAKEUP_WKUP_CLEAR_P0_REG_WKUP_CLEAR_P0_Pos (0UL)

WKUP_CLEAR_P0 (Bit 0)

◆ WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk

#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Msk (0xffffUL)

WKUP_CLEAR_P1 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos

#define WAKEUP_WKUP_CLEAR_P1_REG_WKUP_CLEAR_P1_Pos (0UL)

WKUP_CLEAR_P1 (Bit 0)

◆ WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk

#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Msk (0x3fUL)

WKUP_DEB_VALUE (Bitfield-Mask: 0x3f)

◆ WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos

#define WAKEUP_WKUP_CTRL_REG_WKUP_DEB_VALUE_Pos (0UL)

WKUP_DEB_VALUE (Bit 0)

◆ WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk

#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Msk (0x80UL)

WKUP_ENABLE_IRQ (Bitfield-Mask: 0x01)

◆ WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos

#define WAKEUP_WKUP_CTRL_REG_WKUP_ENABLE_IRQ_Pos (7UL)

WKUP_ENABLE_IRQ (Bit 7)

◆ WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk

#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Msk (0x40UL)

WKUP_SFT_KEYHIT (Bitfield-Mask: 0x01)

◆ WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos

#define WAKEUP_WKUP_CTRL_REG_WKUP_SFT_KEYHIT_Pos (6UL)

WKUP_SFT_KEYHIT (Bit 6)

◆ WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk

#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Msk (0xffffUL)

WKUP_POL_P0 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos

#define WAKEUP_WKUP_POL_P0_REG_WKUP_POL_P0_Pos (0UL)

WKUP_POL_P0 (Bit 0)

◆ WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk

#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Msk (0xffffUL)

WKUP_POL_P1 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos

#define WAKEUP_WKUP_POL_P1_REG_WKUP_POL_P1_Pos (0UL)

WKUP_POL_P1 (Bit 0)

◆ WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk

#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Msk (0xffffUL)

WKUP_IRQ_RST (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos

#define WAKEUP_WKUP_RESET_IRQ_REG_WKUP_IRQ_RST_Pos (0UL)

WKUP_IRQ_RST (Bit 0)

◆ WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Msk

#define WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Msk (0xffffUL)

WKUP_SEL1_GPIO_P0 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Pos

#define WAKEUP_WKUP_SEL1_GPIO_P0_REG_WKUP_SEL1_GPIO_P0_Pos (0UL)

WKUP_SEL1_GPIO_P0 (Bit 0)

◆ WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Msk

#define WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Msk (0xffffUL)

WKUP_SEL1_GPIO_P1 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Pos

#define WAKEUP_WKUP_SEL1_GPIO_P1_REG_WKUP_SEL1_GPIO_P1_Pos (0UL)

WKUP_SEL1_GPIO_P1 (Bit 0)

◆ WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk

#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Msk (0xffffUL)

WKUP_SEL_GPIO_P0 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos

#define WAKEUP_WKUP_SEL_GPIO_P0_REG_WKUP_SEL_GPIO_P0_Pos (0UL)

WKUP_SEL_GPIO_P0 (Bit 0)

◆ WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk

#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Msk (0xffffUL)

WKUP_SEL_GPIO_P1 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos

#define WAKEUP_WKUP_SEL_GPIO_P1_REG_WKUP_SEL_GPIO_P1_Pos (0UL)

WKUP_SEL_GPIO_P1 (Bit 0)

◆ WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk

#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Msk (0xffffUL)

WKUP_SELECT_P0 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos

#define WAKEUP_WKUP_SELECT_P0_REG_WKUP_SELECT_P0_Pos (0UL)

WKUP_SELECT_P0 (Bit 0)

◆ WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk

#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Msk (0xffffUL)

WKUP_SELECT_P1 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos

#define WAKEUP_WKUP_SELECT_P1_REG_WKUP_SELECT_P1_Pos (0UL)

WKUP_SELECT_P1 (Bit 0)

◆ WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk

#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Msk (0xffffUL)

WKUP_STAT_P0 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos

#define WAKEUP_WKUP_STATUS_P0_REG_WKUP_STAT_P0_Pos (0UL)

WKUP_STAT_P0 (Bit 0)

◆ WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk

#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Msk (0xffffUL)

WKUP_STAT_P1 (Bitfield-Mask: 0xffff)

◆ WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos

#define WAKEUP_WKUP_STATUS_P1_REG_WKUP_STAT_P1_Pos (0UL)

WKUP_STAT_P1 (Bit 0)

Macros

Detailed Description

Macro Definition Documentation

◆ AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Msk

◆ AES_HASH_CRYPTO_CLRIRQ_REG_CRYPTO_CLRIRQ_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEXP_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_AES_KEY_SZ_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_MD_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ALG_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_ENCDEC_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_OUT_LEN_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_HASH_SEL_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_IRQ_EN_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_MORE_IN_Pos

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Msk

◆ AES_HASH_CRYPTO_CTRL_REG_CRYPTO_OUT_MD_Pos

◆ AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Msk

◆ AES_HASH_CRYPTO_DEST_ADDR_REG_CRYPTO_DEST_ADDR_Pos

◆ AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Msk

◆ AES_HASH_CRYPTO_FETCH_ADDR_REG_CRYPTO_FETCH_ADDR_Pos

◆ AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Msk

◆ AES_HASH_CRYPTO_KEYS_START_CRYPTO_KEY_X_Pos

◆ AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Msk

◆ AES_HASH_CRYPTO_LEN_REG_CRYPTO_LEN_Pos

◆ AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Msk

◆ AES_HASH_CRYPTO_MREG0_REG_CRYPTO_MREG0_Pos

◆ AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Msk

◆ AES_HASH_CRYPTO_MREG1_REG_CRYPTO_MREG1_Pos

◆ AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Msk

◆ AES_HASH_CRYPTO_MREG2_REG_CRYPTO_MREG2_Pos

◆ AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Msk

◆ AES_HASH_CRYPTO_MREG3_REG_CRYPTO_MREG3_Pos

◆ AES_HASH_CRYPTO_START_REG_CRYPTO_START_Msk

◆ AES_HASH_CRYPTO_START_REG_CRYPTO_START_Pos

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Msk

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_INACTIVE_Pos

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Msk

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_IRQ_ST_Pos

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Msk

◆ AES_HASH_CRYPTO_STATUS_REG_CRYPTO_WAIT_FOR_IN_Pos

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Msk

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_CLR_Pos

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Msk

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_EN_Pos

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Msk

◆ ANAMISC_BIF_CLK_CAL_IRQ_REG_CLK_CAL_IRQ_STATUS_Pos

◆ ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Msk

◆ ANAMISC_BIF_CLK_REF_CNT_REG_REF_CNT_VAL_Pos

◆ ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Msk

◆ ANAMISC_BIF_CLK_REF_SEL_REG_CAL_CLK_SEL_Pos

◆ ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Msk

◆ ANAMISC_BIF_CLK_REF_SEL_REG_EXT_CNT_EN_SEL_Pos

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Msk

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CAL_START_Pos

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Msk

◆ ANAMISC_BIF_CLK_REF_SEL_REG_REF_CLK_SEL_Pos

◆ ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Msk

◆ ANAMISC_BIF_CLK_REF_VAL_REG_XTAL_CNT_VAL_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Msk

◆ CACHE_CACHE_CTRL2_REG_CACHE_CGEN_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Msk

◆ CACHE_CACHE_CTRL2_REG_CACHE_CWF_DISABLE_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Msk

◆ CACHE_CACHE_CTRL2_REG_CACHE_EF_LEN_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Msk

◆ CACHE_CACHE_CTRL2_REG_CACHE_FLUSH_DISABLE_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_LEN_Msk

◆ CACHE_CACHE_CTRL2_REG_CACHE_LEN_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Msk

◆ CACHE_CACHE_CTRL2_REG_CACHE_MHCLKEN_DISABLE_Pos

◆ CACHE_CACHE_CTRL2_REG_CACHE_RAM_INIT_Msk