hw_pdm.h

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#ifndef HW_PDM_H_
#define HW_PDM_H_
 
 
#if dg_configUSE_HW_PDM
 
#include "sdk_defs.h"
#include "hw_src.h"
 
#define HW_PDM_CRG_REG_FIELD_MASK(reg, field)   REG_MSK(CRG_AUD, PDM_##reg##_REG, field)
 
#define HW_PDM_CRG_REG_FIELD_POS(reg, field)    REG_POS(CRG_AUD, PDM_##reg##_REG, field)
 
#define HW_PDM_CRG_REG_GETF(reg, field)         REG_GETF(CRG_AUD, PDM_##reg##_REG, field)
 
#define HW_PDM_CRG_REG_SETF(reg, field, val)    REG_SETF(CRG_AUD, PDM_##reg##_REG, field, val)
 
#define HW_PDM_CRG_REG_SET_BIT(reg, field)      REG_SET_BIT(CRG_AUD, PDM_##reg##_REG, field)
 
#define HW_PDM_CRG_REG_CLR_BIT(reg, field)      REG_CLR_BIT(CRG_AUD, PDM_##reg##_REG, field)
 
#define HW_PDM_SRC_REG_GETF(id, reg, field)         HW_SRC_REG_GETF(id, SRC1, reg##_REG, field)
 
#define HW_PDM_SRC_REG_SETF(id, reg, field, val)    HW_SRC_REG_SETF(id, SRC1, reg##_REG, field, val)
 
#define HW_PDM_SRC_REG_SET_BIT(id, reg, field)      HW_SRC_REG_SET_BIT(id, SRC1, reg##_REG, field)
 
#define HW_PDM_SRC_REG_CLR_BIT(id, reg, field)      HW_SRC_REG_CLR_BIT(id, SRC1, reg##_REG, field)
 
typedef enum {
        PDM_DIRECTION_INPUT,
        PDM_DIRECTION_OUTPUT
} HW_PDM_DATA_DIRECTION;
 
typedef enum {
        HW_PDM_SLAVE_MODE = 0, 
        HW_PDM_MASTER_MODE     
} HW_PDM_MODE;
 
typedef enum {
        HW_PDM_DI_NO_DELAY = 0, 
        HW_PDM_DI_4_NS_DELAY,   
        HW_PDM_DI_8_NS_DELAY,   
        HW_PDM_DI_12_NS_DELAY   
} HW_PDM_DI_DELAY;
 
typedef enum {
        HW_PDM_DO_NO_DELAY = 0, 
        HW_PDM_DO_8_NS_DELAY,   
        HW_PDM_DO_12_NS_DELAY,  
        HW_PDM_DO_16_NS_DELAY   
} HW_PDM_DO_DELAY;
 
typedef enum {
        HW_PDM_CHANNEL_NONE = 0,  
        HW_PDM_CHANNEL_R,         
        HW_PDM_CHANNEL_L,         
        HW_PDM_CHANNEL_LR         
} HW_PDM_CHANNEL_CONFIG;
 
typedef enum {
        HW_PDM_MUX_OUT_SRC1,          
        HW_PDM_MUX_OUT_SRC2,          
} HW_PDM_MUX_OUT;
 
typedef struct {
        /* PDM mode configuration is placed in mode specific structures */
        HW_PDM_MODE             config_mode;            
        HW_PDM_DI_DELAY         in_delay;               
        HW_PDM_DO_DELAY         out_delay;              
        HW_PDM_CHANNEL_CONFIG   output_channel;         
        bool                    swap_channel;           
        uint32_t                clk_frequency;          
        HW_PDM_DATA_DIRECTION   data_direction;        
} hw_pdm_config_t;
 
__STATIC_INLINE HW_PDM_DI_DELAY hw_pdm_get_input_delay(HW_SRC_ID id)
{
        return(HW_PDM_SRC_REG_GETF(id, CTRL, SRC_PDM_DI_DEL));
}
 
__STATIC_INLINE HW_PDM_DO_DELAY hw_pdm_get_output_delay(HW_SRC_ID id)
{
        return(HW_PDM_SRC_REG_GETF(id, CTRL, SRC_PDM_DO_DEL));
}
 
__STATIC_INLINE HW_PDM_CHANNEL_CONFIG hw_pdm_get_output_channel_config(HW_SRC_ID id)
{
        return(HW_PDM_SRC_REG_GETF(id, CTRL, SRC_PDM_MODE));
}
 
__STATIC_INLINE HW_PDM_MODE hw_pdm_get_mode(void)
{
 
        return(HW_PDM_CRG_REG_GETF(DIV, PDM_MASTER_MODE));
}
 
__STATIC_INLINE bool hw_pdm_get_status(void)
{
        uint32_t pdm_div_reg = CRG_AUD->PDM_DIV_REG;
 
        if (pdm_div_reg & REG_MSK(CRG_AUD, PDM_DIV_REG, PDM_MASTER_MODE)) {
                return true;
        }
 
        return(!!(pdm_div_reg & REG_MSK(CRG_AUD, PDM_DIV_REG, CLK_PDM_EN)));
}
 
__STATIC_INLINE uint8_t hw_pdm_get_clk_div(void) {
 
        return(HW_PDM_CRG_REG_GETF(DIV, PDM_DIV));
}
 
__STATIC_INLINE bool hw_pdm_get_in_channel_swap(HW_SRC_ID id)
{
        return(HW_SRC_REG_GETF(id, SRC1, CTRL_REG, SRC_PDM_IN_INV));
}
 
__STATIC_INLINE bool hw_pdm_get_out_channel_swap(HW_SRC_ID id)
{
        return(HW_PDM_SRC_REG_GETF(id, CTRL, SRC_PDM_OUT_INV));
}
 
__STATIC_INLINE void hw_pdm_enable(void)
{
        HW_PDM_CRG_REG_SET_BIT(DIV, CLK_PDM_EN);
}
 
__STATIC_INLINE void hw_pdm_disable(void)
{
        HW_PDM_CRG_REG_CLR_BIT(DIV, CLK_PDM_EN);
}
 
__STATIC_INLINE void hw_pdm_set_input_delay(HW_SRC_ID id, HW_PDM_DI_DELAY delay)
{
        HW_PDM_SRC_REG_SETF(id, CTRL, SRC_PDM_DI_DEL, delay);
}
 
__STATIC_INLINE void hw_pdm_set_output_delay(HW_SRC_ID id, HW_PDM_DO_DELAY delay)
{
        HW_PDM_SRC_REG_SETF(id, CTRL, SRC_PDM_DO_DEL, delay);
}
 
__STATIC_INLINE void hw_pdm_set_output_channel_config(HW_SRC_ID id, HW_PDM_CHANNEL_CONFIG channel_conf)
{
        HW_PDM_SRC_REG_SETF(id, CTRL, SRC_PDM_MODE, channel_conf);
}
 
__STATIC_INLINE void hw_pdm_set_mode(HW_PDM_MODE mode)
{
        HW_PDM_CRG_REG_SETF(DIV, PDM_MASTER_MODE, mode);
}
 
__STATIC_INLINE void hw_pdm_set_in_channel_swap(HW_SRC_ID id, bool swap)
{
        if (swap == true) {
                HW_PDM_SRC_REG_SET_BIT(id, CTRL, SRC_PDM_IN_INV);
        } else {
                HW_PDM_SRC_REG_CLR_BIT(id, CTRL, SRC_PDM_IN_INV);
        }
}
 
__STATIC_INLINE void hw_pdm_set_out_channel_swap(HW_SRC_ID id, bool swap)
{
        if (swap == true) {
                HW_PDM_SRC_REG_SET_BIT(id, CTRL, SRC_PDM_OUT_INV);
        } else {
                HW_PDM_SRC_REG_CLR_BIT(id, CTRL, SRC_PDM_OUT_INV);
        }
}
 
__STATIC_INLINE void hw_pdm_set_pdm_output_mux(HW_PDM_MUX_OUT output)
{
        // Set PDM_MUX_OUT field in SRC2 MUX register
        REG_SETF(SRC2, SRC2_MUX_REG, PDM_MUX_OUT, output);
}
 
__STATIC_INLINE HW_PDM_MUX_OUT hw_pdm_get_pdm_output_mux(void)
{
        // Get HW_PDM_MUX_OUT field in SRC2 MUX register
        return(REG_GETF(SRC2, SRC2_MUX_REG, PDM_MUX_OUT));
}
 
uint32_t hw_pdm_clk_init(uint32_t frequency);
 
void hw_pdm_init(HW_SRC_ID id, hw_pdm_config_t *config);
#endif /* dg_configUSE_HW_PDM */
#endif /* HW_PDM_H_ */